AC hot carrier stress
2.3 Comparison of LDMOS/MOS Characteristics
One of the purposes of measuring VI, as we have mentioned in section 2.1, is to compare the device characteristics in the channel region (intrinsic MOS) and in the LDMOS. The VI is designed with dimensions much smaller than the device width, and thus no significant influence is expected on the I-V characteristics. Fig. 2.7 plots a comparison of the ID-VD characteristics between the LDMOS and the metal contact LDMOS (new structure). A good matching of the ID-VD characteristics shows no significant difference between the LDMOS and the metal contact structure, which assures no process variation in the following measurements.
2.3.1 I-V Characteristics
To compare the I-V characteristics in the intrinsic MOS and in the LDMOS, a measurement setup is illustrated in Fig. 2.8. A current mode (I Mode) is used in SMU3 for the purpose of probing a voltage drop in the channel region. A comparison of the LDMOS (ID-VD) and the intrinsic MOS (ID-VI) is shown in Fig. 2.9. As VGis low (Fig. 2.9(a)), the I-V of the intrinsic MOS and the LDMOS in linear region and saturation regions are nearly the same. This feature implies that VIis close to VDand the LDMOS performance is dominated by the intrinsic MOS at low VG. A similar comparison of the characteristics of the intrinsic MOS and the LDMOS in the high-VG region is presented in Fig. 2.9(b). At small VD, the drain current of the intrinsic MOS and the LDMOS are very close, indicting that the intrinsic MOS still dominates the LDMOS characteristics in the linear region. However, a significant current difference is observed in the saturation region, implying a large voltage drop in the drift region. Thus, the saturation characteristics of the device are controlled by both the intrinsic MOS and the drift region. In addition, Fig. 2.9 also implies two saturation mechanisms in the LDMOS; one is a classic saturation mechanism that takes place in the intrinsic MOS [2.8], and the other is a quasi-saturation mechanism which is determined by the saturation of the drift region [2.6].
The characterization also leads to a possible LDMOS modeling technique: We
low-frequency noise performance, but with the introduction of the applications, such as high-voltage digital cells and operational amplifiers, the flicker noise behavior has become important [2.16]. In this section, we used the VI to characterize the flicker noise in the channel and drift regions. All noise measurements are biased at low VG
(VG <18V) in the linear region to assure that number fluctuation mechanism dominates the noise behavior. In order to have a reasonable comparison, we adjusted the applied voltage drop in the channel region and in the drift region, which allow us to obtain the same order of the current flow. The flicker noise measurement system includes an Agilent 4156 semiconductor parameter analyzer, a BTA 9603 FET noise analyzer, and a SR780 network signal analyzer. All measurement is controlled automatically through GPIB by using a computer program named Cadence-NoisePro.
Fig. 2.10 shows a flicker noise measurement at different applied VG. Each data point represents an average of 3 to 5 devices. As VGis low (Fig. 2.10(a)), the Sid of drift region is small, which is attributed to thermal noise. In addition, the Sid of LDMOS at low VG is nearly the same as the Sid of MOS, implying that the flicker noise of LDMOS at low VGis major determined by the channel-part of the LDMOS.
Compared to the I-V characteristics of Fig. 2.9(a), the ID-VI is close to the ID-VD at low VG and thus the channel region dominates the LDMOS behavior at low VG
regime. At a large VG(Fig. 2.10(b)(c)), the Sidof LDMOS appears to be controlled by both the channel region and the drift region. This feature is in agreement with the comparison of I-V characteristics in Fig. 2.9(b).
The measurement result of the flicker noise behavior also implies a new characterization method for hot carrier stress. By comparing the pre-stress and post-stress flicker noise at different VG, we can identify the locations of oxide damage area in the device and corresponding trap properties. This approach will be utilized and discussed in the chapter 3
2.4 Summary
A novel metal-contact LDMOS structure is fabricated to investigate self-heating effect and LDMOS/MOS characteristics. A new technique for self-heating characterization has been proposed. This approach can probe a self-heating induced VIchange directly without adding an external resistor. The two-stage behavior of a VI
transient is noticed for the first time and explained. This method provides a higher resolution than a conventional ID method. The characteristics of the channel part of the LDMOS, including the I-V characteristics and the flicker noise behaviors, are measured and compared to the LDMOS. Our measurement result shows that the drain current at low VG regime is major determined by the channel-part of the LDMOS, whereas the drain current at high VGregime is affected by both the channel region and the drift region. Similarly, the flicker noise behaviors at low VGregime and at high VG regime are controlled by the channel region and by both the channel region and the drift region, respectively.
Based on the comparison of the I-V characteristics, a new modeling methodology for LDMOS SPICE model is proposed. A two-component LDMOS model using the new methodology will be developed in chapter 5. In addition, we also proposed a noise characterization method to identify oxide damage area in various hot carrier stress modes. This method will be performed and discussed in chapter 3.
Fig. 2.1 Top view of a novel metal contact structure. Three different regions are indicated by Lch (channel region), Lacc (accumulation region), and LFOX (field-oxide region). A contact (VI) is placed in the accumulation region.
Field-Oxide
Fig. 2.2 Cross-section of the metal contact structure to characterize self-heating effect.
The cross-section is plotted from the line (A-A’) in Fig. 2.1. The metal contact (VI) is arranged in thebird’sbeak region with an n+implant.