Figs. 2-8(a) to (f) show typical ID-VG curves of the three types of structures and
two different pad materials. From the curves, we can see the slopes of the
“planar-thick” device in the linear region are the smallest, and those of the NW’s are
the largest. It means that if we use NW, the largest current difference can be obtained in a small change in VG. This is one of the reasons why we want to use the NW structures for sensor applications. To compare the characteristics more clearly, we
utilize the S.S. that is defined as below:
log
1. . D
G
S S I
V
(mV/dec). (2-6)
We can find that the mean S.S. of the NW is much smaller than that of the planar ones.
It is because NW channel has the largest surface-to-volume ratio, and the gate is more effective in control the turning on and off of the channel. Besides, the off-state leakage is dramatically reduced with ultra-thin channel thickness, as compared with the planar device with thick channel.
Moreover, from the figures, we can see the on/off ratio of the NW devices is the
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largest (~106) among the devices, while the planar devices with thick channel is the worst. This is because of the off leakage currents of the thick planar devices which is much larger than the other two structures as mentioned above. The gate is difficult to control the deeper portion of channel which is responsible for the off-state leakage.
Figs. 2-9(a) and (b) show the ID-VG curves of different structures and pad materials.
We can clearly see that the NW structure has the best performance among the test devices.
We also compare the mobility performance of the devices by measuring the field-effect mobility which is defined as,
field-effect mobility ( FE) m
D
where Cox is the gate oxide capacitance per unit area, W is the channel width, and Gm stands for the transconductance given by,
|
. larger than that of the thin planar ones. One of the possible reasons is the small grains size contained in the ultra-thin (~ 100 Å ) channel of the thin planar devices. In this case the top and bottom α-Si/dielectric interfaces are so close that the SPC process18
would be limited by the heterogeneous nucleation process at the interfaces and the grain size thus shrunk Figs. 2-11(a) and (b) are the schematic drawings to explain the phenomenon. For the case when the channel thickness is thin, as shown in Fig.
2-11(a), the grains size will be limited by the thickness, so mobility and the conduction current will suffer from more scattering with the grains boundaries than the case with a thick channel. Besides, although the original α-Si film thickness of NW devices (1000 Å ) is two times larger than that of the planar thick (500 Å ), the mobility is not much bigger. This is attributed to the fact that the portion of the final NW channel is near the side wall of the dummy structure, and generally the grains size near the interface is smaller than the outer part, thus the benefit of an increased grain size with increasing thickness is not significant. Figs. 2-12(a) and (b) are the variation of the mobility. We can see the mean value of the mobility is the best for NW even though the channel thickness is the smallest.
Next, we compare the deviation of threshold voltage among the different structures. Figures 2-13(a) to (f) are the ID-VG curves of fifteen devices measured from the three types of structures with various pad materials. The channel length of the devices was 2 µm, the channel width is 0.4 µm for planar and 65 nm for NW, and the channel thickness is 500, 100 and 400 Å for “planar-thick”, “planar-thin” and
“NW”, respectively. First, from the diagrams, we can clearly see that the variation is
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the worst for the thick planar devices, while the NW devices are the best. Figs. 2-14(a) to (c) and Figs. 2-15(a) to (c) are the mean Vt from different structures and pad materials with channel length of 1µm, 2µm and 5µm, respectively. Vt is defined as VG
at ID = W/L × 10 nA. The error bar in the figures represents the standard deviation in Vt. We can find the deviation shows the identical trend. That is, when the channel length increases, the deviation decreases. As mentioned before, discrete random dopant (or trap) in the depletion region of the channel plays a main role in affecting the threshold voltage deviation. Then, according to Eq. 2-4, the ΔVt will be proportional to WDEP, and inversely proportional to L and W. It seems that this phenomenon that we discovered can be well explained by the effect. In order to verify
this assumption, we plot ΔVt versus 1 / LW in Fig. 2-16. It means that the ΔVt for this effect will be only affected by WDEP, and proportional to it. First, we compare the thick and thin planar devices. Since the channel thickness of the fabricated devices is pretty thin (only 500 Å even for the “thick” planar split), WDEP is assumed to be the channel thickness. Because the thickness of thick planar devices is thicker than the thin planar ones, we can see the ΔVt of planar thick is bigger. It means that there are more ΔQDEP as the channel becomes thicker, so the ΔVt is larger. On the other hand, the channel in NW is of triangular column, so we can’t directly use the channel thickness to represent the WDEP. But we still can use the following formula to find out
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the average WDEP:
(average)
( ) ( )
DEP TRAP DEP TRAP CHANNEL TRAP DEP COVERED
Q qN W L W qN V qN W W L ,(2-9)
where VCHANNEL is volume of the channel, WDEP(average) is the average depletion width and WCOVERED is the gated channel width. Because it is fully depleted, the last term of the original formula can be represented by the volume of the channel. Then, we can utilize the channel surface area that is covered by gate to calculate the average WDEP. And we can find that the WDEP of NW is around 80 Å which is smaller than the thin planar ones, so we can get the smallest slope for NW in Fig. 2-16. In other words, NW has the best control over the threshold voltage variation.
We also compare the ΔS.S. among the different structures. Figures 2-17(a) and (b) show the mean value of S.S. and ΔS.S. of the test samples. The channel length of all samples is 2 µm. Again it can be seen that the thick planar device has the largest ΔS.S., and NW has the smallest deviation. As mentioned before, NW has the largest surface to volume ratio, which can increase gate coverage within finite channel region. The smallest mean value and standard deviation of S.S. with the NW split reflect this trend.
Finally, Table 2-1 summarizes of the conclusions in Chapter 2.
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