Complete loop simulation & layout

The architecture and simulation of each block are introduced in the previous sections. Now we combine all of them and carry out simulation. Figs. 33 & 34 show the settling time when fixing one channel and then sweep to another. The settling time is 80us for fixed channel, and V_ctrl needs 180us to achieve the stable condition when switch to another channel (divide number from 1568 to 1572). The layout of the synthesizer is shown as in Fig. 35.

Fig. 33 Settling time simulation with fix channel

Fig. 34 Settling time simulation when sweeping channel

Fig. 35 Layout of the synthesizer

Chapter 4

M EASUREMENT R ESULTS

During the measurement, we found a serious problem in the VCO so that the PLL can’t work successfully with this problem. In this chapter, we will find out the problem and use other methods to measure the frequency divider, the phase/frequency detector and the charge pump. Fig. 36 shows the die photo.

Fig. 36 Die photo

There are many pads of synthesizer chip, we usually measure it on PCB rather than on wafer, thus the order of pads doesn’t need to follow the G-S-G

(DC pad) or S-G-S (RF pad) rule. But during the frequency divider measurement, the clock signal must input from outside to substitute the VCO, and we don’t consider the order of pad at first. This makes us to input one RF signal (v_i −) with DC probe at first measurement. A DC probe doesn’t have good performance at high frequencies, for instance the reflection coefficient S11 is not low enough and there is a power mismatch problem between two input clocks of frequency divider. Thus, the layout is very critical, and we should fulfill the rule as possible as we can.

4.1 VCO measurement

During measuring the VCO, there is no oscillation at output and we measure the DC value of each part to figure out the problem. Fig. 37 marks all points that their voltages and currents can be measured.

Fig. 37 All measurable points of VCO

Control voltage and

Switch voltages of three banks

1.

When v_ctrl , v , _c1 v and _c2 v at floating, the current of VCO is about _c3 4.55mA; it is close to the simulation result (4.76mA), being enough to supply the VCO to oscillate.

2.

The DC voltage of the buffer output (V ) is 0.6V. Although it is a little higher _i than the simulation value (0.4V), but is still in the normal region.

3.

We connect v_ctrl to a power supply, to tune the varactors. When V was _dd turned on, we find that v_ctrl will increase with V if _dd V is higher than _dd 0.7V. v , _c1 v and _c2 v are also in the same situation. Thus we know the _c3 problem occurring at varactor.

4.1.1 What is the problem with varactor?

We have already understood that the problem comes from the varactor.

The voltage of v_ctrl shouldn’t change with V if the varactor is normal. We try _dd to use some methods to verify that the varactor is just like a resistor with very low resistance.

1.

We add a 1.3KΩ resister between v_ctrl and ground, the voltage of v_ctrl should be normally zero because the varactor is open at DC. But we observe the voltage changes from 0.707V to 0.681V. It indicates that the varactor behaves like a resister doing voltage divide.

2.

When we bias v ,_c1 v and _c2 v at 1.5V in order, _c3 v_ctrl will raise from 0.58V to 1.23V. It indicates that the varactor of each bank doesn’t work, so that

vctrl changes with them.

3

. The current of VCO is about 4.55mA when v ,_c1 v ,_c2 v and _c3 v_ctrl are all floating. After they are connected to a power supply with 0V, the output current lifts to 10.1mA or more. This demonstrates that there is a DC current path flowing through the varactor to the ground so as to increase the current.

4.

There are only probe pads at vop and von , but we use special instrument to measure their DC voltages and find vop rises from 0.707V to 0.93V when v_ctrl is connected to a power supply.

5.

The resistance between v ,_c1 v ,_c2 v and _c3 v_ctrl should be very large (several MΩ ). But we use an electrical meter to measure it and find out the resistance is 23Ω,21.3Ωand 20.3Ω between v_ctrl and v ,_c1 v ,_c2 v . It is _c3 very low and just likes a small resistor

All chips have the same problem so that the PLL can’t work successfully since the VCO can not oscillate. As we can’t measure the loop performance, we try to use other methods to verify other parts of the chip, and this problem will be discussed later.

4.2 Frequency divider measurement

As described before, there is no oscillation at VCO output, and thus no

input signal at the frequency divider. We try to input signal to the frequency divider from outside and probe each pad of the divider to see if it works successfully or not. We bond wire von and vop ,and input them from SMA to avoid the mismatch problem. Fig. 38 is the photograph of PCB.

Fig. 38 PCB of frequency divider measurement

The total current consumption of the frequency divider is 4.4mA (6.6mW), being a little smaller than the simulation value (7.32mW).

During measurement, we use a spectrum analyzer (Aglient E4407B), a signal generator (Aglient E8247C) and a probe station, Fig. 39 shows their photographs.

Fig. 39 Photograph of instruments

We set the input signal frequency at 1.57GHz, its power level is 0dBm and the DC voltage is 0.85V. Then we probe the 11x11um probe pad of each stage as illustrated in Fig. 40.

Fig. 40 Probe pad photo

The probe pad is very important for circuit debug whose structure was shown in Fig. 41. If there is no probe pad in the circuit, we never know any part will work or not. Like vop and von, these two probe pads let us know the DC variation after connecting v_ctrl with power supply, and probe pads at the frequency divider let us know the output frequency of each stage. There are also probe pads at PFD. The size of these probe pads are 11x11um , but the ² minimum size of the hard probe used in CIC is 12x12um , which is a little ² bigger than the probe pad, and is difficult to be used. Therefore, we should increase the size of the probe pad to 12x12um . ²

Fig. 41 Probe pad diagram

Figs. 42 and 43 show the spectrum of the first stage output of frequency divider. We set it at divide-by-2 and divide-by-3 model, respectively, and get a frequency at 785MHz and 525MHz. Because the input RF signal is very strong, the probe also receives it and has a peak at 1.57GHz shown at spectrum analyzer.

Fig. 42 First stage sets to divide-by-2 model

Fig 43 First stage sets to divide-by-3 model

The spectrum of the second stage output of frequency divider was shown in Figs. 44 and 45. Fig. 44 is the spectrum when only first stage is set to divide-by-3 model and Fig.45 is the spectrum when both of them are set to divide-by-3 model.

Fig. 44 Only the first stage is set to divide-by-3 model

Fig. 45 Both of the first and the second stage are set to divide-by-3 model

The divisor N of the programmable divider is from 1024 to 2047 controlled by b to ₀ b , ₉ b is always set to high and ₉ b ,₇ b ,₆ b₄,b are always ₃ set to low. Figs. 46 and 47 are the spectrum when N=1536 and 1575.

Fig. 46 Output spectrum when divide-by-1536

Fig. 47 Output spectrum when divide-by-1575

4.3 PFD and charge pump measurement

When measuring PFD and charge pump, we input the clock signals from SMA at first, after frequency dividing, the signal f_div is sent to the PFD and compares with the reference clock f_ref to generate the up/down signal, then sent to charge pump. Fig. 48 is the spectrum of the reference oscillator, from the spectrum analyzer, we know that the oscillator generates square wave, and has so many side lobes.

Fig. 48 The spectrum of the reference oscillator

We try to measure the waveform of the charge pump current, but the oscilloscope can only display the voltage waveform. Thus we connect the loop filter and use a multimeter to measure its DC voltage. If N=1536,

fdiv=1.022MHz, it is always higher than f_ref , then the I will pull down the _cp VCO frequency during the very short time, and we measure the voltage is 0V

(Fig. 49).

Fig. 49 f_div is higher than f_ref ,V_ctrl is pulled down to 0V

On the contrary, if we set N=1575, f_div=0.996MHz, VCO frequency will be pulled up, and voltage is raised to 1.5V (Fig. 50). In this figure, we know that PFD compares f_div with f_ref to generate an up/down signal every 1u sec, so that there is a little pulse at charge pump output waveform. In spectrum, this is what we called “spur noise”. The peak-to-peak voltage is 122mV, and I is _cp 122uA under the DC 1MΩ load condition.

Fig. 50 f_div is lower than f_ref , V_ctrl is pulled up to 1.5V

Then we change the input frequency to 1536MHz and 1575MHz, f_div is equal to f_ref , the voltage is 0.654V when N=1536 and 0.886 when N=1575.

The current consumption of the charge pump is 0.5mA (0.75mW), and the power consumption of PFD is less than 1mW. Table. 6 is the summary of the power consumption.

1us

Simulation measurement

VCO 7.14mW 6.8mW

Frequency divider 7.32mW 6.6mW

Charge pump

PFD <<1mW <<1mW

Whole chip 15.1mW 14.1mW

Table. 6 Power consumption summary

4.4 Discussion

The simulation and measurement results of power consumption are very close, and all parts work successfully except the VCO. The previous measurements use a signal generator to generate the clock signal for the frequency divider. Signal power and frequency can be fully controlled, but since it is not a close loop, the loop settling time can’t be measured without a control voltage feedback to the VCO. The frequency divider still works even we input the clock signals from SMA. It seems that we can use another VCO to substitute the on-chip one, which has the same frequency and tuning range.

But it is hard to find a single VCO chip because most of the design houses sell a whole module instead of a single VCO chip. The GPS system operates at 1.57GHz, it is not a common specification, in contrast 900MHz, 1800MHz or 2.4GHz VCO is easier to find. If we find such a VCO is available, the whole

loop can be set up as illustrated in Fig. 51. The practical PCB layout would be constructed after concerning about the arrangement of the external VCO pads.

Fig. 51 Loop diagram with external VCO

Chapter 5

C ONCLUSIONS A ND

F UTURE P ROSPECTS

The measurement results are described previously, and due to the problem with varactor, we can’t measure the VCO phase noise and loop settling time. In this chapter, we discuss the possible reasons and learn some useful experiences in this tape out, and then build the future prospects.

5.1 Conclusions

The varactor model is supplied from TSMC, and was used in previous tape out, thus the model is correct. Additionally, DRC and LVS of the layout were also verified. Thus, the problem may come from fabrication.

All parts of the synthesizer work successfully except the VCO. The frequency divider divides the input frequency accurately, PFD can compare with f_div and f_ref to generate the corresponding up/down signals, charge

pump generates the current I and transfers into _cp V_ctrl after loop filter. The measurement of power consumption is 14.1mW with 1.5V supply voltage, it is very low power and achieve our design purpose.

5.2 Future Prospects

In the design of VCO, a start-up circuit can be integrated into the VCO architecture in future tape out to ensure that the circuit can start to oscillate.

The start-up circuit will turn off automatically to save power after VCO starting to oscillate. In simulation, we should add the bond wire effect into it, the parasitic inductance is about 1nH per 1mm, and we should enlarge the simulation range of the resister variation to 10%. Furthermore, the RF output pad must be close to the circuit, the metal line should be as wide as possible and less corner is desirable to reduce parasitic inductance. These design considerations are helpful to design a successful frequency synthesizer in high frequency region.

R EFERENCE

[1]Derek K. Shaeffer, Stanford University, Thomas H. Lee, Stanford University,

“The Design and implementation of low-power CMOS radio receivers”

KLUWER ACADEMIC PUBLISHERS

[2] Farbod Behbahani, Member, IEEE, Hamid Firouzkouhi, Member, IEEE, Ramesh Chokkalingam, Siamak Delshadpour, Alireza Kheirkhahi, Mohammad Nariman, Student Member, IEEE, Matteo Conta, and Saket Bhatia “A fully integrated low-IF CMOS GPS radio with on-chip analog image rejection”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002

[3] Giampiero Montagna, Giuseppe Gramegna, Ivan Bietti, Massimo Franciotta, Member, IEEE, Andrea Baschirotto, Senior Member, IEEE, Placido De Vita, Roberto Pelleriti, Mario Paparo, Member, IEEE, and Rinaldo Castello, Fellow, IEEE “A 35-mW 3.6mm Fully Integrated 0.18-um CMOS GPS ² Radio”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 7, JULY 2003

[4] Valence Semiconductor , Inc. VS7001 “A GPS front end downconverter”

JAN 2002

[5] Hamid R. Rategh, Tavanza, Inc., Thomas H. Lee, Stanford University,

“ Multi-GHz frequency synthesis & division, Frequency synthesizer design

for 5GHz wireless LAN systems”

[6] Ali Hajimiri, Thomas H. Lee, Center for Integrated Systems, Stanford, CA 94305-4070, USA “Phase noise in CMOS differential LC oscillators”, IEEE 1998

[7] D. B. Leeson, “A simple model of feedback oscillator noise spectrum”, Proc.

IEEE, pp. 329-330, Feb. 1966.

[8] F. M. Gardner, “Phase lock Techniques”, New York, NY: John Wiley & Sons, 1979.

P UBLICATION R EMARKS

1. VLSI-2004 (Las-Vegas, USA) 2. PIERS 2004 (Nanjing, China)

在文檔中 全球定位系統專用低功率整數N頻率合成器 (頁 49-0)