Noise in PLL loops

There are several noise sources in a PLL. The three main noise sources are that of the VCO phase noise

φ

_nv, noise of the reference signal

φ

_ni and the noise due to the phase detector

φ

_nd. Fig. 9 shows the linear PLL model with these three noise sources added.

Fig. 9 The linear PLL model with noise added

We begin to discuss the influence caused by each noise. We derive the

output phase noise

φ

_o due to each noise source respectively and add them afterwards. The result is written as :

Ms

noise mainly comes from the reference oscillator and the phase detector, and the noise amplification factor approximately equals to the frequency multiplication of the PLL.

At high frequencies: _nv

vco

1 , which reveals that the main noise contribution comes from the VCO phase noise.

In summary, PLL noise is dominated by the reference oscillator and the phase detector at low frequencies and by the VCO phase noise at high frequencies. Fig. 10 shows the simplified profile of the phase noise at the output of PLL.

Fig. 10 Phase noise contributions in a PLL

Chapter 3

F REQUENCY S YNTHESIZER

In multi-frequency wireless transceivers, frequency synthesizer is an essential part to perform channel switching. Among many different frequency synthesis techniques, the dominant method used in wireless communication industry is the digital PLL circuit, and “Integer-N” frequency synthesizer is widely adopted. Referring to the noise consideration we discussed in the last chapter, the integer-N type has an unavoidable disadvantage that the frequency multiplication (by M) raises the phase noise level by 20log(M dB. ) In order to improve the phase noise, “Fractional-N” type frequency synthesizer was introduced. According to its name, this type makes the output frequency

fVCObe fractional times to the reference frequency f_ref and therefore decline the phase noise. The main advantage of the integer-N type is its functionality, low power, space saving, economy and short settling time. As low current and low power consumption is the important issue in commercial applications, I choose the integer-N type frequency synthesizer in this thesis. Fig. 11 is the architecture of the Integer-N type frequency synthesizer to be designed.

Fig. 11 “Integer-N” PLL architecture

In this architecture, the programmable frequency divider is from 1024 to 2047 and the reference frequency is 1MHz. The design consideration and simulation results of each block are shown in the following sections.

3.1 VCO Design

3.1.1 Complementary & All-NMOS Couple pair VCO

In VCO design, there are three kinds of architecture: voltage controlled crystal oscillator, LC-tank oscillator and ring oscillator. Because of its low phase noise and easy integration, LC-tank oscillator is suitable for RF circuit design.

Fig. 12 shows two typical LC-tank oscillators. The first one uses NMOS and PMOS cross-coupled pairs (Complementary cross-coupled pair) to provide negative-G and the other employs all-NMOS cross coupled pair. The _m

complementary topology uses just one inductor in parallel with varactors to build the LC-resonator instead of two inductors in parallel to signal ground. In both structures, MOS cross-coupled pair is an active part to compensate for the losses of inductor and capacitor.

Fig. 12 Two typical LC-tank oscillator structures

There are several reasons that the complementary structure is superior to the all-NMOS structure: [6]

1.

The complementary structure offers better rise and fall time symmetry. It makes low upconversion of 1/f noise and other low frequency noise sources.

2.

The complementary structure offers higher transconductance for a given current, which results in a better start-up behavior.

Complementary Coupled pair VCO

All-NMOS

Coupled pair VCO

3.

The DC voltage drop across the channel in the all-NMOS structure is larger since the DC voltage of drain is V_dd .This results in stronger velocity saturation.

4.

The complementary structure also exhibits better phase noise performance for all bias points illustrated in Fig. 13.

As long as the oscillator operates in the current limited regime, the tank voltage swing is the same for both oscillators. However if we desire to operate in the voltage limited region, the all-NMOS structure can offer a larger voltage swing.

Fig. 13 Phase noise simulation results for both structures

3.1.2 Design for Low Power and Low Phase Noise

In wireless communications, low power and low noise are very critical, so All-NMOS

Complementary

does in VCO design. Fig. 14 is the description of LC resonator tank where R represents the loss of capacitor and inductor.

Fig. 14 Basic LC resonator tank

Using the energy conservation theorem, the maximal energy stored in the inductor is equal to the maximal energy stored in the capacitor:

2

The peak loss in the tank is written as

2

From these equations, for the unavoidable series resistance in the resonance tank, one can increase the inductance in order to decrease the power loss.

In 1996, Leeson [7] derived the following expression for the single-side band phase noise power spectral density of an LC-tank VCO as:

2 frequency offset, F is called the device excess noise factor or simply noise factor, k is the Boltzmann’s constant and T is the absolute temperature. Eq.

(10) shows the obvious way to reduce phase noise is to increaseP_sig ∝V_peak² , and the most efficient way is increasing the Q factor of the tank. According to the Barkhausen oscillation criterion, the phase stability definition for Q is more appropriate for oscillator application. The phase stability quality factor is defined as improving phase noise. But there is a tradeoff between L/C ratio and tuning range, so one should decide the maximum L/C ratio according to its minimum tuning range which the system can tolerate.

From above, we make Table. 4 and design our R, C value to optimize low power and low phase noise in the specified center frequency.

Low Power Low Phase Noise

Inductor (L) Maximize Maximize

Capacitor (C) Minimize Minimize

Resister (R) Minimize Minimize

Amplitude (V_peak ∝ P_sig^1/2) minimize maximize

Table. 4 Low-Power & Low-Phase noise Optimization Summary

3.1.3 Architecture and Simulation

As described before, there are several advantages inherent in the complementary topology. So we take it to realize our VCO. Fig.15 is the complete circuit with VCO, bank sets and output buffers.

Fig. 15 VCO architecture with bank sets and output buffer

V

_ctrl

In VCO design, one should design the ratio between NMOS and PMOS in the complementary structure carefully. It is about 3:1 to ensure the symmetry of rising time and falling time. LC tank design should follow the low power and low phase noise design issue. Accordingly, larger inductor should be chosen to enhance the Q factor of the tank, and we can get capacitor value with

w_c LC1

= . A PMOS current source bias at V in the top can regulate the _b current flow into VCO and decrease V_DD sensitivity. V_DD is 1.5V to reduce power consumption and obtain better phase noise. Referring to Fig. 16, it is shown that a lower supply voltage has better noise performance. To avoid the manufacture variation and lack of tuning range due to small

CL ratio, we adopt three sets of varactor bank to compensate for it.

Fig. 16 The measured phase noise vs. V_DD and Isupply for complementary LC oscillator

The simulated VCO transient result and the corresponding FFT simulation are shown in Fig. 17. Fig. 18 is its FFT simulation. We see that the output swing of VCO is 1.33 Vp-p and the swing is reduced to 0.28 Vp-p after buffer. The DC value of the output buffer is about 0.4V, being too low to push the frequency divider. Thus we raise the buffer output to 0.85V and then send the signal to the next stage.

Fig. 17 VCO transient simulation

Fig. 18 VCO FFT simulation

Fig. 19 shows the tuning range of VCO. In our design, it has 50MHz tuning range from 1.55 to 1.60GHz (3.1%). A narrow tuning range will decline the frequency sensitivity to the control voltage (V_ctrl) and decrease the settling time.

In this design,K_VCO is about 33.3MHz/V.

Fig. 19 VCO tuning range simulation

Phase noise simulation result is shown as in Fig. 20. At 100 KHz and 600 KHz offset from the carrier, phase noise is -102dBc/Hz and -119dBc/Hz, respectively. Table. 5 is the simulation results of VCO:

Fig. 20 VCO phase noise simulation

Power consumption (with puffer) 7.14mw

Supply voltage 1.5V

Tuning range 1.55~1.6GHz (3.1%)

Phase noise -102dBc/Hz@100K,-119dBc/Hz@600K

Table 5 VCO specification summary

3.2 Frequency Divider Design

In the frequency divider design, we intend to divide the VCO frequency down to 1MHz of reference frequency. Our VCO frequency is about 1.57GHz, and we construct the programmable divider by ten divide-by-2/3 stages which were shown in Fig. 21. The dividing ratio is from 1024 to 2047. b to _o b are ₉ control bits that switch each stage to divide-by-2 or divide-by-3 mode by changing the input level of each bit. Programmable divisor is given as

∑

=

Fig. 21 Frequency divider architecture

As illustrated in the figure, each divide-by-2/3 stage consists of two D-flipflops, an AND gate and an OR gate. Fig. 22 shows the block diagram of each D-flipflop made of two D-latches and one inverter.

Fig. 22 Block diagram of a master-slave D-flipflop

The maximum operation frequency of divider is determined by the speed of D-latches. At low frequencies, CMOS logic is desirable. However, at high frequencies Source Coupled Logic (SCL) is more suitable because of its high speed and low power consumption. Fig. 23 shows the SCL D-latch structure.

Constructed by SCL D-latch

Fig. 23 SCL D-latch structure

The first two stages of the frequency divider must operate at high frequencies (GHz or hundreds MHz) and CMOS logic circuit can’t handle them.

We carry out SCL D-latch structure as shown in Fig. 24. These stages are realized in a differential SCL and logic gates are embedded in it, whose speed will be restricted by the parasitic capacitor. If the parasitic capacitor is too large, voltage of n₁and n₂ can’t be charged promptly and the divider function will be seriously affected. To avoid this problem, layout must be very careful.

Fig. 24 Differential Source Coupled Logic

Fig. 25 is the VCO& frequency divider simulation results. We set VCO DC voltage at 0.85V to ensure gate voltage of each input MOS (input ck in Fig. 24) be high enough and operate accurately. VCO frequency (CK) is divided by 1568 and the output frequency (FDIV) is about 1MHz, being very close to the reference frequency.

1us

Fig. 25 VCO& Frequency divider simulation result

With variation during fabrication, the frequency of VCO may drift to the higher frequency range, so in our simulation we should guarantee this divider still work at 1800MHz. In the power consumption issue, because we use SCL logic and low supply voltage, it only consumes 7.32mW.

3.3 Phase/Frequency Detector Design

In phase frequency detector design, three-state detector is widely used because: it’s linear range is ±2π radians, being wider than ± of two-state, π and it can be used as frequency and phase detector. So it is taken in our design and is illustrated in Fig. 26.

Fig. 26 Phase/Frequency detector architecture

In this work, we use the falling edge trigger module. f_ref is an 1MHz off-chip oscillator output frequency. When the falling edge of f_ref arrives

before the falling edge of f_div, VCO frequency must be raised up to catch f_ref , and the output upp will be set (Refer to Fig. 27). On the other hand, if the falling edge of f_div arrives prior to the falling edge of f_ref , it represents that VCO is faster than the reference signal and should be slow down. In this case dwp will be set (Refer to Fig. 28). However, this PFD has a serious limitation for

its “dead zone”. Dead zone causes jitter in PLL and should be removed. For this purpose, we add two inverters to form a delay chain in the reset path, thereby generating enough delay to eliminate the dead zone of PFD [8].

Fig. 27 f_ref is faster than f_div and upp is set

Fig. 28 f_divis faster than f_ref and dwp is set

3.4 Charge Pump Design

3.4.1 Single-Ended & Differential Charge Pump

Single-ended charge pumps are popular since they don’t need loop filters and offer low power consumption with tri-state operation. Fig. 29 shows a single-ended charge pump with switch at drain.

A fully differential charge pump (Fig. 30) has several advantages over the conventional single-ended charge pump.

1.

Switch mismatches between NMOS and PMOS doesn’t substantially affect the overall performance.

2.

This configuration doubles the range of output voltage compliance compared with the single-ended charge pump. For low voltage operation (1.5V in our design), the limited output voltage range will restrict the tuning range of VCO.

3. The differential output stage is less sensitive to the leakage current since the leakage current behaves as a common-mode offset with the dual output stages.

4. The differential charge pump with two loop filters provides better immunity to the supply, ground and substrate noise when on-chip filters are used.

Fig. 29 Single-ended charge pump with switch at drain

3.4.2 Architecture and Simulation

Owing to the above considerations, we choose a differential, three-state charge pump in our design. The three-state gives an output current ± or I_p zero, depending on the control signals from the phase detector. And it is

followed by a passive loop filter that translates the output current I to the _cp control voltage V_ctrl of VCO. The structure consists of three parts: the current source, the current sink and switches as illustrated in Fig. 30.

Fig. 30 Differential charge pump architecture

In Fig. 30, M1 through M4 and the current source can offer a fixed current to the switches. These switches are controlled by upp , upn , dwp and dwn generated from phase detector whereas two them form of a complementary pair. These complementary signals can assure the current always flow through M2 and M4. When upp and dwnare set, the current flows into the loop filter, and current flows out of the loop filter when dwp and upn are set (refer to Fig. 30). This can also reduce the switch noise. According

to our design, the simulation of current I is about 115uA (shown in Fig. 31) _cp and the corresponding power consumption is 0.64 mw.

M1 M2

M3 M4 Up

Up

Down Down

Fig. 31 The simulation of Icp when upp and dwp are set

3.5 Loop Filter Design

As discussed in chapter 2, loop filter has close relationship with PLL behaviors. In our design, we choose a second-order passive loop filter and practice it off-chip to minimize chip size. The architecture is shown as below.

Fig. 32 Passive loop filter architecture

3.6 Complete Loop Simulation & Layout

The architecture and simulation of each block are introduced in the previous sections. Now we combine all of them and carry out simulation. Figs. 33 & 34 show the settling time when fixing one channel and then sweep to another. The settling time is 80us for fixed channel, and V_ctrl needs 180us to achieve the stable condition when switch to another channel (divide number from 1568 to 1572). The layout of the synthesizer is shown as in Fig. 35.

Fig. 33 Settling time simulation with fix channel

Fig. 34 Settling time simulation when sweeping channel

Fig. 35 Layout of the synthesizer

Chapter 4

M EASUREMENT R ESULTS

During the measurement, we found a serious problem in the VCO so that the PLL can’t work successfully with this problem. In this chapter, we will find out the problem and use other methods to measure the frequency divider, the phase/frequency detector and the charge pump. Fig. 36 shows the die photo.

Fig. 36 Die photo

There are many pads of synthesizer chip, we usually measure it on PCB rather than on wafer, thus the order of pads doesn’t need to follow the G-S-G

(DC pad) or S-G-S (RF pad) rule. But during the frequency divider measurement, the clock signal must input from outside to substitute the VCO, and we don’t consider the order of pad at first. This makes us to input one RF signal (v_i −) with DC probe at first measurement. A DC probe doesn’t have good performance at high frequencies, for instance the reflection coefficient S11 is not low enough and there is a power mismatch problem between two input clocks of frequency divider. Thus, the layout is very critical, and we should fulfill the rule as possible as we can.

4.1 VCO measurement

During measuring the VCO, there is no oscillation at output and we measure the DC value of each part to figure out the problem. Fig. 37 marks all points that their voltages and currents can be measured.

Fig. 37 All measurable points of VCO

Control voltage and

Switch voltages of three banks

1.

When v_ctrl , v , _c1 v and _c2 v at floating, the current of VCO is about _c3 4.55mA; it is close to the simulation result (4.76mA), being enough to supply the VCO to oscillate.

2.

The DC voltage of the buffer output (V ) is 0.6V. Although it is a little higher _i than the simulation value (0.4V), but is still in the normal region.

3.

We connect v_ctrl to a power supply, to tune the varactors. When V was _dd turned on, we find that v_ctrl will increase with V if _dd V is higher than _dd 0.7V. v , _c1 v and _c2 v are also in the same situation. Thus we know the _c3 problem occurring at varactor.

4.1.1 What is the problem with varactor?

We have already understood that the problem comes from the varactor.

The voltage of v_ctrl shouldn’t change with V if the varactor is normal. We try _dd to use some methods to verify that the varactor is just like a resistor with very low resistance.

1.

We add a 1.3KΩ resister between v_ctrl and ground, the voltage of v_ctrl should be normally zero because the varactor is open at DC. But we observe the voltage changes from 0.707V to 0.681V. It indicates that the varactor behaves like a resister doing voltage divide.

2.

When we bias v ,_c1 v and _c2 v at 1.5V in order, _c3 v_ctrl will raise from 0.58V to 1.23V. It indicates that the varactor of each bank doesn’t work, so that

vctrl changes with them.

3

. The current of VCO is about 4.55mA when v ,_c1 v ,_c2 v and _c3 v_ctrl are all floating. After they are connected to a power supply with 0V, the output current lifts to 10.1mA or more. This demonstrates that there is a DC current path flowing through the varactor to the ground so as to increase the current.

4.

There are only probe pads at vop and von , but we use special instrument to measure their DC voltages and find vop rises from 0.707V to 0.93V when v_ctrl is connected to a power supply.

5.

The resistance between v ,_c1 v ,_c2 v and _c3 v_ctrl should be very large (several MΩ ). But we use an electrical meter to measure it and find out the resistance is 23Ω,21.3Ωand 20.3Ω between v_ctrl and v ,_c1 v ,_c2 v . It is _c3 very low and just likes a small resistor

All chips have the same problem so that the PLL can’t work successfully since the VCO can not oscillate. As we can’t measure the loop performance, we try to use other methods to verify other parts of the chip, and this problem will be discussed later.

4.2 Frequency divider measurement

As described before, there is no oscillation at VCO output, and thus no

input signal at the frequency divider. We try to input signal to the frequency divider from outside and probe each pad of the divider to see if it works successfully or not. We bond wire von and vop ,and input them from SMA to avoid the mismatch problem. Fig. 38 is the photograph of PCB.

Fig. 38 PCB of frequency divider measurement

The total current consumption of the frequency divider is 4.4mA (6.6mW), being a little smaller than the simulation value (7.32mW).

The total current consumption of the frequency divider is 4.4mA (6.6mW), being a little smaller than the simulation value (7.32mW).

在文檔中 全球定位系統專用低功率整數N頻率合成器 (頁 25-0)