Complexity and power reduction summary

Figure 5.9 shows the complexity reduction of CFO estimation and power reduction of proposed frequency synchronizer respectively. The complexity of proposed data-partition can be reduced to 25% of conventional estimation approach. If we combine the method of power-aware, the complexity can be reduced more 15% in low SNR, and 23% in high SNR.

Besides, the power of proposed data-partition can be reduced to 40% of conventional frequency synchronizer. If we combine the method of power-aware, the power can be reduce more 10.3% in low SNR, and 16.5% in high SNR.

0 5 10 15 20

0 5 10 15 20 25 30 35

SNR [dB]

Complexity [%]

Data-partition

Data-partition+Power-aware

0 5 10 15 20

20 25 30 35 40 45 50

SNR [dB]

Proposed design power [%] Data-partition

Data-partition+Power-aware

Complexity of CFO estimation [%]

15% 23% 10.3% 16.5%

Figure 5.9 Complexity and power reduction

Chapter 6.

Hardware Implementation

In this chapter, we will introduce the platform based design flow. The architecture of the proposed design, hardware synthesis information and chip summary will be shown in the following sections.

6.1 Design Methodology

The trend of IC technology is towards to System-on-Chip (SoC). System-level simulation becomes very important in today’s design flow. Our design methodology from system simulation to hardware implementation can be shown in Figure 6.1.

Matlab platform

Algorithm verification Fixed-point design

Verilog HDL Coding Gate-level Synthesis Circuit-level Implementation

Channel model

Wordlength Analysis

Verilog Test Bench

Circuit Test Bench System built-up

Figure 6.1 Platform-based design methodology

First, the system platform with channel modals should be established according to the system specification, which ensures the design in the practical condition. Algorithm and architecture developments of each function block should be verified in the system platform to ensure the whole system performance. Fixed-point simulation is applied before hardware implementation to make a trade-off between system performance and hardware cost. An example of the word-length distribution analysis can be shown in Figure 6.1.2. Based on the signal distribution analysis and the PER simulation, a reasonable word-length of each signal can be decided. In hardware implementation, the HDL modules are verified with the test benches dumped from the equivalent Matlab blocks to ensure the correctness.

(a) (b)

Figure 6.2 (a) Signal distribution analysis (b) PER analysis of different word-length

6.2 The High-Speed and Low-Complexity Frequency Synchronizer for UWB Systems

6.2.1 Architecture of the Proposed Frequency Synchronizer

The architecture of the proposed frequency synchronizer is shown in Figure 6.3. It’s developed based on the proposed algorithms with λ = 4. Since the needed computation rate of equation (4.4) and (4.6) can be reduced to 1/λ of equation (4.3) and (4.5) respectively, the proposed design can work on 528MHz/4 = 132MHz low clock frequency. Before CFO estimator, data-partition controller selects one input sample from four data paths in each clock cycle. To avoid burst noise or serious interference causing CFO estimation failure, twice CFO estimation is applied. And a memory is used to store ^2×

⎣

^{N λ}

⎦

= 82 samples. Then CFO is estimated after arc-tangent circuit. Since calculation rate of compensating phasor is reduced by equation (4.6), the proposed CFO compensator can work with single phase accumulator (ACC) and single phase-to-I/Q lookup table (LUT) at 132MHz clock frequency. The needed parallel part is only the complex multipliers to compensate the received FFT symbols of preamble and data signal. Based on data partition and approximate phasor compensation scheme, the proposed design can achieve 528MS/s throughput through a single architecture with parallel multipliers at 132MHz clock frequency.

The detail architecture of the proposed CFO estimator is shown in Figure 6.4. According to this figure, we can see that, the register-files are used instead of the memory because only 82 samples that are 656 bits (4-bits x 82-samples x 2-I/Q) needed to be stored. If we used memory to store the samples, compare with the register files, the required area and power consumption will be enlarged. Besides, consider about dynamic power consumption issue, we denied the shift registers to store the samples, even if its area is smaller than register-files.

Data partition

Coarse Est ./Fine Est.

Control

Figure 6.3 Architecture of proposed frequency synchronizer

MUX

Figure 6.4 Detail architecture of proposed CFO estimator

The detail architecture of the proposed CFO compensator is shown in Figure 6.5(a) and its mapping diagram of sine and cosine is shown in Figure 6.5(b). The sine and cosine generator is designed using lookup table. Both the two function have the same property. The value in the first quadrant can be mapped onto other quadrants by simple sign transformation. Another property is that the values of sine or cosine can be transformed to each other. Generally, we can only build the first quadrant table of sine function and get the cosine values using the mapping function. In the system, however, the sine and cosine generator is used to generate complex values. The relative values have to be accessed at the same time for an angle. If the table only contains the sine values, there must be two accesses for a complex value. In our design, we build a table which contains the sine and cosine values, and we can produce a complex value using an access. The input range of the table is half of the previous. If the input angle is larger than the 45⁰, exchange the output values of sine and cosine. Besides, the complexity of lookup table can be reduced because of the approximate CFO compensation scheme.

A conventional approach based on equation (4.3) and (4.5) is shown in Figure 6.6. It uses parallel-4 architecture to achieve 528MS/s throughput in 132MHz clock frequency. Compared with the parallel approach, the proposed design can reduce 75% memory size and complex multiplications. Implementation result will show the proposed design can efficiently reduce hardware cost and power consumption.

MUX (b) Mapping diagram of sine and cosine

Σ

Figure 6.6 Conventional parallel architecture

6.2.2 Hardware Synthesis

The equivalent gate-count of the proposed design and the power consumption measured by post-layout simulation are listed in Table 6.1 and Table 6.2 respectively. Compared with the conventional parallel approach as shown in Figure 6.6, the proposed design combining with the data-partition-based, power-aware CFO estimation and approximate CFO compensation scheme can reduce 59% gate count and 69.4 ~ 75.6% power consumption.

Table 6.1 Equivalent gate-count of UWB frequency synchronizer Gate-count CFO estimator CFO compensator Total Conventional

parallel design 41K 20K 61K

Proposed

design 11K 14K 25K

Reduction

Percentage 49.2% 9.8% 59%

Table 6.2 Power of UWB frequency synchronizer (528MS/s)

Power (mW) CFO estimator CFO compensator Total

Conventional

parallel design 41.3 16.2 57.5

Proposed

design 0.9 ~ 4.2 13.1 23.5

Reduction Percentage

64 ~ 70.2%

(data-partition +power-aware) 5.4% 69.4 ~ 75.6%

6.3 UWB Baseband Processor

Figure 6.7 shows the micro-photo of the LDPC-COFDM UWB baseband processor integrating the proposed design in standard 0.18µm CMOS process. Its features also listed in

Table 6.3. Measured result shows 21.4mW power is consumed by the proposed 528MS/s frequency synchronizer.

1.16 mm

0.79 mm 1.21mm

1.07 mm 0.93 mm

Figure 6.7 LDPC-COFDM UWB baseband processor

Table 6.3 LDPC-COFDM UWB PHY baseband feature

Technology 0.18µm CMOS 1P6M

Package 208 CQFP

Die area 42.25 mm² (6.5 mm x 6.5 mm)

Max. Working Frequency 264 MHz

Core Power at 480Mb/s (TX/RX) 523 mW/575 mW Supply Voltage 1.8V Core, 3.3V I/O

Design Area 2.17 mm² (5.1%)

Design Power 21.4 mW (3.7%) @480Mb/s RX

Chapter 7.

Conclusion and Future Work

After design description, performance analysis and hardware comparison, a novel frequency synchronizer is proposed here to achieve high throughput, low power, and satisfy performance for OFDM-based WLAN and UWB system. Combining data-partition-based, power-aware CFO estimation and approximate CFO compensation scheme, our proposal can reduce 69.4% ~ 75.6% power consumption with achievable 0.04 ~ 0.6dB SNR loss for 10%

PER of IEEE 802.11a WLAN system and 8% PER of LDPC-COFDM and MB-OFDM UWB systems; and further, the CFO-estimation range of ±100ppm in WLAN and of ±45ppm in UWB also can achieve the system requirement. The proposed design can achieve 528MSamples/s high throughput in both standard 0.13µm and 0.18µm CMOS processes.

For simulation of the power-aware CFO estimation, we established pseudo time-variant mean-CFO with phase noise model includes TIV (time-invariant), SV (slow-variant) and FV (fast-variant). However, the practical CFO model is also needed. In the future, we will survey more practical model to verify the design even if our pseudo model has considered about the worst CFO condition. Therefore, we are supposed to have more power reduction in general simulation case which mean-CFO is time-invariant.

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作 者 簡 歷

姓名 ：陳林宏

出生地 ：台灣省新竹市 出生日期：1976. 11. 14

學經歷：1991. 9 ~ 1994 .6 新竹市立高級工業職業學校 1995. 9 ~ 1999. 6 台北科技大學 電機系 學士 1999. 10 ~ 2001. 6 中華民國陸軍通信預官

2001. 7 ~ 2002. 7 興瑞通信股份有限公司研發部工程師 2003. 9 ~ 2005. 7 國立交通大學 電子研究所 系統組 碩士

得 獎 事 績

九十三學年度 全國系統晶片設計比賽光電通訊類 SOC 組特優獎

發 表 論 文

Lin-Hung Chen, Wei-Che Chang, Hsuan-Yu Liu, and Chen-Yi Lee “ A 528MS/s Frequency Synchronizer for OFDM-based UWB System”, VLSI-DAT 2005

Husan-Yu Liu, Chien-Ching Lin, Yu-Wei Lin, Ching-Che Chung, Kai-Li Lin, Wei-Che Chang, Lin-Hung Chen, Hsie-Chia Chang, and Chen-Yi Lee

“ A 480Mb/s LDPC-COFDM-based UWB Baseband Transceiver in 0.18µm CMOS Process”, ISSCC Feb. 2005.

在文檔中 應用於正交分頻多工為基礎的無線存取系統之低複雜度頻率同步器 (頁 69-0)