CHAPTER 3. A FREQUENCY SYNCHRONIZER DESIGN FOR OFDM WLAN
3.2.2 Samples Power Detection
For low complexity method, we can reduce the half samples of short and long training symbols for correlations according to the information of even or odd index from power distribution of samples. In the realistic system, we need the packet detection before the CFO acquisition. Nevertheless, even if we have packet detection, we can not ensure how accurate is;
furthermore, because of the multipath effect, the power distribution of samples in the short and long training symbols could be changed probably in the same time. For these reasons, we take one more short-symbol to detect the next coming short symbols which samples have stronger power. Due to one short symbol includes 16 samples, and we sum each sample power of even and odd index respectively. And then we can determine that even or odd index samples have stronger power for coarse CFO estimation. Certainly, the opposite result of the detection can be used for following fine CFO estimation. Therefore, the algorithms of the coarse and fine CFO estimation can be modified as equation (3.24) and (3.25) respectively;
and λ is decided by sample power detector. Consider about limited short training symbols and the performance trade off, we used twice correlations that total three short symbols needed.
Figure 3.3 shows the synchronization flow with the sample power detection and the interactive between the packet detection and CFO compensation before FFT demodulation.
)
SNR [dB] RMS [ns]
Probability [%]
Pr( odd-index power > even-index power)
*Simula
ted packets per SNR : 100000
(a)
SNR [dB] RMS [ns]
Probability [%]
Pr( odd-index power > even-index power)
*Simulated packets per SNR : 100000
(b)
Figure 3.2 Power distribution of (a) Short training symbols (b) Long training symbols
Received data Received data
Short training Symbol start?
Short training Symbol start?
Coarse CFO estimation and compensation Coarse CFO estimation
and compensation
Detect long training symbol and fine CFO estimation Detect long training symbol
and fine CFO estimation
Long training Symbol start?
Long training Symbol start?
Fine CFO compensation Fine CFO compensation
FFTFFT
Sample power detection Sample power detection Yes
No
Even/Odd Odd/Even
Yes No
Figure 3.3 The synchronization flowchart with sample power detection
Chapter 4.
A High Speed and Low Complexity Frequency Synchronizer for OFDM-based UWB System
For general OFDM-based wireless access systems, we proposed a frequency synchronizer in chapter 3. Based on this design, the modifications can be made when dealing with different applications with particular requirements and specifications. In this chapter, a high-speed and low complexity frequency synchronizer is proposed for 528MHz OFDM-based UWB system.
4.1 Motivation
To speed up the implementation and power-reduction of 528MHz UWB frequency synchronizer, a novel low-power scheme combining data-partition-based, power-aware CFO estimation and approximate phasor compensation is proposed. It can reduce redundant computation of synchronization algorithm according to performance requirement. Following the algorithm improvement, the needed memory and clock speed of frequency synchronizer can be both decreased. In the further, we can reduce more power consumption in the better channel condition by power-aware concept. Simulation results show the power elimination efficiency is 69.4 ~ 75.6% and the paid performance loss can be limited to 0.04 ~ 0.6dB for typical 8% packet-error-rate (PER) for UWB.
4.2 Effect of Carrier Frequency Offset
receiver. So the required CFO estimation range must be ±40ppm (TX+RX) in frequency synchronizer. Besides, in order to enhance system performance, an accurate CFO estimation is generally requested in frequency synchronizer. However as system migrates from WLAN to UWB, the performance degradation caused by CFO becomes different. According to [14], the average power of frequency-domain signal without inter-carrier interference (ICI) can be derived as equation (4.1).
[ ]
Y 2 X 2H 2{
[sin ] [Nsin( N)]}
2E K = π∈ π∈ (4.1)
Where YK is the received signal, |X|2 is the average transmitted signal power, |H|2 is the average channel response power, ∈ is the relative CFO of the channel (the ratio of actual CFO to the subcarrier spacing), and N is the point number of the DFT used for OFDM. In the (4.1), it can be found that the signal power is degraded by relative CFO ∈. The CFO also causes ICI which is added to the received signal. According to [14], the average power of ICI can be derived as equation (4.2).
[ ] { } ∑− { }
≠− −
=
∈ +
∈
= K k
p K k p
K X H N p N
I E
0
2 2 2
2
2 sinπ 1 sin[π( ) ] (4.2)
Where IK is the ICI of the OFDM system, which using 2K+1 subcarriers. From (4.1) and (4.2), the signal-to-ICI ratio (SIR) of UWB and WLAN system can be calculated and then drawn in Figure 4.1. Since the specifications containing subcarrier spacing, RF frequency, and subcarrier number of UWB and WLAN system are different, the SIR of UWB is ~18dB higher than that of WLAN. The main cause is that the subcarrier spacing of UWB (4.125MHz) is 13.2 times wider than that of WLAN (312.5 KHz). Therefore the relative CFO ∈ of UWB becomes lower. The lower relative CFO leads to less performance degradation.
To understand the required CFO-estimation accuracy from a system-level view, we simulated baseband PER with different CFO-estimation error. The simulated SNR loss for 8%
PER caused by CFO-estimation error is shown in Figure 4.2.From Figure 4.2, it is found the
tolerant CFO-estimation error of UWB can be higher than of WLAN in the same SNR-loss constraint. For example, in 1dB SNR-loss constraint, the estimation error of UWB can be tolerated to 5ppm, but the estimation error of WLAN must be lower than 0.4ppm. Based on the performance comparison, the required accuracy and design complexity of CFO estimation in UWB can be less than that in WLAN. And a low-power scheme with algorithm reduction can be exploited in frequency synchronizer.
2 4 6 8 10
10 15 20 25 30 35 40 45 50
IEEE 802.11a system in 5.8GHz RF band UWB system in 10.6GHz RF band
CFO estimation error [ppm]
Signal-to-ICI ratio [dB]
Figure 4.1 Signal-to-ICI ratio under CFO effect
＊Simulated packets per SNR: 1500, Data bytes per packet: 1024
0 2 4 6 8 10
0 1 2 3 4 5 6 7 8
CFO [ppm]
SNR Loss for 8% PER [dB] 480Mb/s UWB system @ 10.6GHz RF 54Mb/s IEEE 802.11a system @ 5GHz RF
Figure 4.2 SNR loss caused by CFO estimation error
4.3 The Proposed CFO Estimation and Compensation Scheme
The Figure 4.3 shows the block diagram of the proposed frequency synchronizer. In the beginning, the received preamble is sent to CFO estimator. Then the estimated result is sent to CFO compensator. And the late preamble and data signal are compensated and sent out. The compensated output signal can be used for timing synchronization and data demodulation.
Besides, the proposed design is developed based on a data partition scheme in CFO estimator and an approximate phasor compensation scheme in CFO compensator to reduce design complexity. The proposed low-complexity algorithms will be described below.
CFO Compensator CFO
Estimator
Preamble
From
ADC To FFT
To Symbol-timing
detector
Preamble and data
Estimated result
Figure 4.3 Block diagram of frequency synchronizer
4.3.1 Data-partition-based CFO Estimation
The conventional CFO estimator algorithm which uses full repeated symbols for auto-correlation is derived as equation (4.3).
⎪⎪
Where ∈ˆ is the estimated CFO, rn is the n-th received sample, and N is the total sample amount of one symbol. So r0 ~ rN-1 are the samples of one symbol duration. In UWB system, N is equal to 165 for repeated OFDM symbols [8]. And in CFO estimator, the first symbol with N samples needs to be stored in memory or delay-line [9]. To reduce the required memory access, a low-power algorithm based on data partition is proposed. It can be derived as equation (4.4).
⎣ ⎦ used sample amount is reduced from N to⎣N λ⎦, which shown in Figure 4.4. Therefore, the design complexity of auto-correlation containing the memory size to store the used samples and the multiplication of used samples can be efficiently reduced.
Besides, the different correlation distance will affect the estimation accuracy and range.
The signal power of image part will be increased because of long correlation distance, and then the estimation accuracy will be improved. However, the long correlation distance also decreased the estimation range. For the estimation accuracy and range trade off, the correlation distance is limited to 3NT, that equal to 0.9375µs. So the estimation range can achieve ±0.5/0.9375µs = ±533KHz [14], that is ±50.3ppm of the highest RF frequency (10.6GHz) of UWB system. Thus the proposed algorithm can meet the requested ±40ppm CFO estimation range. Coincident, the 3NT correlation distance also can be applied in the
multi-band UWB system [4], for example, used time-frequency code 1 for band group 1, where the first OFDM symbol is transmitted on sub-band 1, the second OFDM symbol is transmitted on sub-band 2, the third OFDM symbol is transmitted on sub-band 3, the fourth OFDM symbol is transmitted on sub-band 1, and so on. This concept of the correlation distance also shown in Figure 4.4(b).
(a)
(b)
r0 r1 r2 r3 rN-2 rN-1 rN rN+1 rN+2 rN+3 r2N-2r2N-1
Received signal:
* * * * * *
Required ??
Tan-1
r0 r1 r2 r3 rN-1 r3N r3N+1r3N+2r3N+3 r4N-1
Received signal:
* * * * *
Tan-1 Multiplication: λ 1
Figure 4.4 (a) The conventional CFO estimation (b) The proposed data-partition-based CFO estimation
In order to reduce complexity and keep performance simultaneously, we have to find a good λ value. As Figure 4.5 shown, if high λ value is chosen, the complexity will be lower, but the CFO estimation error will be increased. In the section 4.3.3, we will choose a good λ value according to the performance loss.
0 5 10 15
Proposed: lamda = 4 lamda = 8
Figure 4.5 CFO estimation error with different complexity
4.3.2 Approximate phasor Compensation
In compensation part, the ideal method is to directly compensate the received signal with the phasor. It can be derived as equation (4.5).
ˆ ) system, the sample period (T=1/bandwidth=1/528MHz) is shorter than 1.9ns. So the compensating phasors for neighboring samples are approximate to each other. Hence the proposed approximate compensation scheme is derived as equation (4.6).
) proposed algorithm where λ = 4. So each phasor can be used to compensate λ samples. And the phasor computations of (4.6) can be reduced to ~ 1/λ of that of (4.5). Figure 4.7 shows the
∈ˆ= 424 KHz (40pm of 10.6GHz). And the x-axis is the receiving time (kT). As shown in Figure 4.7, the difference between the real parts of compensating phasor can be less than 2%.
The difference is small so the approximate phasor compensation can be used to reduce the phasor computations.
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 θ0 θ1 θ2 θ3 θ4 θ5 θ6 θ7 θ8 θ9 θ10 θ11
rˆ0 rˆ1 rˆ2 rˆ3 rˆ4 rˆ5 rˆ6 rˆ7 rˆ8 rˆ9 rˆ10 rˆ11
Received data:
Required ??
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11
θ0 θ4 θ8
rˆ0 rˆ1 rˆ2 rˆ3 rˆ4 rˆ5 rˆ6 rˆ7 rˆ8 rˆ9 rˆ10 rˆ11
Received data:
LUT complexity
λ 1
(a)
(b)
Figure 4.6 CFO compensation scheme (a) Conventional approach (b) Proposed approach
600 610 620 630 640 650 660
<2%
Figure 4.7 Real parts of compensating phasor
4.3.3 Reduced parameter search
In order to find a good λ for data-partition CFO estimation and approximate CFO compensation scheme, we simulated the PER curves with different design complexity.
PER Analysis with Different Design Complexity
Figure 4.8 shows the PER curves with different λ values which control required memory size and design complexity. The required SNR of different design complexity and its SNR loss are listed in Table 4.1. The SNR loss of the proposed design (λ=4) compared with perfect synchronization (CFO-estimation error = 0.0ppm) is only 0.07dB for 8%
PER. PER of the proposed design is close to the design with λ = 2. That means the design complexity can be reduced from 50% to 25% with very little SNR loss. As λ is increased from 4 to 8, only 25%-12.5% = 12.5% design complexity are reduced further.
But the SNR loss will be increased to 0.21dB equal to three times of the proposed design.
Hence the design with λ = 4 is proposed to achieve low design complexity with an acceptable performance loss.
λ= 1, (100% memory) λ= 2, (50% memory)
Proposed:λ= 4, (25% memory) λ= 8, (12.5% memory) λ= 16, (6.25% memory) λ= 32, (3.125% memory)
Perfect synchronization PER = 8%
＊Data rate: 240Mb/s, Simulated packets per SNR: 1500, Data bytes per packet: 1024, Channel CFO: 40ppm
Figure 4.8 PER with different design complexity
Table 4.1 The required SNR for 8% PER of the different design complexity Design
Parameter (λ) Design SNR (dB) SNR Loss compared with perfect synchronization (dB)
1 5.31 0
2 5.34 0.03
4 5.38 0.07
8 5.52 0.21
16 5.67 0.36
32 6.02 0.71
4.3.4 Power Aware CFO estimation
After introduction of the approximate CFO compensation, we focus on data-partition CFO estimation again. We’ll try to reduce more complexity of data-partition estimation by power-aware concept. In the previous design, we used higher accuracy estimation which means higher complexity to estimate the CFO at every packet; we define it as fine estimation.
However, in the better CFO environment, we can reduce the turn on probability of fine estimation at every packet. First, we used a lower accuracy estimation which means lower complexity to estimate the CFO at every packet; we define it as coarse estimation. The coarse estimation is used to decide whether the fine estimation turn on or not according to CFO environment. So we will not use any estimated result from coarse estimation. If coarse-estimation detect the worst CFO environment (fast variation), then fine-estimation will turn on; otherwise, we will use the previous result of fine estimation. For this reason, the complexity will be reduced greatly in the better CFO environment. Figure 4.9 shows the concept of power aware.
F F F F F F F F F Fine Estimation (Est.)
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9
C+F C C C C C+F C C C Coarse Estimation (Est.)
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9
Conventional:
Proposed: Lower-complexity coarse est. is added
Figure 4.9 Power aware concept
In the further, we have to decide when the fine estimation turns on. We have a decision methodology as Figure 4.10. First, we will choose a threshold. If the difference of estimated results between coarse estimation and previous fine estimation is greater than threshold, then the fine estimation will be turned on. Therefore, the current estimated result is from new fine estimation. Otherwise, the fine estimation is turned off; the current estimated result is from previous fine estimation. We can notice that the turn on time of coarse and fine estimation is not overlap, and then the hardware can be shared. Besides, if the threshold is larger, the turn on probability of fine estimation is lower. Of course, the estimation complexity can be reduced.
if (CFOcoarse– CFO previous fine > Threshold) 1. Fine Est. is turned on
2. CFO_Est = CFOfine else
1. Fine Est. is turned off 2. CFO_Est = CFOprevious fine
preamble Fine
preamble coarse coarse
Figure 4.10 Decision methodology of fine estimation turn on
Figure 4.11 shows an example which used coarse estimation (λ=1/64 complexity) and fine estimation (λ=1/4 complexity). These three z-axes represent fine estimation turn on rate, CFO estimation error (RMSE) and estimation complexity respectively. X-axis and y-axis represent SNR and threshold respectively. From these figures, when the threshold is increased, the turn on probability of fine estimation will be decreased. Because of the lower turn on probability of fine estimation, the CFO estimation error will be increased, but the complexity can be reduced. Therefore, the estimation error and complexity are trade-off. For this reason, a good threshold for balance among performance, complexity and CFO environment is important. We will show the performance loss for different threshold and CFO environment in the next section.
Figure 4.11 Relation among fine estimation turn on rate, estimation error and complexity
4.3.4 Threshold search
The decision of threshold is related to system performance and CFO environment. In the FV environment, in order to keep the performance, the turn on probability of the fine
estimation should be higher. That means the threshold should be decreased. In the SV environment, the threshold can be increased that makes the higher turn on probability of the fine estimation and lower complexity. We simulated the PER with different threshold in two CFO environments, one is SV which is shown in Figure 4.12, the other is FV which is shown in Figure 4.13. According to Table 4.2, the SNR loss of the threshold equal to 10ppm compared with the perfect synchronization is 0.6dB for 8% PER. However, when threshold is extended from 10ppm to 12ppm, the SNR loss is larger than 1dB. That means the threshold = 10ppm is chosen to achieve low design complexity with an acceptable performance loss in the SV environment.
0 2 4 6 8 10
10-2 10-1 100
SNR [dB]
PER
SV : perfect sync.
SV : 10ppm SV : 12ppm PER = 8%
Figure 4.12 Threshold search in 110Mb/s SV environment
Table 4.2 Performance of different threshold in SV environment Threshold SNR for 8% PER (dB) SNR loss (dB)
Perfect synchronization 6.4 0
10ppm 7.0 0.6
12ppm 7.8 1.4
From Table 4.3, the SNR loss of the threshold equal to 2ppm compared with the perfect synchronization is 0.1dB for 8% PER. However, when threshold is extended from 2ppm to 4ppm, the SNR loss is equal to 1dB. That means in the FV environment, the threshold = 2ppm is chosen to achieve acceptable performance loss. However, because of the lower threshold, the complexity of the CFO estimation in the FV environment could not be reduced as more as in the SV environment. Therefore, the concept of the power-aware is truly used in proposed design.
0 2 4 6 8 10
10-2 10-1 100
SNR [dB]
PER
FV : perfect sync.
FV : 2ppm FV : 4ppm PER = 8%
Figure 4.13 Threshold search in 110Mb/s FV environment
Table 4.3 Performance of different threshold in FV environment Threshold SNR for 8% PER (dB) SNR loss (dB)
Perfect synchronization 7.0 0
2ppm 7.1 0.1
4ppm 8.0 1.0
Chapter 5.
Simulation Results and Performance Analysis
In order to verify the proposed design, the complete system platforms of the IEEE 802.11a and UWB proposal are established on Matlab. These platforms have been introduced in chapter2. The performance of the proposed design will be simulated and compared with the conventional approaches in the following analysis.
5.1 Performance Analysis of the Proposed Frequency Synchronizer for OFDM WLAN Systems
The proposed frequency synchronizer for OFDM-based wireless systems is simulated in the system platform compliant to the IEEE 802.11a PHY. The PER analysis will focus on the 10% PER, which is the requirement in IEEE 802.11a standard
5.1.1 CFO Estimation Accuracy Analysis
RMSE Analysis
To analyze the CFO estimation accuracy of the proposed frequency synchronizer, the Root-Mean-Square-Error (RMSE) between the estimated CFO and the real CFO is measured, which has shown in Figure 5.1. Because AGC and packet detection need to take several short training symbols before frequency synchronization, we use three short symbols for coarse CFO estimation and one short symbol for sample-power detection. In the beginning, we simulated 4 cases for known sample-power-distribution without multipath effect; of course,
we don’t need sample power detection. These 4 curves show me that even-samples in short symbol and odd-samples in long symbol (the square-mark curve) have more accuracy than opposite results (the triangle-up-mark curve) in SNR less than 5dB compared with 100%
memory rate (the circle-mark curve). However, because of the multipath effect, the known sample power distribution will be interfered and estimation accuracy also decreased as the diamond-mark curve. In order to overcome this problem, the sample-power-detection could be applied to improve the estimation accuracy as the proposed curve. The reason that the accuracy of the proposed curve can’t close to the square-mark curve is only one short symbol for power detection, the correct decision probability could not achieve 100%.
＊Simulated packets per SNR: 5000, CFO: 40ppm
0 5 10 15
100 101 102
SNR [dB]
RMSE
short (100% memory), long (100% memory), RMS=0 short-even (50% memory), long-odd (50% memory) short (50% memory), long (50% memory), RMS=150ns short-even (25% memory), long-odd (25% memory), RMS=0 short-even (50% memory), long-odd (50% memory), RMS=150ns short-odd (50% memory), long-even (50% memory), RMS=0 short (100% memory), long (100% memory), RMS=0, without decision short-even (50% memory), long-odd (50% memory), RMS=0, without decision short (50% memory), long (50% memory), RMS=150ns, with decision (proposed) short-even (25% memory), long-odd (25% memory), RMS=0, without decision short-even (50% memory), long-odd (50% memory), RMS=150ns, without decision short-odd (50% memory), long-even (50% memory), RMS=0, without decision
Figure 5.1 RMSE analysis of the proposed design PER Analysis
For performance analysis of the propose design, PER is simulated with the typical indoor wireless channel model that contains 50ns multipath RMS delay spread, 40ppm CFO and 40ppm SCO. The PER curves of 6Mb/s and 54Mb/s with perfect synchronization (CFO-estimation error = 0.0ppm), 100% memory approach and proposed design can be
shown in Figure 5.2. From Figure 5.2, the SNR loss of the proposed design (50% memory) compared with the 100% memory approach in the 6Mb/s and 54Mb/s are only 0.1dB and 0.13dB respectively for 10% PER. However, the memory size and computational complexity can be reduced from 100% to 50% with very low SNR loss.
(a) (b)
0 1 2 3 4 5
10-2 10-1 100
SNR [dB]
PER
Perfect Sync.
100% memory Proposed, 50% memory PER = 10%
18 18.5 19 19.5 20 20.5 21 21.5 22 10-2
10-1 100
SNR [dB]
PER
100% memory Proposed: 50% memory Perfect Sync.
PER = 10%
Figure 5.2 PER of the proposed design in (a) 6Mb/s (b) 54Mb/s data rates
5.1.2 System Performance
The PER curves of the OFDM-based WLAN system with 6Mb/s ~ 54Mb/s data rates are shown in Figure 5.3 and the design SNR for 10% PER are listed in Table 5.1. Compared with the perfect synchronization, the SNR loss of the proposed design is 0.15 ~ 0.38dB for 10%
The PER curves of the OFDM-based WLAN system with 6Mb/s ~ 54Mb/s data rates are shown in Figure 5.3 and the design SNR for 10% PER are listed in Table 5.1. Compared with the perfect synchronization, the SNR loss of the proposed design is 0.15 ~ 0.38dB for 10%