Conclusion - Design Consideration - Receiver Front-End and Design Considerations

Chapter 2 Receiver Front-End and Design Considerations

2.4. Design Consideration

2.4.2. Sensitivity

2.4.2.4. Conclusion

It is clear that the traditional analysis approach is oversimplified. With little effort, a more accurate estimate of optical sensitivity can be made. So, relying on a vendor specification meant for comparison-shopping or someone’s rule of thumb should sound the alarm. By applying the technique presented in this discussion, it is easy to estimate and predict more realistic optical receiver sensitivity. In the end, there won’t be any big surprises when you test your first parts!

Chapter 3 Differential Active Feedback TIA

3.1. Introduction

This chapter describes a differential active feedback transimpedance amplifier.

Differential architecture have been proposed to improve sensitivity at the input of transimpedance amplifiers. Compared to conventional single ended architecture [16]

[17], this work reject common mode substrate and power supply noise, Due to differential dc coupled, transimpedance sensing photodiode current directly , and achieved twice output swing. In comparison, an ac coupled photodiode current sensing configuration in [18] [19], suffers from the difficulty of realizing on chip capacitors and photodiode bias fluctuation with ambient light variation.

To achieve the required bandwidth, transimpedance amplifier incorporates two high-speed techniques: inductive peaking, and active negative feedback. In conventional resistive feedback techniques, the strength of the feedback directly

trades with the open loop gain. Alternatively, the unilateral feedback in an active stage avoids this trade off.. It achieves better gain bandwidth product.

3.2. Differential Active Feedback TIA Architecture

The conceptual architecture of the TIA is depicted in Figure 3-1. It consists of a regulated cascade (RGC) input stage(M1, M2), a core amplifier stage(TIA), an active negative feedback stage(Mf1, Mf2), and the output buffer stage(B1). The photo diode is connected to node Vin+ and node Vin- for dc–coupled differential photodiode current sensing.

Fig. 3-1 Differential active feedback TIA architecture

It is well known that tradeoffs between bandwidth and photodiode capacitance are inevitable in a conventional common-source TIA. Even though common-gate (CG)

the large photodiode capacitance from the bandwidth determination because of small of the input transistor. Meanwhile, the RGC input configuration reported in [22]–[24]

enhances the input significantly due to the local feedback mechanism, so that the RGC TIA can achieve better isolation of the photodiode capacitance than other configurations. Namely, the RGC circuit enables the TIA to avoid the need of a dummy input capacitor due to the virtual-ground input impedance, thus facilitating the realization of an optical interconnect system in a single chip. Also, the virtual ground input reduces the noise coupling from through the photodiode into the TIA so much that there is no longer a need to balance it out. Furthermore, proper sizing of the local feedback stage reduces the dominant high-frequency noise contribution of the RGC TIA without deteriorating the stability [24].

In conventional resistive feedback techniques, the strength of the feedback directly trades with the open loop gain. Alternatively, the unilateral feedback in an active stage avoids this trade off.. In Figure 3-1, the differential pair M3-M4 provides active feedback. It can be proved that active feedback results in a gain-bandwidth product of roughtly fT/(C1BW) [25].

In high speed circuit design, the output stage must deliver large currents to the 50Ω loads. Therefore, large transistor size is necessary to achieve such a large current.

Unfortunately, the large size will produce substantial parasitic capacitance that will decrease the signal bandwidth. To alleviate the load to preceding gain stages, a fT-doubler [26] circuit shown in Fig.3-2 is adopted. Compare fT-doubler with a simple differential stage, one can get the idea that with the same drive capability fT-doubler has smaller input capacitance.

Fig. 3-2 fT doubler schematic

3.3. 3-D Transformer

To achieve both wide band and high gain design goals, 3-D symmetric transformers [27] are utilized for bandwidth enhancement. Compared to using two asymmetric or one planar symmetric counterparts in a fully differential architecture, it greatly saves chip area. The distributed and lumped circuit models of the 3-D transformer are illustrated in Figure.3-3 (a) and Figure.3-3(b) respectively. Here Rs1,i

and Rs2,i represent the distributed resistance of L1 and L2 on metal layer i. C1,jk and C2,jk denotes the parasitic capacitance of L1 and L2 between metal layer j(= 6, 5, 4, 3, 2), k(= 4, 3, 2) and substrate k(= 0). The outer radius of loops on adjacent layers are offset by the metal width. Thus the parasitic capacitance between adjacent metal layers can be eliminated. Besides, C1,jk and C2,jk are reduced by increasing the distance between metal plate, so as to have better self resonant frequency (fsr). Furthermore, by means of the interleaving architecture in a relatively small area, the effective inductance in each branch is increased by enhancing the mutual coupling of the

transformer (M), including the magnetic coupling on the same layer (M1) and adjacent layer (M2 −M9). Thus the total wired length of the 3-D transformer can be reduced to be configured in a small area. And the parasitic capacitance to substrate can be minimized.

Fig. 3-3 (a) 3-D symmetric transformer (b)Distributd and lumped circuit model

Figure.3-4 illustrates the cross sectional view of planar transformer and its electrical potential distribution. The equivalent parasitic capacitance can be derived as

∑

where C^mkdenotes the metal to substrate parasitic capacitance.

Fig. 3-4 Cross section view of planar transformer and potential distribution.

Figure.3-5 Cross sectional view of 3-D symmetric transformer and its electrical potential distribution. The equivalent parasitic capacitance can be derived as

∑

where Cmtm and Cmts respectively denotes the metal to metal and metal to substrate capacitance. Ceq2 is proven to be smaller than Ceq1 due to smaller potential difference between conducting plate.

Fig. 3-5 Cross section view of 3-D symmetric transformer and potential

Figure.3-6 illustrates the simulated performance of the proposed 3-D transformer and a conventional planar counterpart. For an inductor pair with inductance of 2.85 nH in each branch, 5 turns, metal width = 10 µm, metal spacing = 1.5 µm, and inner diameter of 110 µm, the chip area of 3-D transformer is only 47% compared to that of its planar counterparts. Also it manifests higher self resonant frequency (12 GHz v.s. 9 GHz). Though its quality factor may become worse for the sake of using lower metal layer, this is not an issue for bandwidth enhancement applications.

Fig. 3-6 Planar v.s. 3-D symmetric transformer performance comparison.

3.4. Circuit Design

The detailed circuit schematic of the TIA is as shown in Figure.3-7, which is

composed of a regulated cascode (RGC) input stage (M1, M2) followed by a common source gain stage (M5,M7) with active feedback stage(Mf1,Mf2). For bias photo diode, the operating voltage is 3.3V under 0.18　m CMOS technology. The diode (MD1, MD2 ) is for voltage level shift, preventing M1 M2 operating in high voltage level. The Source followers (MS1, MS2) is for suitable voltage level shift and avoid loading effect.

Fig. 3-7 Differential active feedback TIA schematic

Node Vin+ and Vin- are connect to both side of photo diode, for dc–coupled differential photodiode current sensing. Due to the current of photodiode is from TIA circuit itself, the current of photodiode will be limited by TIA circuit. The maxim current is describe as equation 3-3:

max

Vin Vpd

I VDD− ^bias − ⁺

= (3-3)

The closed loop conversion gain of the TIA can be approximated by

) (

1 ₃ ₃ ₁

1 3 3

R R g g

R R T g

m mf

z +

= − (3-4)

Before analysis the frequency response, we assume the TIA circuit compose of common gate stage Ai and shunt feedback stage Az show in Figure. 3-8. Because the bandwidth of common gate stage Ai is enhance by RGC input stage, the dominate pole occurs in shunt feedback stage Az. We analysis the shunt feedback stage show in Figure. 3-9 and assume A(s) is one pole core amplifier.

Fig. 3-8 Simple architecture of TIA

Fig. 3-9 Shunt feedback stage

For critically damped-response,

According upon analysis, we can design our circuit correctly.

3.4.1. Inductive Peaking Technique

With the advent of monolithic inductors, inductive peaking techniques have become feasible in integrated circuits. Take Fig. 3-10 as an example to understand the principle of shunt-peaking. The amplifier is just a standard common source configuration with the addition of the inductance.

Fig. 3-10 A shunt-peaked amplifier and its small-signal model

One can think about why adding an inductor this way will give us a bandwidth extension intuitively. First, with an input step waveform, the inductor delays current flow through the branch containing the resistor, which makes more current available for charging the capacitor and thus reduces the risetime. It follows that a faster risetime implies a greater bandwidth. Second, one knows that the gain of an amplifier with purely resistively load will degrade at high frequency because the load capacitor’s impedance diminishes. The addition of an inductance in series with the load resistor provides an impedance component that increases with frequency, which helps offset the decreasing impedance of the capacitance. So, the total impedance can remain roughly constant over a broader frequency range just like that the bandwidth is enhanced.

Formally, the impedance of the RLC network may be written as

( )

[

( )

]

Compared with a simple common source amplifier without inductive peaking, the amplifier in Fig. 3-10 enhances the bandwidth by transforming the frequency response from that of a single pole to one with two poles and a zero. The frequency response can be characterized by the ratio of the RC and L/R time constants, that is

R L m= RC

/ (3-6)

Then, the relation between bandwidth of an amplifier with and without inductive peaking can be derived as

Where ω¹_,ω₂ are the bandwidths without and with inductive peaking individually.

Under different design requirements, there is a range of useful inductance values as listed in Table 3-1 [28]. However, since monolithic inductors suffer from parasitic capacitance and a low quality factor, inductive peaking improves the speed to a lesser extent.

In 10Gbps design, an inductor smaller than 3nH is accepted from the resonate- frequency viewpoint. Under maximally flat condition, the load resistance should smaller than 250Ω if total capacitance at output node is assumed 100fF. It means that the bias current may be larger than 3.6mA.

Conditions m=R²C/L Bandwidth

Table 3-1 Shunt-peaking summary

3.4.2. Active Feedback Technique

This work introduce active negative feedback as a means of improving the GBW of amplifiers. Illustrated in Figure 3-11, such an arrangement employs a transconductance stage Gmf to return a fraction of output to the input of Gm1. Unlike the conventional resistor-feedback amplifier, active feedback does not resistively load the transimpedance stage. The transfer function of the overall amplifier is given by

2 2

For a maximally-flat Butterworth response, ζ=√2/2 and the -3dB bandwidth, ω-3dB= 2πf-3dB=ωn/(2π). Multiplying (3-9) by (3-11), we thus have

2 Since Gm1/C1≈2πfT, (3-13) can be rewritten as

This result reveals that active feedback increases the GBW beyond the technology fT

by a factor equal to 1/(C1f-3dB).

Fig. 3-11 Active feedback architecture

3.4.3. Noise Analysis

As introduced before, the accepted minimum input current is relative to the noise

source.

Fig. 3-12 Schematic diagram of TIA including noise source

The input referred noise current spectral density can be described as

( )

Where Cin denotes the total capacitance at input node.

Although the proposed transimpedance amplifier with regulated cascode input stage and shunt-feedback to the second stage overcomes the trade-off among gain, bandwidth, and noise as described in section 3.2, the price paid is that the input noise increases anyway especially at high frequency. To alleviate the last term above

equation, the transconductance of mb1 should be as large as possible.

3.5. Experimental Results

With Oepic-P5030A photo detctor, whose responsivity is 1 A/W, the input referred noise current (IN) of TIA is 1.2µArms. The input sensitivity of the TIA is derived from its input referred noise current (IN). As

r dBm

where ρ is the responsivity of photo detector, and re is the extinction ratio. The corresponding sensitivity is approximately -20 dBm.

Figure.3-13 illustrate the measured frequency response, the -3dB bandwidth is 2.5GHz. Figure.3-14 illustrate the measured output noise spectrum, the input referred noise current can be derived from

where Pn is noise power, Bw is TIA -3dB bandwidth. Transimpedance50 is enacts transimpedance measured in 50-ohm systems.

Operating under a 3.3V supply, the power dissipation is 79 mW, among which 40 mW is consumed by output buffer. Figure.3-15, Figure.3-16, Figure.3-17, Figure.3-18, and Figure.3-19, Figure.3-20, Figure.3-21 illustrate the corresponding eye diagram at 1.25Gbps, 2.5Gbps, 3.125Gbps, 5Gbps, 6Gbps, 7Gbps, and 8Gbps with 231-1 PRBS input. Figure.3-22 illustrates the chip photo. Fabricated in a 0.18µ m CMOS technology, chip size is 738 µm × 1522 µm.

Fig. 3-13 Measured frequency response

Fig. 3-14 Measured output noise spectrum

Fig. 3-15 1.25Gbps eye diagram with -7.4dBm input power (X axis:

134.3ps/div, Y axis: 13.5mV/div, Jitter(pp)=95.5ps).

Fig. 3-16 2.5Gbps eye diagram with -7.4dBm input power (X axis:

65.6ps/div, Y axis: 12.7mV/div, Jitter(pp)=84.55ps).

Fig. 3-17 3.125Gbps eye diagram with -7.4dBm input power (X axis:

56.3ps/div, Y axis: 12.7mV/div, Jitter(pp)=71.3ps).

Fig. 3-18 5Gbps eye diagram with -7.4dBm input power (X axis: 32.3ps/div, Y axis: 10.7mV/div, Jitter(pp)=70.34ps).

Fig. 3-19 6Gbps eye diagram with -7.4dBm input power (X axis: 50.0ps/div, Y axis: 12.0mV/div, Jitter(pp)=57.7ps).

Fig. 3-20 7Gbps eye diagram with -7.4dBm input power (X axis: 50.0ps/div, Y axis: 11.8mV/div, Jitter(pp)=55.56ps).

Fig. 3-21 8Gbps eye diagram with -7.4dBm input power (X axis: 50.0ps/div, Y axis: 11.7mV/div, Jitter(pp)=113.33ps).

Fig. 3-22 TIA chip photograph.

3.6. Conclusion

This chapter describes the design of a fully-integrated 3.125 Gbps differential active feedback transimpedance in a generic 0.18 µ m CMOS technology. The TIA provides a conversion gain of 56 dBΩ and -3 dB bandwidth of about 2.5 GHz. A regulated cascode input stage is utilized to decouple the loading effect at the input node, and wide bandwidth is achieved by means of active feedback and inductive peaking. Instead of using bulky planar inductors or two asymmertric 3-D inductors, this paper proposes a novel fully symmetric 3-D transformer for inductive peaking in each differential pair. Thus the chip area can be greatly reduced. Moreover, an self limiting is built in to alleviate overload induced data jitter. The proposed architecture is suitable for both low cost and low voltage applications.

Chapter 4 90dBΩ, 10Gbps Optical Receiver Analog Front-End

4.1. Introduction

This chapter describes a 90 dB Ω, 10 Gbps fully integrated optical receiver that incorporates transimpedance amplifier, automatic gain control circuit, and limiting amplifier on a single chip. The single chip optical receiver provides several advantages over conventional multiple chips solutions [25] [30] [31]. First, tiny photo current generated from photo detector can be on-chip enlarged to a logic level to increase noise immunity and alleviate off-chip disturbances. Second, no interstage matching networks are required at the TIA output stage and LA input stage. Broad band matching networks in general induce gain loss and are power hungry. Third, gain

requirements of the transimpedance stage and post amplifier can be further optimized, and their bandwidth requirements are relatively relaxed.

4.2. Receiver Analog Front-end Architecture

The receiver architecture is shown in Figure.4-1 To achieve an input sensitivity of −13 dBm with a photo detector whose responsivity is 1 A/W, the transimpedance gain stage is designed to provide a conversion gain of 50 dBΩ and -3dB bandwidth of about 8GHz. The TIA bandwidth is chosen to compromise between noise performance and ISI, and the conversion gain is chosen to make its output swing overpass the input sensitivity of the post amplifier. The limiting amplifier is constructed of a voltage amplifier followed by a slicer. The over-drive voltage of the slicer is designed to be about 200 mV . Thus the voltage amplifier only needs to provide 25 dB conversion gain to fully switch the slicer. The small signal voltage amplifier is comprised of 3 stage gain cell in cascade and manifest -3 dB bandwidth of 14 GHz. The required GBW per stage is about 35 GHz . Bandwidth degradation caused by the slicer is negligible, and it’s overall dominated by the transimpedance gain stage. Compared to a conventional stand alone limiting amplifier with identical gain stages, gain-bandwidth requirement of the gain cells herein are much relaxed. Thus no special bandwidth enhancement techniques are required in the front stage of voltage amplifier.

The slicer stage in further provides about 15 dB conversion gain before driving the output buffer stage. In summary the overall receiver provides 90 dBΩ conversion gain and delivers 900 mV differential output swings to a 50 Ω output load. The DC offset of the gain chain is removed by on-chip low-pass filter and feedback amplifier, the

Fig. 4-1 Optical receiver analog front-end architecture.

4.3. 3-D Transformer

To achieve both wide band and high gain design goals, 3-D symmetric transformers [27] are utilized for bandwidth enhancement. Compared to using two asymmetric or one planar symmetric counterparts in a fully differential architecture, it greatly saves chip area. The distributed and lumped circuit models of the 3-D transformer are illustrated in Figure.4-2 (a) and Figure.4-2(b) respectively. Here Rs1,i

layer (M2 −M9). Thus the total wired length of the 3-D transformer can be reduced to be configured in a small area. And the parasitic capacitance to substrate can be minimized.

Fig. 4-2 (a) 3-D symmetric transformer (b)Distributd and lumped circuit model

Figure.4-3 illustrates the cross sectional view of planar transformer and its electrical potential distribution. The equivalent parasitic capacitance can be derived as

∑

where C^mkdenotes the metal to substrate parasitic capacitance.

Fig. 4-3 Cross section view of planar transformer and potential distribution.

Figure.4-4 Cross sectional view of 3-D symmetric transformer and its electrical potential distribution. The equivalent parasitic capacitance can be derived as

∑

where Cmtm and Cmts respectively denotes the metal to metal and metal to substrate capacitance. Ceq2 is proven to be smaller than Ceq1 due to smaller potential difference between conducting plate.

Fig. 4-4 Cross section view of 3-D symmetric transformer and potential distribution.

Figure.4-5 illustrates the simulated performance of the proposed 3-D transformer and a conventional planar counterpart. For an inductor pair with inductance of 2.85 nH in each branch, 5 turns, metal width = 10 µm, metal spacing = 1.5 µm, and inner diameter of 110 µm, the chip area of 3-D transformer is only 47% compared to that of its planar counterparts. Also it manifests higher self resonant frequency (12 GHz v.s. 9 GHz). Though its quality factor may become worse for the sake of using lower metal layer, this is not an issue for bandwidth enhancement applications.

Fig. 4-5 Planar v.s. 3-D symmetric transformer performance comparison.

4.4. Circuit Design

To alleviate bandwidth degradation caused by the parasitic capacitance of photo detector and IC package, a regulated cascode (RGC) topology is adopted as the input stage. The TIA architecture is in pseudo differential configuration with shunt-feedback for better sensitivity and higher common mode noise immunity. Furthermore, an automatic gain control (AGC) loop is built in to avoid signal overload induced data jitter. The AGC is composed of an amplitude detector, a comparator, and an integrator.

As TIA’s output swing exceeds a preset voltage level Vref , the AGC will be activated.

The comparator then generates a compensating current to charge or discharge the integrator, and the conversion gain of TIA can be adjusted by reducing the shunting resistance in the input stage.

4.4.1. Trans-impedance Amplifier Circuit Schematic

The detailed circuit schematic of the TIA is as shown in Figure.4-6(a), which is composed of a regulated cascode (RGC) input stage (M1, M2) followed by a common source gain stage (M5,M7) with shunt feedback. The right half circuit of TIA (M3,M4,M6,M8) is a replica for automatic gain control.

In the high input current state, the common source amplifiers in the second stage

在文檔中光纖通訊類比前端電路設計與製作 (頁 31-0)