Chapter 3 Differential Active Feedback TIA
3.5. Experimental Results
With Oepic-P5030A photo detctor, whose responsivity is 1 A/W, the input referred noise current (IN) of TIA is 1.2µArms. The input sensitivity of the TIA is derived from its input referred noise current (IN). As
r dBm
where ρ is the responsivity of photo detector, and re is the extinction ratio. The corresponding sensitivity is approximately -20 dBm.
Figure.3-13 illustrate the measured frequency response, the -3dB bandwidth is 2.5GHz. Figure.3-14 illustrate the measured output noise spectrum, the input referred noise current can be derived from
50
where Pn is noise power, Bw is TIA -3dB bandwidth. Transimpedance50 is enacts transimpedance measured in 50-ohm systems.
Operating under a 3.3V supply, the power dissipation is 79 mW, among which 40 mW is consumed by output buffer. Figure.3-15, Figure.3-16, Figure.3-17, Figure.3-18, and Figure.3-19, Figure.3-20, Figure.3-21 illustrate the corresponding eye diagram at 1.25Gbps, 2.5Gbps, 3.125Gbps, 5Gbps, 6Gbps, 7Gbps, and 8Gbps with 231-1 PRBS input. Figure.3-22 illustrates the chip photo. Fabricated in a 0.18µ m CMOS technology, chip size is 738 µm × 1522 µm.
Fig. 3-13 Measured frequency response
Fig. 3-14 Measured output noise spectrum
Fig. 3-15 1.25Gbps eye diagram with -7.4dBm input power (X axis:
134.3ps/div, Y axis: 13.5mV/div, Jitter(pp)=95.5ps).
Fig. 3-16 2.5Gbps eye diagram with -7.4dBm input power (X axis:
65.6ps/div, Y axis: 12.7mV/div, Jitter(pp)=84.55ps).
Fig. 3-17 3.125Gbps eye diagram with -7.4dBm input power (X axis:
56.3ps/div, Y axis: 12.7mV/div, Jitter(pp)=71.3ps).
Fig. 3-18 5Gbps eye diagram with -7.4dBm input power (X axis: 32.3ps/div, Y axis: 10.7mV/div, Jitter(pp)=70.34ps).
Fig. 3-19 6Gbps eye diagram with -7.4dBm input power (X axis: 50.0ps/div, Y axis: 12.0mV/div, Jitter(pp)=57.7ps).
Fig. 3-20 7Gbps eye diagram with -7.4dBm input power (X axis: 50.0ps/div, Y axis: 11.8mV/div, Jitter(pp)=55.56ps).
Fig. 3-21 8Gbps eye diagram with -7.4dBm input power (X axis: 50.0ps/div, Y axis: 11.7mV/div, Jitter(pp)=113.33ps).
Fig. 3-22 TIA chip photograph.
3.6. Conclusion
This chapter describes the design of a fully-integrated 3.125 Gbps differential active feedback transimpedance in a generic 0.18 µ m CMOS technology. The TIA provides a conversion gain of 56 dBΩ and -3 dB bandwidth of about 2.5 GHz. A regulated cascode input stage is utilized to decouple the loading effect at the input node, and wide bandwidth is achieved by means of active feedback and inductive peaking. Instead of using bulky planar inductors or two asymmertric 3-D inductors, this paper proposes a novel fully symmetric 3-D transformer for inductive peaking in each differential pair. Thus the chip area can be greatly reduced. Moreover, an self limiting is built in to alleviate overload induced data jitter. The proposed architecture is suitable for both low cost and low voltage applications.
Chapter 4
90dBΩ, 10Gbps Optical Receiver Analog Front-End
4.1. Introduction
This chapter describes a 90 dB Ω, 10 Gbps fully integrated optical receiver that incorporates transimpedance amplifier, automatic gain control circuit, and limiting amplifier on a single chip. The single chip optical receiver provides several advantages over conventional multiple chips solutions [25] [30] [31]. First, tiny photo current generated from photo detector can be on-chip enlarged to a logic level to increase noise immunity and alleviate off-chip disturbances. Second, no interstage matching networks are required at the TIA output stage and LA input stage. Broad band matching networks in general induce gain loss and are power hungry. Third, gain
requirements of the transimpedance stage and post amplifier can be further optimized, and their bandwidth requirements are relatively relaxed.
4.2. Receiver Analog Front-end Architecture
The receiver architecture is shown in Figure.4-1 To achieve an input sensitivity of −13 dBm with a photo detector whose responsivity is 1 A/W, the transimpedance gain stage is designed to provide a conversion gain of 50 dBΩ and -3dB bandwidth of about 8GHz. The TIA bandwidth is chosen to compromise between noise performance and ISI, and the conversion gain is chosen to make its output swing overpass the input sensitivity of the post amplifier. The limiting amplifier is constructed of a voltage amplifier followed by a slicer. The over-drive voltage of the slicer is designed to be about 200 mV . Thus the voltage amplifier only needs to provide 25 dB conversion gain to fully switch the slicer. The small signal voltage amplifier is comprised of 3 stage gain cell in cascade and manifest -3 dB bandwidth of 14 GHz. The required GBW per stage is about 35 GHz . Bandwidth degradation caused by the slicer is negligible, and it’s overall dominated by the transimpedance gain stage. Compared to a conventional stand alone limiting amplifier with identical gain stages, gain-bandwidth requirement of the gain cells herein are much relaxed. Thus no special bandwidth enhancement techniques are required in the front stage of voltage amplifier.
The slicer stage in further provides about 15 dB conversion gain before driving the output buffer stage. In summary the overall receiver provides 90 dBΩ conversion gain and delivers 900 mV differential output swings to a 50 Ω output load. The DC offset of the gain chain is removed by on-chip low-pass filter and feedback amplifier, the
Fig. 4-1 Optical receiver analog front-end architecture.
4.3. 3-D Transformer
To achieve both wide band and high gain design goals, 3-D symmetric transformers [27] are utilized for bandwidth enhancement. Compared to using two asymmetric or one planar symmetric counterparts in a fully differential architecture, it greatly saves chip area. The distributed and lumped circuit models of the 3-D transformer are illustrated in Figure.4-2 (a) and Figure.4-2(b) respectively. Here Rs1,i
and Rs2,i represent the distributed resistance of L1 and L2 on metal layer i. C1,jk and C2,jk denotes the parasitic capacitance of L1 and L2 between metal layer j(= 6, 5, 4, 3, 2), k(= 4, 3, 2) and substrate k(= 0). The outer radius of loops on adjacent layers are offset by the metal width. Thus the parasitic capacitance between adjacent metal layers can be eliminated. Besides, C1,jk and C2,jk are reduced by increasing the distance between metal plate, so as to have better self resonant frequency (fsr). Furthermore, by means of the interleaving architecture in a relatively small area, the effective inductance in each branch is increased by enhancing the mutual coupling of the transformer (M), including the magnetic coupling on the same layer (M1) and adjacent
layer (M2 −M9). Thus the total wired length of the 3-D transformer can be reduced to be configured in a small area. And the parasitic capacitance to substrate can be minimized.
Fig. 4-2 (a) 3-D symmetric transformer (b)Distributd and lumped circuit model
Figure.4-3 illustrates the cross sectional view of planar transformer and its electrical potential distribution. The equivalent parasitic capacitance can be derived as
∑
where Cmk denotes the metal to substrate parasitic capacitance.
Fig. 4-3 Cross section view of planar transformer and potential distribution.
Figure.4-4 Cross sectional view of 3-D symmetric transformer and its electrical potential distribution. The equivalent parasitic capacitance can be derived as
∑
where Cmtm and Cmts respectively denotes the metal to metal and metal to substrate capacitance. Ceq2 is proven to be smaller than Ceq1 due to smaller potential difference between conducting plate.Fig. 4-4 Cross section view of 3-D symmetric transformer and potential distribution.
Figure.4-5 illustrates the simulated performance of the proposed 3-D transformer and a conventional planar counterpart. For an inductor pair with inductance of 2.85 nH in each branch, 5 turns, metal width = 10 µm, metal spacing = 1.5 µm, and inner diameter of 110 µm, the chip area of 3-D transformer is only 47% compared to that of its planar counterparts. Also it manifests higher self resonant frequency (12 GHz v.s. 9 GHz). Though its quality factor may become worse for the sake of using lower metal layer, this is not an issue for bandwidth enhancement applications.
Fig. 4-5 Planar v.s. 3-D symmetric transformer performance comparison.
4.4. Circuit Design
To alleviate bandwidth degradation caused by the parasitic capacitance of photo detector and IC package, a regulated cascode (RGC) topology is adopted as the input stage. The TIA architecture is in pseudo differential configuration with shunt-feedback for better sensitivity and higher common mode noise immunity. Furthermore, an automatic gain control (AGC) loop is built in to avoid signal overload induced data jitter. The AGC is composed of an amplitude detector, a comparator, and an integrator.
As TIA’s output swing exceeds a preset voltage level Vref , the AGC will be activated.
The comparator then generates a compensating current to charge or discharge the integrator, and the conversion gain of TIA can be adjusted by reducing the shunting resistance in the input stage.
4.4.1. Trans-impedance Amplifier Circuit Schematic
The detailed circuit schematic of the TIA is as shown in Figure.4-6(a), which is composed of a regulated cascode (RGC) input stage (M1, M2) followed by a common source gain stage (M5,M7) with shunt feedback. The right half circuit of TIA (M3,M4,M6,M8) is a replica for automatic gain control.
In the high input current state, the common source amplifiers in the second stage of TIA may be driven into deep triode region and results in overload induced data jitter. To mitigate this effects, the feedback resistors are adjusted by turning-on the shunting resistance of M7. On the contrary, as the input current is below a predetermined threshold level, the shunting transistors are turned off for low noise operation.
4.4.2. Automatic Gain Control Circuit Schematic
The detailed circuit schematic of AGC is shown in Figure.4-6.(b), which is comprised of a peak-detector (M1, M2, C1, C2) followed by an OTA for amplitude comparison (M3-M8), a lossy integrator stage (M11, R1, C3). and a low pass filter (R2, C4). The loop bandwidth of AGC is mainly determined by 1/R2C4. Here M1 acts as the nonlinear rectifying element on the output signal of TIA. On the other hand, VTH derived from Vref at the replica of TIA core sets up the threshold voltage to turn on AGC. As the photo current exceeds a predetermined input level, the output node of TIA Vo will be driven to be lower than Vref . Thereafter, the OTA (M3-M10) would sense the voltage difference and generate the compensation current to charge or
resistance of M7 and M8 in the TIA core.
Fig. 4-6 (a) Transimpedance amplifier circuit schematic (b)Amplitude detector for AGC.
4.4.3. Limiting Amplifier Circuit Schematic
The core circuit of the voltage amplifier is shown in Figure.4-7(a), which is based on Cherry-Hooper circuit architecture with active feedback [25]. Compared to the prior art in [25], the GBW requirement in the front-stage of voltage amplifier is
relaxed and thus no peaking inductor is required to save area. Also, different from our previous work in [32] using resistive feedback, unilateral feedback avoids trade-off between feedback factor (close loop gain) and open loop gain (close loop BW) [25].
The gain cell of slicer is shown in Figure.4-7(b). Herein inductive peaking technique is utilized to accelerate voltage switch and balance rising and falling time at high voltage level.
Fig. 4-7 :Gain Cell of (a) Voltage amplifier, and (b) Slicer.
4.5. Experimental Results
With Oepic-P5030A photo detctor, whose responsivity is 1 A/W, the sensitivity of the optical receiver AFE at 10 Gbps is about -13 dBm for BER less than 10−12. The bit error rate performance at 10 Gbps is summarized in Figure.4-8. The tolerated power level is up to 0 dBm by the built in automatic gain control scheme. The input referred noise current (IN) of the optical receiver is derived from its sensitivity performance. As
r dBm
where ρ is the responsivity of photo detector, and re is the extinction ratio. The corresponding IN is approximately 6.68 µA.
Figure.4-9 illustrate the corresponding 10 Gbps eye diagrams at sensitivity level with 231 − 1 PRBS inputs and bit error rate less than 10−12. Figure.4-10 illustrate the corresponding 10 Gbps eye diagrams at overload level of the same pattern length and bit error rate less than 10−12. Operating under a 1.8V supply, the power dissipation is 199 mW, among which 35 mW is consumed by output buffer. Figure.4-11, Figure.4-12, Figure.4-13, and Figure.4-14 illustrate the corresponding eye diagram at 1.25Gbps, 5Gbps, 7Gbps, and 10Gbps with 231-1 PRBS input at a bit error rate of 10-12 . Figure.4-14 illustrates the chip photo. Fabricated in a 0.18µ m CMOS technology, chip size is 1300 µm × 1566 µm.
Fig. 4-8: 10Gbps bit error rate performance with 231-1 PRBS input.
Fig. 4-9 : 10Gbps eye diagram @ -13dBm sensitivity level with 231-1 PRBS input.(X axis:16.2ps/div, Y axis: 100mV/div, Jitter(pp)=30.96ps)
Fig. 4-10 : 10Gbps eye diagram @ 0dBm overload level with 231-1 PRBS input.(X axis:16ps/div, Y axis: 100mV/div, Jitter(pp)=36.27ps)
Fig. 4-11: 1.25Gbps eye diagram with 231-1 PRBS input. (X axis: 132.1ps/div, Y axis: 96.9mV/div, Jitter(pp)=58.7ps).
Fig. 4-12 : 5Gbps eye diagram with 231-1 PRBS input. (X axis: 33.3ps/div, Y axis:
100mV/div, Jitter(pp)=24.42ps).
Fig. 4-13 : 7Gbps eye diagram with 231-1 PRBS input. (X axis: 24ps/div, Y axis:
97.3mV/div, Jitter(pp)=30.93ps).
Fig. 4-14 : 10Gbps eye diagram with 231-1 PRBS input.(X axis:50ps/div, Y axis:
Fig. 4-15 : Optical receiver AFE chip photograph.
4.6. Conclusion
This paper describes the design of a fully-integrated 10 Gbps optical receiver analog front-end in a generic 0.18 µ m CMOS technology. The optical AFE provides a conversion gain of 90 dBΩ and -3 dB bandwidth of about 7.86 GHz, which is limited by the transimpedance amplifier. A regulated cascode input stage is utilized to decouple the loading effect at the input node, and wide bandwidth is achieved by means of shunt feedback and inductive peaking. Instead of using bulky planar inductors or two asymmertric 3-D inductors, this paper proposes a novel fully symmetric 3-D transformer for inductive peaking in each differential pair. Thus the chip area can be greatly reduced. Moreover, an AGC is built in to alleviate overload
induced data jitter. The proposed architecture is suitable for both low cost and low voltage applications.
Table I summarized the performance comparison between this work, our previous work in [32] and the prior arts in [25][30][31]. By single chip integration, gain-bandwidth requirement for individual building blocks can be rearranged and further optimized. The proposed prototype is both power and area efficient while manifesting good performance.
This work [25] [30] [31] [32]
Function TIA+AGC+LA Single Chip
LA LA and TIA
chip sets
TIA TIA+AGC+LA Single Chip
Power 199mW (1.8V) 150mW(1.8V) TIA:108mW LA:360mW (1.8V)
137mW(1.8V) 210mW(1.8V)
Technology 0.18 µm 0.18 µm 0.18 µm 0.18 µm 0.18 µm
Inductor Counts
7 24 N.A. 2 9
GBW 248.5 THz-Ω 2.97 THz 11.7 THz-Ω(TIA) 1.19 THz(LA)
4.6 THz-Ω 135 THz-Ω
Table 4-1 Performance comparison
Chapter 5 Conclusion
This thesis describes the design of optical receiver front-end fabricated in TSMC 0.18µm 1P6M CMOS technology. Furthermore, the design methodology and implementation techniques of optical receiver were presented. Major research results can be summarized as follows.
First, in order to accomplish a high speed circuit at low supply voltage, inductive peaking technique is adopted. An attractive feature of this technique is that the bandwidth enhancement comes with no additional power dissipation. To reduce the chip area and improve the resonate-frequency of the inductive load, an inverting type transformer with symmetric stacked configuration is proposed.
Second, a trans-impedance amplifier with automatic gain control is demonstrated.
The bandwidth is enhanced by the following techniques: (i) A low input impedance TIA is implemented by regulated cascode gain stage consists of a common gate
amplifier with its gate controlled by a negative local feedback loop. (ii) the global feedback is replaced with local feedback to further increase the dominate pole. (iii) Shunt-peaking is adopted to produce an additional zero. Moreover, the gain control is realized by adjusting the gate voltage of the feedback transistor parallel with a fixed passive resistor. Implemented in a 0.18μm digital CMOS process, the input dynamic range is from -13dBm to 0dBm.
Finally, a single chip 10Gbps optical receiver front-end is implemented in 0.18mm CMOS technology, which manifests GBW exceeds that of the state-of-the-arts reported to date. The single chip optical receiver facilitates GBW optimization, and benefits from low power consumption and small form factor.
Bibliography
[1] M. Yoneyama, Y. Miyamoto, T. Otsuji, H. Toba Y.Yamane, T.Ishibashi, and H.
Miyazawa, “Fully electrical 40-Gb/s TDM system prototype based on InP HEMT digital IC technologies,” J. Lightwave Technol., vol. 18, pp. 34-43, Jan.
2000.
[2] M. Mokhtari, T. Swahn, R. H. Walden, W. E. Stanchina, M. Kardos, T. Juhola, G. Schuppener, H. Tenhunen, and T. Lewin, “InP-HBT chip-set for 40Gb/s fiber optical communication systems operational at 3V,” IEEE J. Solid-State Circuits, vol. 32, pp. 1371-1383, Sep. 1997.
[3] M. Lang, Z. Wang, Z. Lao, M. Schlechtweg, A. Thiede, M. Rieger-Motzer, M.
Sedler, W. Bronner, G. Kaufel, K. Kohler, A.Hulsmann, and B. Raynor, “20-40 Gb/s 0.2µ m GaAs HEMT chip set for optical data receiver,” IEEE J.
Solid-State Circuits, vol. 32, pp. 1384-1393, Sep. 1997.
[4] A. Tanabe,M. Soda, Y. Nakahara,T.Tamura, K. Yoshida, A.Furukawa, “A single chip 2.4-Gb/s CMOS optical receiver IC with low substrate cross-talk preamplifier,” IEEE JSSC, vol. 33 No. 12, Dec. 1998, pp. 2148-2153.
[5] K.Ohhata, T. Masuda, K. Imai, R. Takeyari, k.Washio, “A wide-dynamic-range, high transimpedance Si-Bipolar preamplifier IC for 10Gb/s optical fiber links,” IEEE JSSC, vol. 34 No. 1, Jan. 199, pp. 18-24.
[6] John R. Long, “Monolithic Transformers for Silicon RF IC Design”, in IEEE Journal of Solid_State Circuits, pp. 1368- 1382, September, 2000.
[7] Alireza Zolfaghari, Andrew Chan, and Behzad Razavi, “Stacked Inductors and Transformers in CMOS Technology”, in IEEE Journal of Solid_State Circuits , pp. 620- 628, April, 2001.
[8] Chih-Chun Tang, Chia-Hsin Wu, and Shen-Iuan Liu, “Miniature 3-D Inductors in Standard CMOS Process”, in IEEE Journal of Solid-State Circuits, pp.
471-480, April 2002.
[9] Behazed Razavi, “Design of High-Speed Circuits for Optical Communication System,” Custom Integrated Circuits, 2001, IEEE Conference on. , 2001 Page(s): 315 -322
[10] Kim, H.H.; Chandrasekhar, S.; Burrus, C.A., Jr.; Bauman, J., “A Si BiCMOS transimpedance amplifier for 10-Gb/s SONET receiver,” Solid-State Circuits, IEEE Journal of , Volume: 36 Issue: 5 , May 2001 Page(s): 769 –776
[11] Ohhata, K.; Masuda, T.; Imai, K.; Takeyari, R.; Washio, K., “A wide-dynamic-range, high-transimpedance Si bipolar preamplifier IC for
10-Gb/s optical fiber links,” Solid-State Circuits, IEEE Journal of , Volume:
34 Issue: 1 , Jan 1999 Page(s): 18 -24
[12] Maxim Data sheet MAX3970 19-1970; Rev2; 1/02
[13] Kim, H.; Bauman, J., “A 12 GHz 30 dB modular BiCMOS limiting amplifier for 10 Gb SONET receiver,” Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International , 2000 Page(s): 160 -161, 453
[14] Maxim Application Note:HFAN-4.0.1 [15] Maxim Application Note:HFAN-3.0.0
[16] S. S. Mohan, M. Mar Hershenson, S. P. Boyd, and T. H. Lee, “Bandwidth Extension in CMOS with Optimized On-Chip Inductors,” IEEE J. Solid-state Circuits, Vol. 35, No. 3, pp. 346-355, March 2000.
[17] K. Phang and D.A. Johns, “A CMOS Optical Preamplifier for Wireless Infrared Communications:’ IEEE Trans. Circuits and Systems-11: Analog and Digital Signal Processing, Vol. 46, No. 7, pp. 852-859, July 1999.
[18] Ruotsalainen, P. Palojarvi, and J. Kostamovaara, “A Current-Mode Gain-Control Scheme with Constant Bandwidth Delay for a Transimpedance Preamplifier,” IEEE J. Solid-state Circuits, Vol. 34, No. 2, pp. 253-258, February 1999.
[19] M. B. Ritter, E Gfeller, W. Hirt, D. Rogers, S. Gowda, “Circuit and System Challenges in IR Wireless Communication,” Proc. ISSCC, pp. 398-399, February 1996.
[20] C. Toumazou and S. M. Park, “Wide-band low noise CMOS transimpedance amplifier for gigaHertz operation”, Electronics Letters, vol. 32, pp 1194-1 196, June 1996
[21] S. M. Park and C. Toumazou, “Giga-hertz Low Noise CMOS Transimpedance Amplifier”, Proc. IEEE ISCAS, vol. 1, pp 209-212, June 1997
[22] J. Lee, S.-J. Song, S. M. Park, C.-M. Nam, Y.-S. Kwon, and H.-J. Yoo, “A multichip on oxide 1-Gb/s 80 dB fully-differential CMOS transimpedance amplifier for optical interconnect applications,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2002, pp. 80–81.
[23] S. M. Park and H.-J. Yoo, “2.5 Gbit/s CMOS transimpedance amplifier for optical communication applications,” Electron. Lett., vol. 39, no. 2, pp.
211–212, Jan. 2003.
[24] S. M. Park and H.-J. Yoo, “1.25-Gb/s regulated cascode CMOS transimpedance amplifier for gigabit ethernet applications,” IEEE J. Solid- State Circuits, vol. 39, pp. 112–121, Jan. 2004.
laser/modulator driver in 0.18 µ m CMOS technology”, in Proceedings of 2003 IEEE ISSCC Digest of Technical Papers”, pp. 188–189, February, 2003.
[26] Behazed Razavi, Design of Integrated Circuits for Optical Communications.
2002
[27] Wei-Zen Chen and Wen-Hui Chen, ” Symmetric 3D Passive Components for RF ICs Application”, in 2003 IEEE RFIC Symposium Digest of Technical Papers, pp. 599– 602, June 2002. R.O.C and U.S. patent pending.
[28] Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge university press,1998
[29] E.M. Cherry and D. E. Hooper, ” The design of wide-band transistor feedback amplifier”, Inst. Elec. Eng. Proc., vol. 110, no. 2, pp. 375-389, Feb. 1963.
[30] Anders K. Petersen, et al, “ Front-end CMOS chipset for 10 Gb/s communication” in 2002 IEEE RFIC Symposium Digest Digest of Technical Papers, pp. 93–96, June 2002.
[31] Behnam Analui and Ali Hajimiri, ” Multi-pole bandwidth enhancement technique for transimpedance amplifiers”, in Proceedings of 2002 European Solid-State Circuits Conference, pp. 303-306. September 2002.
[32] Wei-Zen Chen, Ying-Lien Cheng, and Da-Shin Lin, ”A 1.8 V, 10 Gbps Fully Integrated CMOS Optical Receiver Analog Front End”, 2004 ESSCIRC, to be presented.
簡歷
姓名:林大新
學歷:精誠高級中學
國立中央大學機械系
國立交通大學電子工程研究所系統組
發表論文:
[1] Wei-Zen Chen, Ying-Lien Cheng, and Da-Shin Lin, ”A 1.8 V, 10 Gbps Fully Integrated CMOS Optical Receiver Analog Front End”, 2004 ESSCIRC, to be presented.
[2] JSSC paper accept.
得獎:
九三年度大學院校混合訊號式積體電路設計碩士論文觀摩競賽優等.