Limiting Amplifier Circuit Schematic

The core circuit of the voltage amplifier is shown in Figure.4-7(a), which is based on Cherry-Hooper circuit architecture with active feedback [25]. Compared to the prior art in [25], the GBW requirement in the front-stage of voltage amplifier is

relaxed and thus no peaking inductor is required to save area. Also, different from our previous work in [32] using resistive feedback, unilateral feedback avoids trade-off between feedback factor (close loop gain) and open loop gain (close loop BW) [25].

The gain cell of slicer is shown in Figure.4-7(b). Herein inductive peaking technique is utilized to accelerate voltage switch and balance rising and falling time at high voltage level.

Fig. 4-7 :Gain Cell of (a) Voltage amplifier, and (b) Slicer.

4.5. Experimental Results

With Oepic-P5030A photo detctor, whose responsivity is 1 A/W, the sensitivity of the optical receiver AFE at 10 Gbps is about -13 dBm for BER less than 10⁻¹². The bit error rate performance at 10 Gbps is summarized in Figure.4-8. The tolerated power level is up to 0 dBm by the built in automatic gain control scheme. The input referred noise current (IN) of the optical receiver is derived from its sensitivity performance. As

r dBm

where ρ is the responsivity of photo detector, and re is the extinction ratio. The corresponding IN is approximately 6.68 µA.

Figure.4-9 illustrate the corresponding 10 Gbps eye diagrams at sensitivity level with 2³¹ − 1 PRBS inputs and bit error rate less than 10⁻¹². Figure.4-10 illustrate the corresponding 10 Gbps eye diagrams at overload level of the same pattern length and bit error rate less than 10⁻¹². Operating under a 1.8V supply, the power dissipation is 199 mW, among which 35 mW is consumed by output buffer. Figure.4-11, Figure.4-12, Figure.4-13, and Figure.4-14 illustrate the corresponding eye diagram at 1.25Gbps, 5Gbps, 7Gbps, and 10Gbps with 2³¹-1 PRBS input at a bit error rate of 10^-12 . Figure.4-14 illustrates the chip photo. Fabricated in a 0.18µ m CMOS technology, chip size is 1300 µm × 1566 µm.

Fig. 4-8: 10Gbps bit error rate performance with 2³¹-1 PRBS input.

Fig. 4-9 : 10Gbps eye diagram @ -13dBm sensitivity level with 2³¹-1 PRBS input.(X axis:16.2ps/div, Y axis: 100mV/div, Jitter(pp)=30.96ps)

Fig. 4-10 : 10Gbps eye diagram @ 0dBm overload level with 2³¹-1 PRBS input.(X axis:16ps/div, Y axis: 100mV/div, Jitter(pp)=36.27ps)

Fig. 4-11: 1.25Gbps eye diagram with 2³¹-1 PRBS input. (X axis: 132.1ps/div, Y axis: 96.9mV/div, Jitter(pp)=58.7ps).

Fig. 4-12 : 5Gbps eye diagram with 2³¹-1 PRBS input. (X axis: 33.3ps/div, Y axis:

100mV/div, Jitter(pp)=24.42ps).

Fig. 4-13 : 7Gbps eye diagram with 2³¹-1 PRBS input. (X axis: 24ps/div, Y axis:

97.3mV/div, Jitter(pp)=30.93ps).

Fig. 4-14 : 10Gbps eye diagram with 2³¹-1 PRBS input.(X axis:50ps/div, Y axis:

Fig. 4-15 : Optical receiver AFE chip photograph.

4.6. Conclusion

This paper describes the design of a fully-integrated 10 Gbps optical receiver analog front-end in a generic 0.18 µ m CMOS technology. The optical AFE provides a conversion gain of 90 dBΩ and -3 dB bandwidth of about 7.86 GHz, which is limited by the transimpedance amplifier. A regulated cascode input stage is utilized to decouple the loading effect at the input node, and wide bandwidth is achieved by means of shunt feedback and inductive peaking. Instead of using bulky planar inductors or two asymmertric 3-D inductors, this paper proposes a novel fully symmetric 3-D transformer for inductive peaking in each differential pair. Thus the chip area can be greatly reduced. Moreover, an AGC is built in to alleviate overload

induced data jitter. The proposed architecture is suitable for both low cost and low voltage applications.

Table I summarized the performance comparison between this work, our previous work in [32] and the prior arts in [25][30][31]. By single chip integration, gain-bandwidth requirement for individual building blocks can be rearranged and further optimized. The proposed prototype is both power and area efficient while manifesting good performance.

This work [25] [30] [31] [32]

Function TIA+AGC+LA Single Chip

LA LA and TIA

chip sets

TIA TIA+AGC+LA Single Chip

Power 199mW (1.8V) 150mW(1.8V) TIA:108mW LA:360mW (1.8V)

137mW(1.8V) 210mW(1.8V)

Technology 0.18 µm 0.18 µm 0.18 µm 0.18 µm 0.18 µm

Inductor Counts

7 24 N.A. 2 9

GBW 248.5 THz-Ω 2.97 THz 11.7 THz-Ω(TIA) 1.19 THz(LA)

4.6 THz-Ω 135 THz-Ω

Table 4-1 Performance comparison

Chapter 5 Conclusion

This thesis describes the design of optical receiver front-end fabricated in TSMC 0.18µm 1P6M CMOS technology. Furthermore, the design methodology and implementation techniques of optical receiver were presented. Major research results can be summarized as follows.

First, in order to accomplish a high speed circuit at low supply voltage, inductive peaking technique is adopted. An attractive feature of this technique is that the bandwidth enhancement comes with no additional power dissipation. To reduce the chip area and improve the resonate-frequency of the inductive load, an inverting type transformer with symmetric stacked configuration is proposed.

Second, a trans-impedance amplifier with automatic gain control is demonstrated.

The bandwidth is enhanced by the following techniques: (i) A low input impedance TIA is implemented by regulated cascode gain stage consists of a common gate

amplifier with its gate controlled by a negative local feedback loop. (ii) the global feedback is replaced with local feedback to further increase the dominate pole. (iii) Shunt-peaking is adopted to produce an additional zero. Moreover, the gain control is realized by adjusting the gate voltage of the feedback transistor parallel with a fixed passive resistor. Implemented in a 0.18μm digital CMOS process, the input dynamic range is from -13dBm to 0dBm.

Finally, a single chip 10Gbps optical receiver front-end is implemented in 0.18mm CMOS technology, which manifests GBW exceeds that of the state-of-the-arts reported to date. The single chip optical receiver facilitates GBW optimization, and benefits from low power consumption and small form factor.

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簡歷

姓名:林大新

學歷:精誠高級中學

國立中央大學機械系

國立交通大學電子工程研究所系統組

發表論文:

[1] Wei-Zen Chen, Ying-Lien Cheng, and Da-Shin Lin, ”A 1.8 V, 10 Gbps Fully Integrated CMOS Optical Receiver Analog Front End”, 2004 ESSCIRC, to be presented.

[2] JSSC paper accept.

得獎:

九三年度大學院校混合訊號式積體電路設計碩士論文觀摩競賽優等.