Briefly, the dissertation has involved physical concept of DT technology with HK/MG MOSFET, WSG-SONOS memory and ZTC model. We describe the merits of DT technology with using experimental data and ISE simulation tool. Moreover, the definite physical insight dependence of elevated temperature is also discussed. Major contributions of each section in thus thesis are summarized as following:
First, the linearly extrapolated threshold voltage of the maximum transconductance method to extract VTH of DTMOS is proposed and then a body effect coefficient extraction analytical expression of DTMOS called m-model includes physical insights is successfully presented in detail. It explains why the DTMOS shows very excellent gate control ability and quite low off-leakage from energy band diagram variation. By using our m-model, it provides an important physical meaning including threshold voltage and body effect coefficient factors for designing body doping profile and work function adjustment for advanced HK/MG short channel device. The different alpha ratio between gate and substrate can be used to achieve our requirement of circuit. In addition, we prove the channel effective mobility can be enhanced by reducing depletion charge under DT mode using split C-V method. The un-ideal short channel including VTH roll-off and DIBL effect would also be improved resulting in lower carrier ballistic transport coefficient and higher injection velocity from source terminal. The higher overdrive of HK/MG device can be still achieved by DTMOS.
Second, a novel dynamic-threshold source-side injection (DTSSI) in WSG-SONOS memory with high performance and reliable multilevel application for 2-bit/cell operation is successfully demonstrated, for the first time. We have investigated the programming mechanism of DTSSI in detail using the experimental data and Integrated Systems Engineering (ISE) TCAD simulation tools. It shows that the supply current (ISG), and the lateral and vertical electric fields adjacent to neutral gap region are the three major factors affecting programming efficiency under DTSSI programming mode. We prove the higher programming efficiency to support high-speed multilevel operation with quite low power consumption can be performed
by appropriate operating voltages for the WSG-SONOS memory. Moreover, the greater noise margin between each level state provides higher flexibility for sensor amplification in circuit design with using DTSSI to achieve programming process.
Further, we also found that the interferences of second bit effect may be almost ignored when operating 2-bit/cell utilizing DT mode in our device. The superior data retention and excellent endurance characteristics indicate the high potential of the WSG-SONOS memory programmed with DTSSI for high-reliability and high-performance embedded memory applications in the green technology.
Finally, for the first time, the new analytical expressions of zero-temperature-coefficient (ZTC) point modeling of DTMOS transistor are successfully presented in detail for both long and short channel device. The maximum error lower than 1% is obtained in the linear and saturation regions, respectively, confirms the good agreement between our DTMOS ZTC point model and experimental data. Moreover, we also establish the fixed body-bias ZTC modeling, simultaneously. The detail physical insights and expressions are also summarized in Table 4.1. The proposed formulations are useful for future integrated circuit design using DT technology.
5.2 Recommendation for Future Research
There are some still unknown physical insights to be studied for future work.
Here are some suggestions as shown as following:
As detailed in our work, the body effect coefficient and metal gate work function choosing are the key factors for high performance with low power consumption application. To enhance the overdrive current for higher body effect coefficient factor, the body doping concentration and profile need to be controlled carefully. However, the doping fluctuation effect in very short channel device is a critical issue due to its depletion charge effect dependence of threshold voltage. Although the retrograde doping profile is used to improve the phenomenon, the threshold voltage variation affects in deep sub-micron DTMOS is still unclear. As a result, the detail process effect for discrete doping effect on VTH is suggested to study with using simulation tools. Furthermore, the adjustment of lower metal work function in DTMOS for very short channel device is also need to be collocated at the same time.
Besides, the mechanism of WSG-SONOS memory with using DTSSI
programming method to achieve multi-level with 2-bits/cell application is described clearly. However, the reliability effect of charge storage lateral spatial distribution with utilizing DTSSI programming method is still needed to be considered. Especially, after cycling effect stress, the serious damage both for tunnel oxide and interface would degrade the reliability resulting from trap-assist-tunneling effect. Once we can prove the lateral spatial distribution of electron injection is different to hot-hole injection by utilizing charge pumping method under different programming mode under, the excellent endurance and good retention of WSG-SONOS memory can be explained clearly. Moreover, the charge storage vertical spatial distribution with utilizing DTSSI programming method is needed to be considered, too. It concerns to the scaled-down issue for good control ability of short channel effect with decreasing charge trapping layer and oxide thickness. The storage nitride layer with silicon-dots has demonstrated its excellent reliability and performance for scaling device.
Therefore, it can be predicted that charge storage layer of WSG-SONOS memory uses nitride layer with silicon-dots can further enhance its electrical characteristics.
Moreover, replacing traditional blocking silicon dioxide layer with high-k material, such as Al2O3, HfO2 and Gd2O3, is suggested to enhance electrical characteristic and reducing power supply voltage. Finally, the performance and reliability of WSG-SONOS memory operates at elevated temperature is suggested to study for its special wrapped-select-gate transistor in its structure. We proposed the DTMOS ZTC point modeling and detailed the physical insights may help WSG-SONOS memory to be more stable at different operation temperature in circuit level. Summary, our recommendations provide the feasibility of DT technology for future green MOSFET era.
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