The Zero-Temperature-Coefficient Point Modeling of DTMOS 4.1 Introduction
4.3.2 The Validation of Zero-Temperature-Coefficient Point Modeling of DTMOS The proposed model is verified using the experimental data obtained from our
Consequently, by solving the equations, we propose formulations for the linear and saturation region of the ZTC point model of the DTMOS transistor, respectively:
Linear region:
4.3.2
The Validation of Zero-Temperature-Coefficient Point Modeling of DTMOS The proposed model is verified using the experimental data obtained from our DTMOS device in which channel length and width is 1 and 10 m for long channel device and 0.1 and 10 m for short channel device, respectively. Figure 4.6 shows the threshold voltage dependences on the temperature from 25°C to 125°C with different body biases. The physical parameters p0, q0, and r0 of the ZTC point model for DTMOS can be extracted easily from our model. In general, the threshold voltage decrease with increasing body bias can be considered a continued reduction of the depletion region in DTMOS, as shown in Fig. 4.7. The straight black line shows that the body bias varies dynamically with gate bias under different alpha ratios and the crossover points shows a gradual reduction in threshold voltage, due to the increase inni with increasing operating temperature. The inset of Fig. 4.8 shows the temperature dependence of the body effect coefficient over the temperature range of 298K to 398K.
The characteristic features s0 and t0 in our ZTC point model of DTMOS are extracted from the slope and extrapolated point of a body effect coefficient versus absolute temperature curve, simultaneously. Figure 4.9 and Fig. 4.10 show the K1 degradation factors dependence of temperature with different alpha ratios under linear and saturation regions, respectively. The higher carrier energy results in the lower values of K1 degradation factors. It can also prove the large enhancement of mobility while operated under DT mode, indirectly. At the same time, the error between our model and experiment is almost neglected, proving our Gm extraction method for K1
degradation factors is feasible. The VG, (ZTC) and K1 dependence of body bias are both shown in Fig. 4.11. It can be found that our fixed body bias mode of ZTC model can still perform excellent prediction results with quite low mismatch to the row data at elevated temperature environment. The detail expressions of fixed body bias ZTC model both under linear and saturation are shown in Table. 4.1. Furthermore, Fig. 4.12 shows the ZTC point of DTMOS can be determinate by row data with different alpha ratios condition under fixed body-bias mode. The maximum error can be reduced smaller than 1% for Poly/SiO2 NMOS. The clear comparison results between our DTMOS ZTC model and experimental data under linear and saturation regions are both shown in Fig. 4.13. The maximum error about 1.5% happens at the transition region through linear region to saturation region. Different alpha ratios prove the good agreement between our model and experimental values. In addition, the variation characteristics of ZTC point operation after stress 2000 sec demonstrate the excellent reliability for DTMOS due to its low operation voltage, as shown in Fig. 4.14. Similar to the silicon dioxide device, the HK/MG devices also show the ZTC point characterization as shown in Fig. 4.15. The VTH and K1 degradation factor dependence of body bias are both shown in Fig. 4.16 and Fig. 4.17. Unlike long channel device, the short channel device shows the smaller K1 degradation factor both under linear and saturation regions in Fig. 4.18 due to its higher carrier transport energy. Then, the temperature effects of body effect coefficient can be extracted from Fig. 4.19.
Different to long channel device, the DIBL effect couldn’t be neglected in short channel device. The temperature effects of DIBL concern parameter can also be extracted from Fig. 4.20 at elevated temperature from 298 K to 398 K. Finally, we demonstrate that ZTC point of both long channel and short channel devices for
traditional or advanced gate stacks can be precise prediction by our DTMOS ZTC model, for maximum error smaller than 1%, with different behaviors of ZTC point under saturation region resulting from DIBL effect. The large improvement for precisely predicted ZTC point can be attracted to the detailed temperature dependence of physical parameters effect, respectively. The detail physical insights and expressions of DTMOS ZTC modeling both under linear and saturation are shown in Table. 4.1, simultaneously. Figure 4.23 and Fig. 4.24 show a clear chart to illustrate the ZTC point position at an ID-VG curve. It locates after the VTH about 0.2 V at linear region and 0.3 V at saturation, respectively. As we know that DTMOS shows the more excellent electrical characteristics at low temperature operation, for predicting ZTC precisely now, the DTMOS operated at quite low temperature can also be performed more reliable. A design window for different DT technology application now can be depicted precisely by utilizing our ZTC modeling, as shown in Fig. 4.25. For high performance operation, the ZTC point would be higher due to increase of power supply voltage. In addition, the higher alpha ratio provides better subthreshold swing and DIBL effect for device characteristics. As a result, we give results sufficiently accurate to predict the ZTC behaviors of DTMOS.
4.4 Summary
Analytical expressions of zero-temperature-coefficient (ZTC) point modeling of DTMOS transistor are successfully presented in detail. The maximum error smaller than 1% are obtained in the linear and saturation regions, respectively, confirms the good agreement between our DTMOS ZTC point model and experimental data. In addition, we also establish the fixed body-bias ZTC modeling, simultaneously. The detail physical insights and expressions are also summarized in Table 4.1. The proposed formulations are useful for future integrated circuit design using DT technology.
Fig. 4.1 ID-VG characteristics and ZTC point of NMOS under normal and DT-modes at elevated temperature from 298 K to 398 K, respectively.
Fig. 4.2 CGC characteristics of NMOS extracted from split C-V method under fixed body-bias and DT-modes at 298 K, respectively.
0.0 0.3 0.6 0.9 1.2 1.5 0.00
0.04 0.08 0.12 0.16
25oC 45oC 65oC 85oC 105oC 125oC
V
G(V) I
D( m A )
VG,(ZTC)
= 0.85V
VG,(ZTC)
= 0.96V Hollow:Normal mode
L/W=1/10m
Solid:DT mode @ VD = 0.1 V
0.0 0.2 0.4 0.6 0.8 1.0 0.00
0.02 0.04 0.06 0.08 0.10
Split C-V method