NW crossbar circuits

Implementation of the nanowire devices in ultra-high density, large-scale application will likely in turn require the implementation of novel architectures.

This includes both nano-architectures at the circuit level that link large numbers of devices with each other and with external systems to perform memory and/or logic functions as well as system architectures that allow the circuits to communicate with other systems and operate independently of their lowerlevel details. In particular, since traditional defect-free oriented processes will likely no longer be feasible at the molecular scale, the new architectures must be defect-tolerant. Reconfigurable architectures, particularly crossbar structures in which active devices are formed at the intersections when two sets of wires cross each other, have been demonstrated to possess desirable properties at both the nano-architecture as well as the system-architecture level. In an earlier proof-of-concept study, Duan et al and Huang et al have shown that prototype logic circuits can be achieved on crossed nanowire p/n junctions. In these studies, the cross-wire structures were achieved via flow alignment, and devices at the single to few NW levels were examined. To implement desired hierarchical patterning of arrays of aligned and crossed NWs at centimetre scale, Whang et al developed a technique in which locating individual NWs to the desired positions is no longer required. In Whang’s approach, a monolayer of aligned NWs was produced first via the LB approach.

Photolithography was then used to define a pattern over the entire substrate surface which sets the array dimensions and array pitch. Finally, NW soutside the patterned array were removed by gentle sonication, resulting in arrays of parallel NWs at desired locations (Fig. 103). To produce crossed NW arrays, sequential layers of aligned NWs were transferred in an orthogonal orientation and were patterned in the same fashion as described above (Fig. 103). Fig.

103(C) shows an image of a 10μm×10 μm square array with a 25μmarray pitch, and demonstrates that such a method provides ready and scalable access to ordered arrays over large areas. The nanowire array exhibits order on multiple length scales: 40nm diameter NWs, 0.5μm NW spacing, 10μm array size, 25μm array pitch repeated over centimetres—that is representative of the substantial control enabled by the LB approach. Array geometries and tiling patterns more complex than square structures are also believed to be

achievable.

Figure 7 (A) Hierarchical patterning of crossed NW arrays by photo-lithography, where NWs are removed from regions outside of the defined array pattern. (B) Dark-field optical micrograph of crossed NWs deposited uniformly on a 1 cm × 1 cm substrate. Scale bar: 50μm. (C) SEM image of patterned crossed NW arrays. Scale bar: 10μm.

(Inset) Large area dark-field optical micrograph of the patterned crossed NW arrays.

Scale bar: 100μm. (D) SEM image of an ultra-high density crossed NW array. Scale bar: 200 nm.

【Gambino J P and Colgan E G 1998 Mater. Chem. Phys. 52 99】

6.7 Conclusion

The area of semiconductor NWs has been constantly gaining interest and momentum among science and engineering communities since the late 1990s.

In this review, we attempted to summarize progresses made in this field during the last several years, ranging from nanowire growth with precise control at the atomic level to device characterization that probes novel properties in 1D systems and novel device structures, and to integration and assembly methods of large numbers of NWs for practical applications. The key ingredients in the semiconductor nanowire system include the single-crystalline nature of the material, strong quantum confinement effects due to the small diameter and the ability to carry out tailored growth with desired shape, size and material composition (including radial and axial nanowire heterostructures). The separation of high-temperature growth and low-temperature device fabrication processes also implies that nanowire devices are well suited to applications on non-crystalline substrates such as flexible electronics. Because of their high carrier mobility and large surface

area, semiconductor NWs have also been studied in a variety of applications besides high-performance electronics, including dye-sensitized solar cells, label-free, ultrasensitive bio-and chemical sensors. By exploiting the optical cavity and/or waveguide properties of the semiconductor material, nanowire-based on-chip photonic devices and circuits have been demonstrated as well, including light-emitting diodes, lasers, active waveguides and integrated electro-optic modulators. Such topics are beyond the scope of this reviewand interested readers are referred to the corresponding references listed above.

Reference

z http://en.wikipedia.org/

z 莊達人, VLSI 製造技術, 2004/06/20, version.5, P684/666.

z Hong Xiao, Introduction to semiconductor Manufacturing Technology, 2001/05/27.

z 吳文發、秦玉龍, NDL 奈米通訊-第六卷第一期, 電遷移效應對銅導線可 靠度之影響.

z Y.C. Hu, Y.H. Lin, and C.R. Kao, Electromigration failure in flip chip solder joints due to rapid dissolution of copper, 2003/08/22.

z Cadence design system, Learning to live with electromigration, 2002.

z Dieter K. Schroder, Electromigration, Arizona State University.

z Solid State Technology May, 2000.

z 楊金成、柯富祥、王美雅、王天戈, NDL 奈米通訊-第六卷第四期, 金屬

雜質於DUV 光阻中擴散及吸附行為之研究(I).

z http://www.physik.uni-marburg.de/, Surface Diffusion of Adsorbates, Page updated 3 June 2006.

z Huajian Gao, Crack-Like Grain Boundary Diffusion Wedges in Thin Films on Substrates.

z H.GAO, L.ZHANG, W.D.NIX, C.V.THOMPSON and E.ARZT, Crack-Like Grain-Boundary Diffusion Wedges in Thin Metal Films, 22 May 1999.

z http://math.berkeley.edu/~sethian/2006/Semiconductors/ieee_surfac e_diffusion.html

z CSL, 2005,

http://www.csl.mete.metu.edu.tr/Electromigration/emig.htm

z S.Thompson etc. A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, 2002 IEDM pp61-64

z 2005 International Technology Roadmap for Semiconductor

z 2006 update International Technology Roadmap for Semiconductor z H. S. P. Wong, "Beyond the conventional transistor," IBM Journal of

Research and Development, vol. 46, pp. 133-168, 2002.

z Mobility-enhancement technologies , Chee Wee Liu, S. Maikap, and C.-Y. Yu , IEEE CIRCUITS & DEVICES MAGAZINE MAY/JUNE 20056.S. C. Sun and J. D. Plummer, IEEE Trans. Electron Devices ED-27, 1497 (1980).

z S.-I. Takagi, A. Toriumi, M. Iwase, and H. Tango, IEEE Trans. Electron Devices 41, 2357 (1994).

z S.-I. Takagi, A. Toriumi, M. Iwase, and H. Tango, IEEE Trans. Electron Devices 41, 2363 (1994).

z Subband structure engineering for performance enhancement of Si MOSFETs IEDM-97 pp219-222

z Strained silicon MOSFET technology , IEDM-2002 pp 23-25

z S.Thompson etc Uniaxial-process-induced strained-Si extending the CMOS roadmap ,E.D, vol.53,pp1010

z M. Qin, V.M.C. Poon, S.C.H. Ho, J. Electrochem. Soc.

148 (2001)271.

z W.P. Maszara, Z. Krivokapic, P. King, J.-S. Goo, M.-R. Lin, 2002IEDM Tech. Dig. 367 (2002).

z J. Kedzierski, D. Boyd, P. Ronsheim, S. Zafar, J. Newbury, J. Ott, C.

Cabral Jr., M. Ieong, W. Haensch, 2003 IEDM Tech. Dig. 315 (2003).

z M.A. Pawlak, A. Lauwers, T. Janssens, K.G. Anil, K. Opsomer, K.

Maex, A. Vantomme, J.A. Kittl, IEEE Electron. Device Lett. 27 (2006) 99.

z C. Cabral Jr., J. Kedzierski, B. Linder, S. Zafar, V.

Narayanan, S. Fang, A. Steegen, P. Kozlowski, R.

Carruthers, R. Jammy, 2004Symp. VLSI Tech. Dig. 184 (2004).

z M. Terai, K. Takahashi, K. Manabe, T. Hase, T. Ogura, M. Saitoh, T.

Iwamoto, T. Tatsumi, H. Watanabe, 2005 Symp. VLSI Tech. Dig.68 (2005).

z J.A. Kittl, A. Veloso, A. Lauwers, K.G. Anil, C.

Demeurisse, S. Kubicek, M. Niwa, M.J.H. van Dal, O. Richard, M.A.

Pawlak, M. Jurczak, C. Vrancken, T. Chiarella, S. Brus, K. Maex, S.

Biesemans, 2005 Symp. VLSI Tech. Dig. 72 (2005).

z J.A. Kittl, M.A. Pawlak, A. Lauwers, C. Demeurisse, K. T. Kauerauf, M. Jurczak, S. Biesemans, 2004 IEDM Tech. Dig.

855 (2004).

z A. Lauwers, A. Veloso, T. Ho mann, M.J.H. van Dal, C. Vrancken, S.

Brus, S. Locorotondo, J.-F. de Marne e, B. Sijmus, S. Kubicek, T.

Chiarella, M.A. Pawlak, K. Opsomer, M. Niwa, R. Mitsuhashi, K.G.

Anil, H.Y. Yu, C. Demeurisse, R. Verbeeck, P. Absil, K. Maex, M.

Jurczak, S. Biesemans, J.A. Kittl, 2005 IEDM Tech. Dig. 661 (2005).

z J.P. Gambino, E.G. Colgan, Mater. Chem. Phys. 52 (1998) 99.

z C. Lavoie, F.M. d＇Heurle, C. Detavernier, C. Cabral Jr., Microelec- tron. Eng. 70 (2003) 144.

z J.A. Kittl, A. Lauwers, M.A. Pawlak, M. Van Dal, A. Veloso, K.G. Anil, G. Pourtois, C. Demeurisse, M. de Potter, C. Vrancken, K. Maex, Microelectron. Eng. 82 (2005) 441.

z M.A. Pawlak, J.A. Kittl, O. Chamirian, A. Veloso, A.

Lauwers, T. Schram, K. Maex, A. Vantomme, Microelectron. Eng. 76 (2004) 349.

z R. Chau, 30 nm and 20 nm physical gate length CMOS transistors, Abstr. Silicon Nanoelectronics Workshop (2001)2–3.

z S. Song, J.H. Yi, S. Kim, J.S. Lee, K.I. Fujiwara, H.K. Kang, J.T. Moon, M.Y. Lee, CMOS device scaling beyond 100nm, IEDM Tech. Dig.

(2000) 235–238.

z C.-J. Choi, J.-H. Ku, S. Choi, K. Fujiwara, J-T. Moon, Ni salicide technology for deep sub-quarter micron, Proc. ESC Symp ULSI Process Integration, vol. PV-2001-2 (2001) 565–570.

z J-.H. Ku, C.-J. Choi, S. Song, S. Choi, K. Fujiwara, H.-K. Kanhg, S.-I. Lee, High performance pMOSFETs with Ni(Six Ge1 2 x ) / poly-Si0.8 Ge0 .2 gate, Symp. VLSI Tech.

Dig. Tech. (2000) 76–77.

z I. Kunishima, K. Suguro, T. Aoyama, J. Matsunaga, Homogeneous heteroepitaxial NiSi2 formation on (100)Si, Jpn. J. Appl. Phys. 29 (1990) L2329.

z G.J. Huang, L.J. Chen, Effects of crystallinity and thickness of silicide layer and substrate, J. Appl. Phys. 78 (1995) 929.

z Tsong-Jen Yang, Wen-Luh Yang and Po-Min Lo ｀ ＇ Selective Deposition NiP as Diffusion Source to Form n+p Junction and NiSi Simultaneously ＇ ＇ , Department of Materials Science and Engineering , Feng Chia University Department of Electronic Engineering, Feng Chia University

z F.A.Harraz,T.Sakka,and Y.H.Ogata , “ Immersion plating of nickel

onto a porous silicon layer from fluoride solutions

“phys.stat.sol.(a)197,NO.1,51-56(2003)

z Meng-Chi Chen, Chen*, Yean-Kuen Fang**,,“The Studies of Contact Reactions Among Tungsten Plug, Copper Plug, CoSi2 and NiSi in Deep Submicron ULSI Technology “, Department of Electrical Engineering National Cheng Kung University

z 吳文發 ,“金屬矽化物的研製 “奈米通訊第五卷第 2 期

z Hong Xiao, “ Introduction to Semiconductor Manufacturing Technology “,Prentice Hall

z 楊藏嶽 ,“電化學及應用 “,中國電機工程學會

z Introduction to Flash Memory,vol.91,no.4,april 2003 z 產業評析：相變化記憶體市場機會之探索(陳俊儒) z 技術專文：奈米晶粒記憶體技術(曾培哲)

z 中央大學：選擇性氧化複晶矽鍺形成鍺量子點及其在金氧半浮點電容之 應用(曾韋傑)

z 聯合大學：A Study of Device and Reliability Measurements in the 0.25um Split Gate Flash Memory(張逸凡)

z 中原大學：The Study of ONO and Memory Applications(葉智仁) z Flash Memory Cells-An Overview.vol.85,no.8,august 1997

z A Study on ONO Tunneling Current and Data Retention Effects in Stacked-Gate Flash Memories.

z 中原大學：The Study of Si-implanted Oxide-Nitride-Oxide(ONO) for Memory Applications(郭百均).

z 2005 International Technology Roadmap for Semiconductors.2005 Edition available online at http://public.itrs.net/

z Frank D J, Dennard R H, Nowak E, Solomon P M, Taur Y and Wong H-S P 2001 Proc. IEEE 89 259

z Likharev K K 2003 Electronics below 10 nm, in Nano and Giga

Challenges in Microelectronics (Amsterdam: Elsevier)

z Lieber C M 2003 MRS Bull. 28 486

z Wagner R S 1970 Whisker Technology (New York: Wiley)

z Yamanaka M, Sakata I and Sekigawa T 2000 Japan J. Appl. Phys. 39 3302

z Yang C, Zhong Z and Lieber C M 2005 Science 310 1304 z Wu Y and Yang P 2001 J. Am. Chem. Soc. 123 3165

z Kong Y C, Yu D P, Zhang B, Fang W and Feng S 2001 Appl. Phys.

Lett. 78 407

z Qian C, Kim F, Ma L, Tsui F, Yang P and Liu J 2004 J. Am. Chem.

Soc. 126 1195

z Cui Y, Zhong Z, Wang D, Wang W U and Lieber C M 2003 Nano Lett.

3 149

z Gambino J P and Colgan E G 1998 Mater. Chem. Phys. 52 99 z 林鴻志,“深次微米閘極技術之發展與未來驅勢(II)