Future development

5.10.1 MRAM memory and FeRAM

Magnetic core memories were used in early mainframe computers. The modern magnetic RAM is primarily a development of the last two decade.

Magnetization is a result of the electrons spin in a ferromagnetic metal such as iron, cobalt and nickel. The magnetic field applied on MRAM magnetizes these materials. MRAM store information as the orientation of magnetization of a ferromagnetic region. FeRAM is currently one of several "advanced"

non-volatile memory (NVRAM) technologies that are attempting to gain acceptance as an alternative to flash by avoiding its key weaknesses – high program and erase voltages, slow programming speed, write-erase endurance that is limited to ~105 cycles. Compared to its primary competitors among the new NVRAM technologies, MRAM and PRAM, FeRAM is more mature with volume production at Fujitsu beginning in 1999.

Fig. 93 FeRAM structure and operation element

【奈米電子元件技術組電子所：非揮發性記憶體(NVM)、相變化記憶體(PCM)(高明哲)】

Ferro electric memories have also been developed for many years. The ferroelectric RAM cell stores data in a capacitor which uses a ferroelectric film as the dielectric. Once the voltage is applied on of the crystal cells in the ferroelectric film. The polarization effect with two net stable states when the applied voltage is removed.

Fig. 94 Logic element

【電子月刊，鐵電記憶元件特輯，April,2002】

5.10.2 Phase Change Memory

Phase change random access memory (PCRAM) is one of the candidates for next generation RAMs and could be competitive with Flash memory due to its amazing characteristics, such as high-density, high-speed, non-volatility and scalability. However, several problems remain to be solved before commercialization of PCRAM. One of the biggest problems is the quite high reset current during the operation. There were many proposals to reduce the reset current. For example, N-doping into Ge2Sb2Te5 was found to successfully decrease the reset current and becomes a suitable chalcogenide material in PCRAM due to its higher electrical resistivity in the crystalline phase.

Special device designs were also reported to improve this property, such as an edge-contact type cell, µ Trench PCRAM cell, and lateral PCRAM cell and phase change line memory. Furthermore, it was also reported that by inserting a high resistive heating layer (~10 nm) between the bottom electrode and the phase-change material could successfully decrease the operation current. The simulation results suggested that a suitable inserted heating layer should possess an electrical resistivity (ρelec) higher than 0.1 Ω cm, and with thermal conductivity κ and specific heat as low as those of phase-change material, such as Ge2Sb2Te5. Therefore, a device with a highly resistive TiON layer (~7 nm) which was sandwiched between the TiN bottom electrode and Ge1Sb2Te4 revealed lower reset and set voltages than those without. It is believed that the selection of the right materials as inserted heating layers could be an excellent way to facilitate the commercialization of PCRAM.

Earlier study showed that interfacial instability including the inter-diffusion between the chalcogenide material and the bottom electrode is one of the main reasons for the low cycle life of PCRAM cells. Ternary systems of the type TM-Si-N (TM = Ti, Ta, Mo or W) have

Specifically, many researches were done on Ti-Si-N films because of their outstanding barrier performance in Cu metallization. Therefore focused researches of Ti-Si-N films were on the deposition and resultant characteristics of such films, while others were on the formation of nano-composite structures and the related mechanical properties.

The purpose of this study was to contribute a useful heating layer, which would in the meantime also act as a diffusion barrier for PCRAM of a long cycle life. The material was based on Si-rich SiTiNx composition with a high electrical resistivity falling in the range of simulation proposal.

Such films were expected to be different from the highly conductive Ti-rich Ti-Si-N for interconnects in Cu processing.

Fig. 95 Phase Change Memory structure and Temperature-Time curve

【奈米電子元件技術組電子所：非揮發性記憶體(NVM)、相變化記憶體(PCM)(高明哲)】

5.11 Conclusion

Silicon-oxide-nitride-oxide-silicon (SONOS) becomes more and more attractive because of its high compatibility with existing CMOS logic processes and simplicity in device structures. Recently, the two-bit operation of SONOS which used channel hot electron injection to program and hot hole enhanced injection to erase attract more and more practical applications. It can easily achieve cost reduction simply by doubling the bit counts in the same area.

However, its reliability issues are considered as challenges to be solved in the near future. Because of the Frenke-Poole emission and oxide trap assisted tunneling, the program-state threshold voltage has a negative shift. And the net positive charge in the bottom oxide assisted the substrate electron injecting cause the erase-state threshold voltage has a positive shift. It is not easy to predict that how the flash will be developed in the future，but it is necessary to developed it to become tiny, fast, and a big capacity.

Chapter 6 Nanowires

6.1 Abstract

Semiconductor nanowires (NWs) represent a unique system for exploring phenomena at the nanoscale and are also expected to play a critical role in future electronic and optoelectronic devices. Here we review recent advances in growth, characterization, assembly and integration of chemically synthesized, atomic scale semiconductor NWs. We first introduce a general scheme based on a metal-cluster catalyzed vapor–liquid–solid growth mechanism for the synthesis of a broad range of NWs and nanowire heterostructures with precisely controlled chemical composition and physical dimension. Such controlled growth in turn results in controlled electrical and optical properties. Subsequently, we discuss novel properties associated with these one-dimensional (1D) structures such as discrete 1D subbands formation and Coulomb blockade effects as well as ballistic transport and many-body phenomena. Room-temperature high-performance electrical and optical devices will then be discussed at the single- or few-nanowire level. We will then explore methods to assemble and integrate NWs into large-scale functional circuits and real-world applications, examples including high-performance DC/RF circuits and flexible electronics. Prospects of a fundamentally different ‘bottom-up’ paradigm, in which functionalities are coded during growth and circuits are formed via self-assembly, will also be briefly discussed.

6.2 Introduction

Great advances in integrated circuit technologies have been accomplished during the past four decades that resulted in electronic devices with higher device density, faster clock rate and lower power consumption.

However, as the devices reach deep sub-100 nm scale, conventional scaling methods which maintain the device’s basic structure while shrinking its size face increasing technological and fundamental challenges. For example, device size fluctuations will result in a large spread in device characteristics at the nanoscale, affecting key parameters such as the threshold voltage and on/off current. Increasing demand on the resolution of the equipment and

expenses of building and operating the facilities also pushes the traditional approach towards its practical limit and hinders device scaling from reaching true atomic level. To sustain the historical scaling trend beyond CMOS, novel one-dimensional (1D) structures, including carbon nanotubes (CNTs) and semiconductor nanowires (NWs), have been proposed as the active components (as well as interconnects) in future nanoscale devices and circuits.

In this case, the critical device size is defined during the growth (chemical synthesis) process and can be controlled with atomic scale resolution. To date, great efforts and progress have been made in the field of CNTs, although CNT based applications are still hindered by difficulties to produce uniform, semiconducting nanotubes. On the other hand, semiconductor NWs can be prepared with reproducible electronic properties in high-yield, as required for largescale integrated systems. Furthermore, the well-controlled NW growth process implies that materials with distinct chemical composition, structure, size and morphology can be integrated. Such an ability to build specific functions into the system during growth may in turn lead to bottom-up assembly of integrated circuits, which offers the potential of parallel production of massive number of devices with similar material and electrical/optical properties. Drastically different from the ‘top-down’ paradigm commonly used in today’s semiconductor industry, this ‘bottom-up’ paradigm, analogous to the way that nature works, may prove to be a suitable solution to the technological challenges as devices approach atomic size. From a fundamental physics point of view, the low dimensional nanowire structure is an ideal platform to probe properties which may be inaccessible or hard to achieve in larger devices, due to the reduced device size and ideal material properties. For example, discreteness of electrons comes into play when the Coulomb energy associated with the addition of an individual electron becomes larger than the thermal energy; 1D quantum wires and zero-dimensional quantum dots (QDs) form when the relevant device size is comparable to the de Broglie wavelength of the carriers. As a result, the electrical and optical properties in these nanoscale devices are determined not only by the materials composition but can also be tailored by the specific device geometry.