先進的金氧半場效發射電晶體技術

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報告題名：

Advanced MOSFET Technologies

作者：劉品麟、楊登偉、黃方澤、張新宏、王啟安、劉憲融系級：電子工程學系碩一、產業研發專班碩一學號：M9510853、M9519987、M9593990、M9595027、M9595000、M9595014 開課老師：李景松副教授課程名稱：高等半導體元件開課系所：電子工程學系開課學年：95 學年度第 2 學期

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中文摘要

多方功能性與複雜性的積體電路組合近來增加的很快速。在 1990 年後，藉著縮小的元件和線寬的尺寸這些複雜的特性被完成，且還需要去藉著使用較低電阻值的銅去取代鋁合金來降低電路延遲。電致遷移(EM)，金屬的質量傳輸是由於導電的電子和擴散金屬原子之間的動能轉換，和存在的電流流通在金屬導線上。電致遷移已經在 100 年多前就已經被大量的發現，1996 年的早期的 IC 製造出來的時期是它第一次被揭發和持續有問題出現。電致遷移是未來在後段製程研究的主要影響因素。另外，在這 20 年來，應力通道技術被完全檢驗，因為它增強了載子在元件驅動電流移動的主要因素的貢獻。為了 CMOS 高的效能，近來他有被提出整合入積體電路工業裡。雖然有很多的方法去尋找高增強型的元件，但應力技術是很有希望的候選者之一。接下來的章節我們將探討在一般(100)矽基板的矽通道的應力。我們將討論基本的矽應力的物理機制、近來提出的技術和未來的目標。互補式金氧半製程是最重要的半導體積體電路技術，舉凡記憶體及邏輯等多樣化的產品皆以此作為發展的原動力，相關產業也因而興盛不已。一個 MOS 電晶體元件是以閘極作為控制電極，即以閘極的電壓訊號控制電晶體的輸出特性。傳統上，是以含高濃度 n 型雜質的多晶矽做為此閘極材質。進入深次微米紀元後，相關的閘極技術有很大的變革，也面臨許多的挑戰及問題待突破與解決，包括材料種類、形成方式、及可靠性等。除了以上簡短說明之外，此報告將還會針對 MOSFET 應用方面，如無電鍍化學、Flash、奈米科技的應用‧‧‧等等作更深一步的探討。

關鍵字：Electromigration、Strain、FUSI、Electroless plating、

Flash、Nanowires.

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English Abstract

Functionality and complexity of circuit components in integrated circuits have recently increased rapidly. These complex features have been achieved by reduction in the dimensions of both the devices and wiring. In the 1990s, the need to reduce circuit delays prompted the replacement of Al alloy with lower resistivity Cu.

Electromigration (EM), the mass transport of a metal due to the momentum transfer between conducting electrons and diffusing metal atoms, and the current flows exist and through metal wires. The electromigration was discovered more than 100 years ago, it first showed up in ICs as early as 1966 and has been a persistent problem since the early days of IC manufacturing. The electromigration is mainly factor to study for backend process in future.

Further, the strained channel technology has been examined over twice decades because it enhances the carrier mobility contributing to the device drive current. Recently It has be proposed to be integrated into integrated circuit industry for the CMOS higher performance. Although there are many methods to seek for higher device performance enhancement, but the strain technology is the promising candidate. In this chapter we will focus on the strained silicon channel on general (100) silicon wafer. We will discuss the fundamentals of strained silicon physic mechanism, the recent proposed technology and the future work.

A study of the implementation of FUSI gates to scaled devices is presented, addressing the issue of phase control at short gate lengths. A linewidth effect for Ni FUSI gates is found for non-optimized processes targeting NiSi, with formation of NiSi at long gate lengths and Ni-rich silicides at short gate lengths. This is attributed to Ni diffusion from areas surrounding the gates, resulting in a larger reacted Ni-Si ratio at short gate lengths. The linewidth dependence of the Ni FUSI phase results in an undesirable kink in the Vt roll-off characteristics, due to the difference in effective work function between the Ni silicide phases, which is particularly large for HfSiON dielectrics. An optimized 2-step RTP silicidation process is shown to eliminate this problem allowing the formation of NiSi gates uniformly at all gate lengths. The application and scalability of Ni-rich silicides to PMOS devices is also demonstrated, as well as a scheme for CMOS integration of dual WF phase

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controlled FUSI, using an etch back step to reduce the poly-Si height on PMOS electrodes before full silicidation.

Except as above brief description, the paper will continued focus the application for MOSFET device, as electroless plating, flash, nanowires technology…etc, and it will discuss them detailed.

Key Word:

Electromigration、Strain、FUSI、Electroless plating、

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nanowires 83

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6.2 Introduction 83 6.3 Growth of NWs 85

6.3.1 The vapour–liquid–solid growth method 85

6.3.2 Nanowire heterostructures 87

6.3.2.1 Radial nanowire heterostructures 88

6.3.2.2 Axial nanowire heterostructures 88 6.3.3 Growth of metal oxide NWs 89

6.4 Nanowire electronic devices 90

6.4.1 Field-effect transistor devices 90

6.5 Assembly and integration techniques 93

6.5.1 Fluidic flow-directed assembly technique 94 6.6 Nanowire circuits 96

6.6.1 NW crossbar circuits 96 6.7 Conclusion 97

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Chapter 1 Electromigration

1.1 Introduction

When electrons flow through wires on a chip, they collide with metal atoms, producing a force on the atoms, exists wherever wires break over the chip’s lifetime. When early ICs were returned from the field and examined under a microscope, very fine “cracks” in the wires were found. To avoid the damages that which make the metal wires thicker. Making wires thicker was easy when they were 10 microns wide, but it can’t satisfy today’s 90 nanometer and 65 nanometer technologies.

The conditions necessary for electromigration to be a significant problem continue to bear down on us with increasing speed Æ high current densities, long narrow wires, logic hazards, and high operating frequencies. The transition was solved the electromigration problem from aluminum wires to copper wires. The copper has made electromigration analysis of chips more complex in fact. Reduced wire size in both width and thickness and higher frequencies continue to push the current densities wires can handle. Wire slotting and via haracteristics in copper also lead to more complex design rules for electromigration.

Let us briefly examine the advantages for using Cu and arrive at some feel for the driving force for its use. Cu has a room-temperature resistively about 60% that of Al. Naively, this might lead one to think that a substantial increase in speed may be achieved by its use, but careful analyses indicate that the benefit realized from the lower resistance is minimal. Therefore the primary benefit for the replacement of Al-base alloys with Cu is for reliability purposes and the reduction of electromigration-induced damage in the higher melting point slower-diffusing metal. In addition, if the reliability did not alloy an increase in the current density, the benefit is hardly realized, since the processing of Cu alloy is so much more difficult at this time, therefore it is more appropriate when comparing competing metallurgical schemes, to speak of increase allowable current density and not of increased lifetime.

The IC designers need tools that can find and help fix eletromigration problems during the design stage before they become problems in silicon.

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At the high current densities typical in thin-film conductors on integrated circuits, there is significant momentum transfer from the electrons to the atoms. The microstructure of the metallization leads to the consequent atomic flow being non-uniform, and damage results in the form of voids or hillocks.

The temperature and electron wind force are main factor for electromigration.

1.1.1 History

The phenomenon of electromigration has been known for over 100 years, having been discovered by the French scientist Gerardin.

The topic first became of practical interest in 1966 when the first integrated circuits became commercially available.

In this field, the research was pioneered by James R. Black, who set the basis for all research in this area and after whom Black's law (Black's equation) is named. As below Fig. 1.

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1.1.2 Practical implications of EM

The phenomenon of electromigration will let metal line to open or short. At the time the metal interconnects in ICs were still about 10 micrometres wide. Currently interconnects are only micrometres or nanometers in width making research in electromigration increasingly important.

Electromigration was identified first as a serious reliability concern on the Al-based integrated circuit (IC) in 1967. More than thirty years later, electromigration remains a dominant reliability concern for the modern IC due to the aggressive decrease of interconnect dimensions and the comparably aggressive increase of current densities required during operation (Fig. 2).

Simultaneously, the need to lower capacitance in the interconnect system in order to further decrease RC-delay has motivated the implementation of low-k inter-level dielectric (ILD) materials in place of the traditional SiO2-based material (Fig. 3).

Fig. 2 The requ1red current density at operating conditions continues to rise with time as depicted by the International Technology Roadmap for Semiconductors, 2002 edition. 【Christine S. Hau-Riege, An introduction to Cu electromigration, 20 October 2003, p2】

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Fig. 3 The minimum effective dielectr1c constant needed for the continuous decrease in RC-delay, as depicted by International Technology Roadmap for Semiconductors, 2002 edition.

【Christine S. Hau-Riege, An introduction to Cu electromigration, 20 October 2003】

1.1.3 Fundamentals

The characteristics are predominantly: z The composition of the metal alloy. z The dimensions of the conductor. The shape of the conductor:

z The crystallographic orientation of the grains in the metal. z The layer deposition.

z Heat treatment or annealing. z The passivation characteristics. z The interface to other materials.

Æ As above, there are affected the durability of the interconnect lines. The time dependent current:

z Direct current. z Alternating current.

Forces on ions in an electrical field:

z Two forces affect ionized atoms in a conductor. The direct electrostatic force “Fe” as a result from the electric field. The force from the exchange of momentum with other charge carriers “Fp” showing toward the flow of charge carriers. In metallic conductors “Fp” is called “electron wind” or “Ion wind”.

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z The electromigration occurs when some of the momentum of a moving electron is transferred to a nearby-activated ion. This causes the ion to move from its original position. Over time this force knocks a significant number of atoms from their original positions. A break or gap can develop in the conducting material, preventing the flow of electricity. In the narrow interconnect conductors, such as those linking transistors and other components in integrated circuits, this is known as a void or internal failure open circuit (as Fig. 4 and Fig. 5)). The electromigration can also induce the atoms of a conductor to pile up and drift toward other nearby conductors, creating an unintended electrical connection known as a hillock failure or whisker failure (short circuit, as Fig. 6 and Fig. 7). Both of these situations can lead to a malfunction of the circuit.

Fig. 4 the atomics of aluminum were movement along grain boundary in electronic field. 【羅仁聰,半導體銅導線之電子及應力遷移可靠度探討,交通大學機械系, 2005】

Fig. 5 Electromigration induces the void and hillock.

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Fig. 6 SEM micrograph showing voids and hillocks. 【http://www.msm.cam.ac.uk/mkg/e_mig.htm】

Fig. 7 TEM micrographs of in-situ test showing voiding. 【http://www.msm.cam.ac.uk/mkg/e_mig.htm】

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1.1.4 Failure mechanisms

z Diffusion mechanisms:

¾ In a homogeneous crystalline structure, because the uniform lattice structure of the metal ions, there is hardly any momentum transfer between the conduction electrons and the metal ions. However, this symmetry does not exist at the grain boundaries and material interfaces, and here momentum is transferred much more vigorously. Since the metal ions in these regions are bonded more weakly than in a regular crystal lattice, once the electron wind has reached certain strength, atoms become separated from the grain boundaries and are transported in the direction of the current. This direction is also influenced by the grain boundary itself, because atoms tend to move along grain boundaries.

¾ Diffusion processes caused by electromigration can be divided into grain boundary diffusion, bulk diffusion and surface diffusion. In general, grain boundary diffusion is the major electromigration process in aluminum wires, whereas surface diffusion is dominant in copper interconnects.

z Grain boundary diffusion: (as Fig.8 and Fig.9)

¾ We have been studying a new class of defects called the grain boundary diffusion wedges in polycrystalline thin films. These diffusion wedges are formed by stress driven mass transport between the free surface of the film and the grain boundaries during the process of substrate-constrained grain boundary diffusion. The mathematical modeling involves solution to integro-differential equations representing a strong coupling between elasticity and diffusion. We show that the solution can be decomposed into diffusional eigenmodes reminiscent of crack-like opening displacement along the grain boundary that which leads to a singular stress field at the root of the grain boundary. We find that the theoretical analysis successfully explains the difference between the mechanical behaviors of passivated and unpassivated copper films during thermal cycling on a Si substrate.

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dislocations with Burgers vector parallel to the interface can be nucleated at the root of the grain boundary. This is a new dislocation mechanism in thin films that which contrasts to the well-known Mathews-Freund-Nix mechanism of threading dislocation propagation. Recent TEM experiments at the Max Planck Institute have shown that, while threading dislocations dominate in passivated metal films, parallel glide dislocations dominate in unpassivated copper films with thickness below 400nm. This is fully consistent with our theoretical predictions. z Bulk difference: (as Fig. 10)

¾ Bulk diffusion, the concentration of metal particle is zero momentum when the surface material have been coating. Base on difference concentration, the metal particle of the PR film diffuses to surface material.

z Surface diffusion: (as Fig. 11)

¾ Diffusion of adsorbates is an important elementary step of many surface processes such as epitaxial growth or catalytic reactions. Usually, surface diffusion is a thermally activated process that is initiated by heating the substrate. In some cases it would be desirable to enable diffusion at a lower temperature where competing surface reactions have not yet set in. For this and other purposes one would like to induce diffusion by electronic instead of thermal excitation similar to the well studied phenomena of desorption induced by (multiple) electronic transitions.

Fig. 8 we have a class of defects called the grain boundary diffusion wedges in polycrystalline thin films.

【H.GAO, L.ZHANG, W.D.NIX, C.V.THOMPSON and E.ARZT, Crack-Like Grain-Boundary Diffusion Wedges in Thin Metal Films, 22 May 1999】

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Fig. 9 The phenomenon usual occurs at which dislocation.

【H.GAO, L.ZHANG, W.D.NIX, C.V.THOMPSON and E.ARZT, Crack-Like Grain-Boundary Diffusion Wedges in Thin Metal Films, 22 May 1999】

Fig. 10 Bulk diffusion is the global macro-motion of the material within the deposited layer. 【楊金成、柯富祥、王美雅、王天戈, NDL 奈米通訊-第六卷第四期, 金屬雜質於 DUV 光阻中擴散及吸附行為之研究(I)】

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Fig. 11 Surface diffusion relates to the motion of metal boundaries. Diffusion of adsorbates is an important elementary step such as epitaxial growth or catalytic reactions. Usually, surface diffusion is a thermally activated process that is initiated by heating the substrate.

【http://math.berkeley.edu/~sethian/2006/Semiconductors/ieee_surface_diffusion.html】

z Thermal effects: (as Fig. 12 and Fig. 13)

¾ In an ideal conductor, the atoms are arranged in a perfect lattice structure, the electrons moving through it would experience no collisions and electromigration would not occur. In real conductors, the defects in the lattice structure and the random thermal vibration of the atoms about their positions causes electrons to collide with the atoms and scatter, that is the source of electrical resistance. Normally, the amount of momentum imparted by the relatively low-mass electrons is not enough to permanently displace the atoms. Anyway, in high-power situations (such as with the increasing current draw and decreasing wire sizes in the VLSI microprocessors); enough

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electrons bombard the atoms with enough force to become significant. Or, the process of electromigration accelerates by causing the atoms of the conductor to vibrate further from their ideal lattice positions, increasing the amount of electron scattering. High current density increases the number of electrons scattering against the atoms of the conductor, and hence the speed at which those atoms are displaced.

¾ In integrated circuits, electromigration does not occur in semiconductors directly, but in the metal interconnects deposited on them.

¾ Electromigration is exacerbated by high current densities and the Joule heating of the conductor, and it can lead to eventual failure of electrical components. Localized increase of current density is known as current crowding.

Fig. 12 Thermal induced electromigration effect.

【CSL, 2005, http://www.csl.mete.metu.edu.tr/Electromigration/emig.htm】

Fig. 13 Base on difference temperature, variation ratio of time vs. resistance for electromigration effect.

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z Balance of atom concentration:

¾ A governing equation which describes the atom concentration evolution throughout some interconnect segment, that is the mass balance (continuity) equation

Where is the atom concentration at the point with a

coordinates at the moment of time t, and J is the

total atomic flux at this location. The total atomic flux J is a combination of the fluxes caused by the difference atom migration forces. The major forces are induced by the electric current, and by the gradients of temperature, mechanical stress

and concentration. . Define the

fluxes mentioned above. . Here e is the

electron charge, eZ is the effective charge of the migrating atom, ρ the resistively of the conductor where atom migration ‘takes place’, is the local current density, k is Boltzmann’s constant, T is the absolute temperature. Is the time and position

dependent atom diffusivity. . It uses Q the

heat of thermal diffusion. Here Ω = 1 / N0 is

the atomic volume and N0 is initial atomic concentration, H = (σ11

+ σ22 + σ33) / 3 is the hydrostatic stress and σ11,σ22,σ33 are the

components of principal stress. .

¾ Assuming a vacancy mechanism for atom diffusion we can express D as a function of the hydrostatic stress

where EA is the effective activation

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concentration represents availability of empty lattice sites, which that might be occupied by a migrating atom.

1.1.5 Electromigration reliability of a wire (Black's

equation)

z At the end of the 1960s J. R. Black developed an empirical model to estimate the MTTF (mean time to failure) of a wire, taking electromigration into consideration (as Fig 1).

z It is clear that current density J and (less so) the temperature T is deciding factors in the design process that affect electromigration. z The temperature of the conductor appears in the exponent. It strongly

affects the MTTF of the interconnect lines. For an interconnect lines to remain reliable in rising temperatures, the maximum tolerable current density of the conductor must necessarily decrease.

1.1.6 Wire material

z It is known that pure copper used for Cu-metallization is more electromigration-robust than aluminum. Copper wires can withstand approximately five times more current density than aluminum wires while assuming similar reliability requirements. This is mainly due to the higher electromigration activation energy levels of copper caused by its superior electrical and thermal conductivity as well as its higher melting point (as Fig.14 and Fig. 15).

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Fig. 14 The table of aluminum element.

【Hong Xiao, Introduction to semiconductor Manufacturing Technology, 2001/05/27】

Fig. 15 The table of copper element.

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1.1.7 Summary

Electromigration is generally considered to the result of momentum transfer from the electrons, and it move in the applied electric field, to the ions which make up the lattice of the interconnect material.

Now semiconducting chips include a dense array of narrow, thin-film metallic conductors that serve to transport current between the difference devises on the chip. These metallic conductors are called interconnects.

As ICs become progressively more complex, the individual components must become increasingly more reliable if the reliability of the whole is to be acceptable. Anyway, due to continuing miniaturization of very large scale integrated (VLSI) circuits, thin-film metallic conductors or interconnects are subject to increasingly high current densities. Under these conditions, the electromigration can induce to the electrical failure of interconnects in relatively short times, reducing the circuit lifetime to an unacceptable level. It is therefore of great technological importance to understand and control electromigration failure in thin film interconnects.

In conventional metal wires like those used in house wiring, joule heating limits the allowable current to about 105 A.cm-2. At current densities higher than this the wire will heat up and fuse. Because they are deposited onto large efficient single crystal silicon heat sinks, thin film interconnects in ICs can sustain current densities up to 1012 A.cm-2 without immediate damage.

The electromigration causes several different kinds of failure in narrow interconnect. The most familiar are void failures along the length of the line and diffusive displacements at the terminals of the line that destroy electrical contact. The research has shown that both of these failure modes are strongly affected by the microstructure of the line and can, therefore be delayed or overcome by metallurgical changes that alter the microstructure (as Fig. 16).

Fig. 16 A cross-sectional view of the interconnect structure. 【http://www.csl.mete.metu.edu.tr/Electromigration/emig.htm】

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When electrons are conducted through a metal and they interact with imperfections in the lattice and scatter. Scattering occurs whenever an atom is out of place for any reason. Thermal energy produces scattering by causing atoms to vibrate. This is the source of resistance of metals. The higher the temperature, the more out of place the atom is the scattering and the greater the resistivity.

For the electromigration we need a lot of electrons, and also we need electron scattering electromigration does not occur in semiconductors microstructure, but it may in some semiconductor materials if they are so heavily doped that they exhibit metallic conduction.

1.2 Application

1.2.1 Line effect

z The electromigration is the momentum of atoms in response to “the electron wind”. The momentum transfer with the electrons pushing the atoms.

z It can induce to circuit failure through metal lines resistance increase or in the extreme the line opens (as Fig. 17).

Fig. 17 The electromigration induced the line effect. 【Image courtesy of T. Alford, Arizona State University】

z The momentum of atoms dominated by changes in mobility, e.g., at grain boundaries lattice (as Fig. 18).

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Fig. 18 The electromigration effect at grain boundary.

【Micrographs courtesy of K. Gadre and P. Nguyen, Arizona State University】

1.2.2 Passivating layers

(As Fig. 19) z The stress develops by migrating atoms.

z The passivating layers contain the stress, but cracks in such layers enhance electromigration effect.

Fig. 19 The electromigration effect at passivating layers. 【H. Murayama et al., Microelectron. Rel. 41, 1265 (2001)】

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1.2.3 Via issue

(as Fing.20 and Fig.21)

z Contact or via of electromigration can occur due to high current densities:

¾ Poor metal step coverage.

¾ Different materials, e.g., W plugs/Al lines.

¾ Al electromigration is not re-supplied by W (no voids for Al plugs). z Contact (Via) electromigration:

¾ The current continues to flow through the Ti/TiN and Al3Ti layers

when there is a void, but the resistance increases.

Fig. 20 The electromigration effect at via issue. 【Image courtesy of T. Alford, Arizona State University】

Fig. a If there are poor step coverage, it would has a void at the via. Fig. b If W plug don’t cover the TiN, it will has current crowding effect (high

current density at corner).

Fig. c The TiN layer likes a filter, and it can reduce current crowding effect.

Remark:

TiN:

¾ The resistivity of TiN is high than W and Al. ¾ It can reduce the contact resistance (Glue layer). ¾ Barrier layer.

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Fig. 21 The electromigration effect at via.

【TEM Micrographs Courtesy of T.S. Sriram and E. Piccioli, Compaq Computer Corporation】

z Via electromigration test structure: ¾ The force current through via.

¾ To change current direction allows upper and lower interfaces to be probed.

¾ Can combine with poly-Si resistance heater to change temperature.

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Fig. 22 via electromigration test structure. 【Image courtesy of T. Alford, Arizona State University】

1.2.4 EM in Solder Joints for flip-chip

z For solder joints used in IC chips, the atoms pile up at the anode, voids are generated at the cathode and back stress is induced during electromigration. The typical failure of a solder joint due to electromigration will occur at the cathode side. Due to the current crowding effect, voids form at the corner of the solder joint first. Then the voids extend and cause a failed circuit (as Fig. 23).

Fig. 23 The electromigration in solder joints for flip-chip.

【Y.C. Hu, Y.H. Lin, and C.R. Kao, Electromigration failure in flip chip solder joints due to rapid dissolution of copper, 2003/08/22】

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1.3 Conclusion

1.3.1 What is EM (electromigration)?

z The mass transport of a metal due to the momentum transfer between conducting electrons and diffusing metal atoms, this is exists current flows through metal wires.

z The conditions necessary for electromigration to be a significant problem continue to bear down on us with increasing speed and ferocity:

¾ High current densities. ¾ Long narrow wires. ¾ Logic hazards.

¾ High operating frequencies.

z The microstructure of the metallization induces to the atomic flow being non-uniform, and damage results in the form of voids or hillocks.

z The temperature and electron wind force are main factor for electromigration.

1.3.2 How to improve electromigration issue in future?

z The Cu has been used as a common alloy metal (typically between 0.5wt-% and 3wt-%) in aluminum interconnects to improve electromigration resistance and reliability.

z An optimized coarse-grained switching cell is designed to prevent electromigration, minimize voltage drop, and ensure fast wake-up time.

z Passivation openings should be designed to be as large as possible to reduce current density and improve electromigration life times. z To reduce the operation voltage and temperature.

z Raising adhesion strength between metal and metal alloy. z To form good step coverage at via.

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Chapter 2 Strain Technology

2.1 Abstract

The strained channel technology has been examined over twice decades because it enhances the carrier mobility contributing to the device drive current. Recently it has proposed to be integrated into integrated circuit industry for the CMOS higher performance. Although there are many methods to seek for higher device performance enhancement, but the strain technology is the promising candidate. In this chapter we will focus on the strained silicon channel on general (100) silicon wafer. We will discuss the fundamentals of strained silicon physic mechanism, the recent proposed technology and the future work.

2.2 Introduction

Silicon CMOS has emerged over the last 25 years as the predominant technology of the microelectronics industry. The concept of scaling has been consistently applied over many technology generations, resulting in consistent improvement in both device density and performance. Device dimensions are shrunk from the micrometer scale into the nanometer regime. Scaling of MOSFET is continuing for higher device performance, higher integrated circuit density, lower cost and etc. According to design rule, when the dimension of device is scaled down, the silicon dioxide thickness must be scaled down. Because of the short channel effects, the junction depth must be shallower, the substrate impurity concentration must be higher etc. Device performance can improve by inducing a larger charge density for a given gate voltage drive; enhancing the carrier transport; ensuring device scalability to achieve a shorter channel length; and reducing parasitic capacitances and parasitic resistances. Fig. 24 summarizes these opportunities/challenges and corresponding proposed technology options. These options can be classified into two categories: new materials and new device structures, which are usually related. As summarized in the table below, strained silicon could be one of the candidates to enhance the carrier transport. A high dielectric constant (κ) material is required to achieve low equivalent oxide thickness (EOT). When the requirements of device performance or reliability can’t be reached, we must

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change the material or structure. For example we replace silicon dioxide by the high-k material when the thickness of silicon dioxide is thinner than 2 nanometer. It suffers from carrier directly tunneling. Although using the high – k dielectric have a thicker physic thickness preventing from carrier directly tunneling, but it also leads to the degradation of mobility due to the uncertain or additional scattering mechanism. If we want to continue the Moore’s law, the use of high-k dielectric is necessary but we don’t want the mobility to degrade due to the introduction of high-k dielectric. Strained channel technology can overcome this disadvantage. In 2002 IEDM, Intel publishes the introduction of strain. Recently the International Technology Roadmap for semiconductor recognized that local strain has been integrated into current IC manufacturing and should be extendable to at least the 32 nm generation in Fig. 25 and Fig. 26.

Fig. 24 Potential solutions to improve device performance

【H. S. P. Wong, "Beyond the conventional transistor," IBM Journal of Research and Development, vol. 46, pp. 133-168, 2002.2】

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Fig. 25 ITRS 2005

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Fig. 26 ITRS 2006 update

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2.3 Physic mechanism

Now we will start to discuss the physic mechanism about strained silicon channel. In this section all we discuss is the conventional (100) silicon wafer. This is because the different growth orientation wafer has different responses of different kinds of strain due to lattice structure leading to different band structure (e.g. Fig. 27) then if we consider above, it will become more complex. Hereby in this section we just only simply discuss the conventional (100) silicon wafer.

Fig. 27 The different channel orientations on (a) (100) substrate, (b) (110) substrate, and (c) (111) substrate.

【Mobility-enhancement technologies , Chee Wee Liu, S. Maikap, and C.-Y. Yu , IEEE CIRCUITS & DEVICES MAGAZINE MAY/JUNE 2005】

In Fig. 28 we know when we shrink the device dimension; the applied voltage can’t be shrunk like it. Because of maintaining the sufficient drive current. As a resulting, the vertical field will increases with the dimension scaling down. The increasing vertical field degrades the mobility due to the different scattering mechanism. The reader is referred elsewhere for further discussion of mobility in Si inversion layers.

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Fig. 28 Mobility degrades with increasing the vertical field.

【S.Thompson etc. A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, 2002 IEDM pp61-64】

Therefore, for the higher drive current we must enhance the carrier mobility. Hereby there two approaches are used for enhancing mobility.

1. Strain technology. 2. Size effect.

Below we will discuss them respectively.

There are many methods used for the strained-channel by the naturally different lattice constant, partial process steps or device packaged. In this section we will introduce the substrate-based strain (biaxial train) and process-based strain (uniaxial strain).

z Biaxial strain:

Biaxial strain is also referred as global strain; it is substrate-based strain technology.

The strain exists in the surface parallel to substrate and vertical channel. The schematics Fig. 29 illustrate the structure.

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Fig. 29 Biaxial strain illustration. 【Applied Materials】

Under the biaxial strain, there is the same strain in the different position. Biaxial tensile stress could improve both N(electron mobility ) and P(hole mobility) -MOSFETs simultaneously. Although, this is true, it occurs only at low electric field and high stress Because of PMOS degrades at high electric field. (I.e. Fig. 30 ), and we will discuss this phenomena later.

Fig. 30 Biaxial strain illustration 【C.Hu, IEDM-2003】

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z Uniaxial strain:

Uniaxial strain is also referred as local strain. There is different strain in different position. And it is relative to device structure, channel length and channel width. The Fig. 30 illustrates the uniaxial strain, and points out what kinds of strain we need.

z Effect of strain on mobility

In Fig. 28 we know the mobility is limited by impurity scattering, phonon scattering and surface roughness scattering. Therefore the performance gain is possibly resulting from light effective mass, reduced inter-valley scattering and having a better heterointerface than that between silicon and silicon dioxide.

Considering the constant energy surface of silicon (100) conduction band in Fig. 31.

Fig. 31 Constant energy surface of conduction band illustration

【S.M.Sze, Semiconductor Device Development in the 1970s and1980s – A perspective, “Proc. IEEE, 69, 1121(1981).】

The electron transport characteristic is determined by the Six-fold valley and in the equilibrium the Six-fold valley is degenerate, then the occupancy possibility of electrons in the Six-fold valley is equal.

If we consider 2-D transport plane, the 2-fold valley is the optimum electronic system as schematically shown in Fig. 32.This is because the 2-fold valleys have the lower effective mass parallel to the Si/SiO2 interface which increase mobility and the higher effective mass perpendicular to the interface

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which increases inversion layer capacitance. Both of causations the occupancy of 2-fold valleys contribute to higher current drive of MOSFETs., Therefore if we increase the 2-fold valley occupancy , the electrons will transport by lighter effective mass then increase the electron mobility .The occupancy of 2-fold valleys is determined by the subband energy difference between the 2-fold valleys and 4-fold valleys. Hereby when we increase the splitting energy, the mobility will be enhanced due to increased 2-fold valleys occupancy, as schematically shown in Fig. 33. In Fig. 33 we know size effect and strain can increase the splitting energy. Fig. 34 shows when the thickness of Si channel on Insulator is between 3nm and 5nm, the mobility is increased due to the all electrons populate in 2-fold valleys-Except strain and size effect, the vertical electric field can also increase the splitting energy. And this is why the electron mobility enhancement is still maintained at high electric field! It is not only because reduced effective mass but also reduce intervalley scattering due to energy splitting. For a given strain, quantifying the effective mass reduction and comparing it to the enhanced Mobility reveals that mass reduction alone explains only part of the mobility enhancement Hence, electron scattering must also be reduced due to the conduction valleys splitting into two sets of energy levels, which lowers the rate of Inter-valley phonon scattering between the 2-fold valley and 4-fold valleys. Quantifying the improvement due to scattering has been difficult using acceptable scattering parameters, but reduced scattering is still believed to account for the rest of the mobility enhancement. Now we will discuss why the Gate voltage-induced quantum confinement (vertical field) also affects the splitting of 2-fold and 4-fold valleys. As schematically shown in Fig. 36, the vertical field affects the position of ground stares of 2-fold and 4-fold valleys is determined by the out-of-plane effective mass of 2-fold and 4-fold valley. As a resulting, the total splitting energy is equal to the strain-induced energy splitting plus the vertical field-induced energy splitting. According to this result, when the splitting energy is increased some scattering path will be suppressed. It is also contributed to the mobility enhancement.

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Fig. 32 Schematic subband structure of 2-D electron on (100) and the characteristics of two kinds of subbands ; the 2-fold and 4-fold valley.

【Subband structure engineering for performance enhancement of Si MOSFETs IEDM-97 pp219-222】

錯誤!

Fig. 33 Two device structure to enhance the electron occupancy of the 2-fold valleys by increasing the energy different.

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Fig. 34 Schematic diagrams of the band structure of SOI MOSFETs with different Si channel thickness

Fig. 35 Strain-induced band splitting

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Fig. 36 Strained MOSFET inversion layer

Up to now we only discuss the electron mobility enhancement under the biaxial tensile strain, the hole mobility enhancement is similar to electron, but there are something different. The electron mobility enhancement is resulting from the repopulation of electrons and reduced intervalley scattering. The hole mobility enhancement mainly is resulting from the reduced effective mass due to strain-induced valence band warping, As schematically shown in Fig. 37, hole constant-energy band surfaces for the top band obtained from six-band k • p calculations for common types of 1-GPa stresses: (a) unstressed (b) biaxial tension, (c) longitudinal compression on (001) wafer, and (d) longitudinal compression on (110) wafer (note significant differences in stress induced band warping altering the effective mass). By comparing the figure 11(a) and (b) we can understand why the holes mobility degrades at high field under biaxial tensile. This is because of the different out-of-plane effective mass between top band and second band (here the top band and second band differ from the light-hole band and heavy-hole band, because the light-hole band and heavy-hole band lose their meaning). This situation is opposite to the electron , because the splitting energy between top and second bands is decreased by vertical field increasing interband scattering , as schematically shown in Fig 38.

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Fig. 37 Lattice classify

【S.M.Sze, Semiconductor Device Development in the 1970s and1980s – A perspective, “Proc. IEEE, 69, 1121(1981).】

Fig. 38 Vertical field

【S.Thompson etc Uniaxial-process-induced strained-Si extending the CMOS roadmap ,E.D, vol.53,pp1010】

2.4 Recent technology

In this section we will introduce several proposed strain technologies. z Substrate-based strained-Si channel MOSFET:

The strained-Si channel is grown on relaxed SiGe layer /or graded SiGe layer, in which there are misfit dislocation formed due to the strain relaxation. So if we want to maintain strain in the Si channel, several conditions must be satisfied. The thickness of Si channel must be thinner than a critical thickness, which is a function of Ge concentration. The thickness of Si channel decreases with increasing the Ge concentration.

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The thermal budget must be lowered in order to prevent the strain from relaxing and prevent Ge atoms from diffusing to the interface between gate dielectric and Si-channel, as schematically shown in Fig. 39 because the present of Ge atoms cause additional challenges the thermal instability, parasitic hole channel at the Si/SiGe interface and lower thermal conductivity of SiGe etc. All of these are need to solve.

Fig. 39 Vertical field

【 S.Thompson etc Uniaxial-process-induced strained-Si extending the CMOS roadmap ,E.D, vol.53,pp1010】

z Process-based strained-Si channel MOSFET:

There are several method proposed to introduce the strain in Si channel, as schematically shown in Fig. 40. According to Fig. 30 we know that there are different strain requirement for PMOS and NMOS respectively. We utilize the stop-etch-capping-layer to introduce the tensile strain and compressive strain to NMOS and PMOS by depositing LPCVD nitride layer and PECVD nitride layer respectively in Fig. 40 (a). We also utilize the different thermal expansion coefficient between silicon and silicide to introduce the strain in Fig. 40 (b). STI is frequently used for lateral isolation in deep sub-micrometer technology in Fig. 40 (C).

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And the strained PMOS transistor features an epitaxially grown strained SiGe film embedded in the S/D regions using a selective epitaxial growth was reported by Intel in Fig. 40 (d).

Fig. 40 there is several methods proposed to introduce the strain in Si channel, as schematically.

【S.Thompson etc Uniaxial-process-induced strained-Si extending the CMOS roadmap ,E.D, vol.53,pp1010】

2.5 Conclusion

Whether biaxial or uniaxial technologies the Future work is to integrate strain technology with high-K dielectric, Ni silicide, SOI and other advanced technology for further improving devices performance.

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Chapter 3 Ni Fully Silicided (FUSI)

3.1 Abstract

A study of the implementation of Ni fully silicided (FUSI) gates to scaled devices is presented, addressing the issue of phase control at short gate lengths. A linewidth effect for Ni FUSI gates is found for non-optimized processes targeting NiSi, with formation of NiSi at long gate lengths and Ni-rich silicides at short gate lengths. This is attributed to Ni diffusion from areas surrounding the gates, resulting in a larger reacted Ni–Si ratio at short gate lengths. The linewidth dependence of the Ni FUSI phase results in an undesirable kink in the Vt roll-off characteristics, due to the difference in effective work function between the Ni silicide phases, which is particularly large for HfSiON dielectrics. An optimized 2-step RTP silicidation process is shown to eliminate this problem allowing the formation of NiSi gates uniformly at all gate lengths. The application and scalability of Ni-rich silicides to PMOS devices is also demonstrated, as well as a scheme for CMOS integration of dual WF phase controlled FUSI (NiSi for NMOS and Ni-rich silicides for PMOS), using an etch back step to reduce the poly-Si height on PMOS electrodes before full silicidation.

3.2 Introduction

Ni fully silicided (FUSI) gates are considered as candidates for metal gate electrode applications in next generation CMOS technologies. While initial work focused on NiSi FUSI gates and the modulation of its effective work function (WF) on SiO2 or SiON with dopants or alloying elements, recent work has shifted to consider other Ni silicide phases as well. On HfSiON dielectrics, there is a strong dependence of the effective WF on the Ni silicide phase, while a milder dependence on Ni silicide phase is observed for SiO2. The implications for device applications are twofold: on one hand it may be possible to take advantage of the phase dependent WF to tune transistor threshold voltages (Vt) for NMOS and PMOS devices by targeting different Ni silicide phases on NMOS and PMOS. On the other hand, the sensitivity of WF and Vt to silicide phase places a great concern on the ability to control the silicide phase in contact with the dielectric, uniformly at all gate lengths in all

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transistors of a microchip. This paper addresses the implementation of Ni FUSI gates to scaled devices and the phase control issues associated with it. A linewidth effect for FUSI gates is explained in terms of the Ni–Si reaction and phase formation, suggesting the formation of NiSi gates (NiSi in contact with the dielectric) at long gate lengths and Ni-rich FUSI gates (Ni-rich silicide in contact with the dielectric) at short gate lengths for non-optimized processes targeting NiSi. The scalability of NiSi FUSI gates is demonstrated, using an optimized 2-step RTP process that results in uniform formation of NiSi gates at all gate lengths studied. The application and scalability of Ni-rich silicides to PMOS devices is demonstrated. A CMOS integration scheme for dual WF phase controlled FUSI (NiSi for NMOS and Ni-rich silicides for PMOS) is also demonstrated.

Gate depletion and boron penetration are notorious process hazards for submicron CMOS processes with their very thin gate oxides, dual flavored poly-Si and low temperature budgets. The thermal budget must be sufficient to achieve adequate gate activation to avoid performance loss caused by gate depletion. On the other hand, the temperature budget must be reduced to limit short-channel effects, as well as to avoid PMOST threshold voltage reduction due to boron penetration. This paper shows that transistor matching degrades strongly when gate depletion or boron penetration occurs. This means that these effects must be interpreted as stochastic effects, associated with the grain size distribution in the poly-Si gate and how the dopant diffuses in the gate and through gate dielectric (Fig. 41).

Fig. 41. Schematic representation of poly-Si grain doping stages

a: after implant, b: fast diffusion along grain boundaries, c: almost fully doped, d: local boron penetration.

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3.3 NiSi salicide technology

3.3.1 Optimum silicidation temperature

Fig. 42 shows a typical salicide process for advanced CMOS. Because self-aligned silicidation is carried out after source drain formation, the silicidation temperature is desirable to be sufficiently low in order to keep ultra-shallowness of the junction for sub-100 nm technology node CMOS. Fig.44 shows a comparison of the silicidation temperature and other properties of various silicide materials. NiSi has the lowest silicidation temperature among the materials listed in the table and wide range of 350–750℃. Fig. 43 shows sheet resistance dependence on silicidation temperature for NiSi and TiSi2. In

the case of TiSi2 , the range is actually very small. The sheet resistance of

TiSi2 is high below 800℃, because content of C49 crystal (higher resistivity crystal) structure increases. Between 850℃ and 950℃, the sheet resistance goes through a minimum because the phase becomes C54 structure (lower resistivity crystal). Above 950 ℃ , it becomes again higher because agglomeration of the silicide film occurs. On the other hand, the sheet resistance of NiSi is stable and minimum between 450℃ and 750℃. Increase of the sheet resistance above 800C is due to phase transition from NiSi to NiSi2.

Thus, NiSi is the most suitable from the viewpoint of low process temperature for sub-100-nm technology node (or sub-50-nm gate length) CMOS. On the other hand, it should be noted that the process temperature after the salicide should not be higher than 750℃.

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Fig. 43. Dependence of sheet resistance on the silicidation temperature.

3.3.2 Silicon consumption during the silicidation

Silicon consumption during the silicidation is a very important factor for salicide. Here, silicon consumption is defined as the distance between the initial silicon interface and the bottom of the silicide, as shown in Fig. 45. The distance is normalized by the silicide thickness and shown in Fig. 44. Because NiSi is monosilicide, the silicon consumption is basically smaller than that of disilicide. From Fig. 44, it is found that the NiSi silicon consumption is about 20% smaller than that of CoSi2 case. This means that thickness of the silicide

can be increased about 20% and the sheet resistance can be reduced by that amount. This is beneficial for ultra-shallow junctions for sub-100-nm node CMOS.

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Fig. 45. Illustration explaining silicon consumption

3.3.3 Adverse narrow line effect

When the width of the TiSi2 line becomes narrow, significant increase in

the sheet resistance is observed, as shown in Fig. 46. This is called as ‘narrow line effect’. There are two reasons for the increase. In the width range between 2.0 and 0.2 mm, the silicide is composed of the mixture of C54 (low resistivity) and C49 (high resistivity) crystals as shown in the TEM photograph in Fig. 47. By the higher temperature of the second step anneal (for the TiSi2 case),

all the C49 films should transit to C54, but the transition becomes difficult when the width of the TiSi2 line becomes small. In addition, when the width of the

TiSi2 becomes less than 0.2 mm, the grain of silicide is disconnected in the line

by agglomeration phenomenon as shown in Fig. 48. The narrow line effects of TiSi2 can be suppressed by introducing additional process steps such as preamophization of the film by such as Mo or As shown in Fig. 46. While in the case of NiSi, the increase of the sheet resistance for the narrow line is not observed at all, because there is only NiSi crystal phase (low resistivity) in the wide process temperature range below 750℃. Even the sheet resistance of the narrow line becomes small in the NiSi case, as shown in Fig. 46. This is because the silicide film becomes thicker at the edge of the line, as shown in Fig. 49. In the case of Ni silicidation, Ni is the moving species for the reaction. The thicker silicide is formed at the edge since more Ni atoms are supplied there than the center to react with silicon as shown in Fig. 50. On the contrary, in the TiSi2 case, Ti is the moving species and, thus, more Ti atoms diffuse into

silicon at the edge, resulting in thinner films at the edge. In the case of Cobalt silicide, there are many phase, Co2 Si (high resistivity), CoSi (high resistivity)

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and CoSi2 (low resistivity), and the situation is complicated, but the adverse

narrow line effect was usually not observed. Similar phenomenon of thickness increase at the edge of line as NiSi was observed.

Fig.46. Dependence of sheet resistance on line width for various silicide materials.

Fig. 47. Relationship between crystal structure and TiSi2 line width.

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Fig.49. TEM images of cross-section of TiSi , NiSi, and CoSi lines

Fig.50. Schematic cross-section of moving species during silicidation at the edge of the poly Si gate electrode.

3.3.4 Bridging failure

Silicide formation on the gate sidewall can result in short-circuit failures between the gate and source / drain terminals. Such failure sometimes occurs in the case of TiSi2 , because moving species of the silicidation is Si as shown

in Fig. 44, and sometimes Si atoms diffuse into the Ti film on the sidewall portion and form a silicide salicide, as shown in Fig. 51a. On the other hand, Ni silicidation proceeds by the diffusion of Ni into silicon area as shown in the table, and thus, there is no possibility for the silicide later formed at the sidewall as shown in Fig. 51b. This is a great advantage of NiSi salicide. For the case of TiSi2 silicide, the bridging failure is suppressed by two-step silicidation. In the

first step, the Ti film deposited on MOSFETs was silicided at low temperature such as 600℃. In the low temperature, silicidation reaction was not very strong and the possibility of the aggressive diffusion of Si into the sidewall portion of the Ti metal is small. Then, non-silicided Ti film on the sidewall is etched off by acid solution. C49 TiSi is, then, converted to the C54 TiSi by the second anneal

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at 800℃. In the case of CoSi2, the possibility of the bridging can be avoided

also by the second step silicidation. In this case, Co film is converted to Co2 Si

in low temperature anneal, such as at 450℃. In the case of Co2 Si formation,

Co atom is the moving species and there is no possibility of the bridging. Then, after the removal of the non-reacted Co film, Co Si is converted to CoSi via CoSi phase at high temperature, such as at 750℃. In the case of one-step anneal, bridging of CoSi2 was observed, but it was confirmed that the bridging

is completely suppressed by the two-step silicidation. In the case of TiSi2,

however, the bridging possibility cannot be completely neglected because of the silicidation mechanism — or moving species. In the case of NiSi, there has been no bridging failure at all because of the silicidation mechanism.

Fig.51 Schematic cross-section of moving species during silicidation at the gate sidewall.

3.4 Experimental

Ni/poly-Si/dielectric stacks were deposited on (100) Si wafers, for varying film thickness, in the 30-170 nm and 60-100 nm ranges for Ni and Si films, respectively. Dielectric films used in this study included SiO2, SiON, HfSiON and HfSiON/SiO2 stacks of varying thickness with equivalent oxide thickness (EOT) in the 1–20 nm range. Samples were reacted by rapid thermal processing (RTP) to form silicide films at temperatures in the 280–850℃ range, typically for 30–60s. A wet etch used in self-aligned Ni silicide processes (diluted sulfuric-peroxide solution) was subsequently performed. In some samples a second RTP anneal step was performed after the selective

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etch. Samples were characterized by X-ray diffraction (XRD) using Cu Kα radiation and scanning electron microscopy (SEM). Patterned FUSI gate devices were also fabricated for electrical characterization, using a chemical-mechanical polishing (CMP) flow previously described or a conventional flow (the latter used only for fabrication of capacitors overlapping isolation). A CMP flow with a patterned poly-Si etch back step was used for fabrication of phase controlled dual WF Ni FUSI CMOS circuits.

3.5 Results and discussion

3.5.1 Ni silicide phase formation and effective work

function

Fig. 52 shows a schematic of the Ni-Si reaction path. After formation of Ni-rich silicides, two branches are possible in the reaction path, depending on whether Ni or Si is consumed first. NiSi2 nucleates at higher temperatures (if Si is still available). For Ni to Si atomic ratios between 1 and 2, Ni3Si2 can grow by reaction of NiSi with the Ni-rich silicides. On the other hand, if Si is fully consumed after initial growth of the Ni-rich silicides, NiSi cannot nucleate. Ni31Si12 and Ni3Si are observed in this case with increasing thermal budget, provided sufficient Ni is available. Fig. 53 shows the XRD spectra of FUSI samples for the different silicide phases, obtained by controlling the deposited Ni to Si thickness ratios and using sufficient thermal budgets to drive the reactions to completion. The effective WF of several Ni silicide phases on HfSiON and SiO2 are shown in Fig. 54. A significantly higher WF is seen for the

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Fig. 52 Schematic of Ni–Si reaction path.

Fig. 53 X-ray diffraction patterns (Cu Kα radiation) showing formation of the different Ni silicide phases controlled by the Ni to Si thickness ratio (tNi/tSi). Temperatures of RTP reaction are indicated.

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3.5.2 Scalability of Ni FUSI gate processes and device

implementation

On small patterned structures, control of the silicide phase is not easily achieved by simply controlling the deposited Ni to Si thickness ratio. Ni available from areas surrounding small devices can diffuse and react with poly-Si in the gate to increase the effective (reacted) Ni to Si ratio (Fig. 55). When targeting NiSi, for example, a deposited Ni to Si thickness ratio of 0.6 results for large structures in a stack with a NiSi layer in contact with the dielectric interface and a layer of Ni-rich silicide on top, when the thermal budget of the reaction is high enough to form NiSi. In Fig. 56, the sheet resistance as a function of linewidth is plotted for the reaction of 60 nm Ni with 100 nm poly Si at 520 ℃ (30s). The low sheet resistance for wide lines corresponds to the presence of NiSi. For narrow lines, however, an increase in sheet resistance is observed, which can be attributed to the formation of a thicker Ni-rich silicide (and little or no NiSi). In Fig. 56 it can be seen that there is good agreement between the sheet resistance at narrow linewidths obtained for 60 nm Ni using the 1-step RTP process (520℃) and the sheet resistance of a Ni-rich silicide obtained from 170 nm Ni. In order to control the silicide phase of FUSI gates at arrow linewidths, a 2-step RTP process is used (Fig. 56). The reacted Ni to Si ratio is controlled in this process by the thermal budget of the first RTP step (RTP1). After selective Ni etch, no additional Ni is available for the reaction during the RTP2 step (used to form NiSi) and the Ni to Si ratio remains unchanged. Fig. 57 illustrates the RTP1 process window for a 2-step RTP process targeting NiSi FUSI gates (NiSi at interface with the dielectric) and using 100nm poly-Si. Calculated using measured Ni silicidation kinetic data, for a reaction not limited by Ni availability (which can be the case at short gate lengths). At low RTP1 thermal budgets, insufficient Ni is reacted and the gates remain incompletely silicided after the RTP2 step. At high thermal budgets, a Ni-rich FUSI gate is formed. The process window for NiSi FUSI gates is seen to be narrow. Further more, since the morphology of the films cannot be expected to be ideal (layered structure with planar interfaces) and in order to account for process variability, additional margins need to be added, reducing the effective process window. Fig. 58 shows the Vt roll-off of Ni FUSI / HfSiON devices for several processes. This corresponds to the transition form NiSi FUSI gates at long gate lengths to Ni-rich FUSI gates at short gate lengths, in agreement with the corresponding WF values (see Fig. 54). This step is

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eliminated with the optimized 2-step RTP process, obtaining a smooth Vt roll-off curve indicating that the NiSi phase in contact with the dielectric is maintained at all gate lengths. Finally, a process targeting Ni-rich silicided gates is shown as well, achieving a smooth Vt roll-off. From these plots, and considering the requirement of low Vt values for scaled CMOS technologies, it is clear that NiSi is more attractive for NMOS devices on HfSiON, while Ni-rich silicides are more attractive for PMOS applications.

Fig. 55 The sheet resistance for a 1-step RTP FUSI process targeting NiSi increases on narrow gates (left). This is attributed to full silicidation of the narrow gates with a Ni-rich silicide, due to the diffusion of Ni from surrounding areas resulting in a higher effective Ni–Si ratio (right).

Fig. 56 Sheet resistance vs. linewidth for Ni FUSI gates fabricated by reaction of a Ni film with 100 nm poly-Si (left). A Ni-rich silicide is obtained for 170 nm Ni using a 1-step RTP process. A linewidth effect is observed for 60 nm Ni using a 1-step process. This is eliminated by using an optimized 2-step RTP process which results in a NiSi FUSI gate (right).

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Fig.57 (a) Schematic of the two-step RTP silicidation process. At short gate lengths, the reacted Ni-to-Si ratio increases with increasing RTP1 thermal budget due to Ni diffusion from areas surrounding the gate. The reacted Ni- to-Si ratio and resulting silicidephase can be controlled by the RTP1 thermal budget. The RTP2 step is used to drive the reaction to completion. (b)Reacted Ni-to-Si ratios extracted from RBS analysis as a function of RTP1 temperature for 100 nm poly-Si.

Fig. 58 RTP1 process window for a 2-step RTP process targeting NiSi gates (NiSi at interface with dielectric), calculated based on Ni silicidation kinetics. A Ni2Si/NiSi stack is assumed within the process window (solid lines), presence of Ni3Si2 would further reduce the process window (upper limit of RTP1 thermal budget, assuming a Ni3Si2/NiSi stack, shown in dashed lines). Margins should be added to account for interface roughness and non-uniformity of silicidation.

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3.5.3 Dual work function phase controlled Ni FUSI

CMOS integration scheme

For bulk Si CMOS technologies, in order to achieve tar- get Vt values, it is desirable to use a high effective WF (4.8-5.2 eV) material on PMOS devices and a low WF material (4.0-4.4 eV) on NMOS devices. As discussed in the previous section, the change in effective WF with Ni silicide phase on HfSiON opens an interesting opportunity for dual WF metal gate CMOS integration. Fig. 49 shows the integration scheme we propose to use, to achieve NiSi FUSI gates on NMOS devices and Ni-rich FUSI gates on PMOS devices. Following the CMP flow for fabrication of FUSI devices previously described, and before the FUSI module, a patterned poly-Si etch back step is used to reduce the poly-Si height on the PMOS devices. An optimized 2-step RTP FUSI process is then used to silicide simultaneously NMOS and PMOS gates. This approach was demonstrated, including the fabrication of working ring oscillators. Fig. 60 shows cross-sections of NMOS (NiSi FUSI gate) and PMOS (Ni-rich FUSI gate) transistors fabricated on the same wafer using this flow. Device characteristics obtained are shown in Figs. 61 (Vt roll-off).

Fig. 59 Schematic of dual WF phase controlled Ni FUSI CMOS integration scheme using poly-Si etch-back on PMOS.

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Fig. 60 SEM cross-sections of NMOS NiSi FUSI gate (left) and PMOS Ni-rich FUSI gate (right) devices fabricated on the same wafer using the dual WF CMOS integration scheme shown in Fig. 59

Fig. 61 Linear Vt roll-off for devices built using the CMOS dual WF phase controlled FUSI flow shown in Fig. 59.

3.6 Conclusions

The scalability issues of Ni FUSI gates were discussed, showing phase control at short gate lengths to be a key concern. A linewidth effect was found for processes targeting NiSi FUSI gates with non-optimal thermal reaction, which resulted in formation of Ni-rich FUSI gates at short gate lengths. An optimized 2-step RTP process was shown to solve this issue achieving good scalability for NiSi FUSI gates. Scalable processes for Ni-rich FUSI gates were also demonstrated. A dual WF Ni FUSI / HfSiON CMOS integration scheme, using a poly-Si etch back step and simultaneous silicidation of NMOS and PMOS was demonstrated and used to fabricate circuits with NiSi FUSI gates on NMOS devices and Ni-rich FUSI gates on PMOS devices.

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Chapter 4 Electroless Plating

4.1 Introduction

Along with semiconductor industry in during several years rapid development, process technology unceasingly progresses for CMOS devices to keep up with the downscaling and into ULSI nodes. The metallization process has become an extremely important essential step. In the semiconductor technology node, the metal thin film function mainly is Ohmic Contact, Schottky Barrier Contact, Gate electrode and interconnects. However, silicide in the semiconductor circuits function mainly is Ohmic Contact or Interconnect for reduce contact resistivity to improved RC delay.

This research in choice of material, because silicide of nickel has low resistance and few silicon consumption, the NiSi is the main material. On the other hand, for the semiconductor manufacture process, deposition of NiSi by chemical displacement and electroless plating onto a silicon layer can form ultra-shallow junction different to CVD (Chemical vapor deposition) and ITM (implant through metal) are obtained simultaneously, therefore improve short-channel effects (SCEs), achieves the device downscaling goal.

For a CMOS technology to keep up with the downscaling, in order to reduce short-channel effects (SCEs) and RC delay. Fig. 62 is show structure of MOSFET. Fig. 63 is show materials effect of MOSFET downscaling. To understand the shallow junction and low parasitic source / drain (S / D) resistance are required. Self-aligned silicide is wildly used in CMOS process manufacturing to reduce sheet resistance of source and drain.

Fig. 62 Structure of MOSFET

【 Selective Deposition NiP as Diffusion Source to Form n+p Junction and NiSi Simultaneously】

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Fig. 63 Materials effect of MOSFET downscaling

【 Selective Deposition NiP as Diffusion Source to Form n+p Junction and NiSi Simultaneously】

Al was used reduce resistance of gate and metal junction. Because of in integrated circuit temperature regular meeting to achieve 450-500℃, reaches as high as 0.5-1at.% in this temperature range silicon in the Al solubility, and in the aluminum thin film the rapid proliferation causes in the contact surface production hole. This was called aluminum spiking question. Fig. 64 is show Si dissolution in the aluminum. Aluminum spikes could punctuate through the doped junction, short source / drain with the substrate, and damage the devices. Fig. 65 is shows spike effect. Because of Al spike effect and process temperature limit. Therefore from 1966, he metal silicide technology is applied reduces to the Ohmic contact and the Schottky contact resistance. In 1979, the high conductive metal silicide is used to form polyside structure with the poly silicon. In 1981, Self-aligned silicide (salicide) technology was extends form silicon the contact window to the gate polycide and source/drain diffusion area. Fig. 66 is show generalization structure of salicide and Fig. 67 is shows manufacture step of salicide.

先進的金氧半場效發射電晶體技術

報告題名：

Advanced MOSFET Technologies

中文摘要

關鍵字：Electromigration、Strain、FUSI、Electroless plating、

Flash、Nanowires.

English Abstract

Key Word:

Electromigration、Strain、FUSI、Electroless plating、

Contents

nanowires 83

Chapter 1 Electromigration

1.1 Introduction

1.1.1 History

1.1.2 Practical implications of EM

1.1.3 Fundamentals

1.1.4 Failure mechanisms

1.1.5 Electromigration reliability of a wire (Black's

equation)

1.1.6 Wire material

1.1.7 Summary

1.2 Application

1.2.1 Line effect

1.2.2 Passivating layers

1.2.3 Via issue

Remark:

1.2.4 EM in Solder Joints for flip-chip

1.3 Conclusion

1.3.1 What is EM (electromigration)?

1.3.2 How to improve electromigration issue in future?

Chapter 2 Strain Technology

2.1 Abstract

2.2 Introduction

2.3 Physic mechanism

2.4 Recent technology

2.5 Conclusion

Chapter 3 Ni Fully Silicided (FUSI)

3.1 Abstract

3.2 Introduction

3.3 NiSi salicide technology

3.3.1 Optimum silicidation temperature

3.3.2 Silicon consumption during the silicidation

3.3.3 Adverse narrow line effect

3.3.4 Bridging failure

3.4 Experimental

3.5 Results and discussion

3.5.1 Ni silicide phase formation and effective work

function

3.5.2 Scalability of Ni FUSI gate processes and device

implementation

3.5.3 Dual work function phase controlled Ni FUSI

CMOS integration scheme

3.6 Conclusions

Chapter 4 Electroless Plating

4.1 Introduction