Chapter 2 Preparation methods of HfO 2
2.3 DC Magnetron Sputtering
The usual HfO2 film with DC magnetron sputtering method is reactively sputtered from an Hf target in an Ar + O2 ambient onto Si substrate. The advantages of the DC magnetron sputtering are simple and cheap. In addition, the HfO2 film prepared by CVD system easily contains organic impurities and/or oxygen vacancies inside. This will cause leakage current through Frenkel-Pool effect or trap assisted tunneling [8]. Less contaminants are produced by the process of the sputtering because there is no other unnecessary chemicals. However, the uniformity of the DC sputtering is worse than that of the ALCVD and the MOCVD in 12 inch diameter Si wafer. Further, sputtering in an O2 ambient easily produces SiO2 interfacial layer.
Therefore, we decide to sputter Hf in an Ar ambient only. After pure Hafnium has been deposited on Si substrate, we put the wafer into furnace system with O2 ambient at some low temperature for oxidation. At some low temperature (＜500℃), Si will not react with O2 to form the SiO2. Then, the HfO2 film is prepared without SiO2
interfacial layer.
2.4 References
[1] R. J. Carter, E. Cartier, M. Caymax, S. De Gendt, R. Degraeve, G. Groeseneken,
10
M.Heyns, T. Kauerauf, A. Kerber, S. Kubicek, G. Lujan, L. Pantisano, W. Tsai, E.
Young, “Electrical Characterisation of High-K Materials Prepared by Atomic Layer CVD”, IWGI 2001, Tokyo.
[2] Benjamin Chih-ming Lai, Nan-hui Kung, and Joseph Ya-min Lee, “A study on the capacitance--voltage characteristics of metal-Ta2O5-silicon capacitors for very large scale integration metal-oxide-semiconductor gate oxide applications”, J.
Appl. Phys. 85, 4087 1999.
[3] Wai Shing Lau, Merinnage Tamara Chandima Perera, Premila Babu, Aik Keong Ow, Taejoon Han, Nathan P. Sandler, Chih Hang Tung, Tan Tsu Sheng and Paul K.
Chu, “The Superiority of N2O Plasma Annealing over O2 Plasma Annealing for Amorphous Tantalum Pentoxide (Ta2O5) Films”, Jpn. J. Appl. Phys. Vol.37 pp.L435-L437 1998.
[4] Y. Chuo, D. Y. Shu, L. S. Lee, W. Y. Hsieh, M. –J. Tsai, A. Wang, S. B. Hung, P. J.
Tzeng, Y. W. Chou, “In-Line Inspection on Thickness of Sputtered HfO2 and Hf Metal Ultra-Thin Films by Spectroscopic Ellipsometry”, 2004 IEEE.
[5] Takeshi Yamaguchi, Hideki Satake, Noburu Fukushima, “Band Diagram and Carrier Conduction Mechanisms in ZrO2 MIS Structures”, IEEE Transactions on Electron Devices, Vol. 51, No. 5 May 2004.
[6] Suvi Haukka, Marko Tuominen and Ernst Granneman, Semicon Europa/Semieducation, April 5th,2000.
[7] International SEMATECH Confidential and Supplier Sensitive, “Status of High-k Gate Dielectric Development and the Demonstration of High-k Devices with Equivalent Oxide Thickness (EOT) of <= 1.0 nm”, 2002.
[8] Wai Shing Lau, Thiam Siew Tan, Nathan P. Sandler, Barry S. Page,
“Characterization of Defect States Responsible for Leakage Current in Tantalum Pentoxide Films for Very-High-Density Dynamic Random Access Memory (DRAM) Applications”, Jpn. J. Appl. Phys., Vol.34, pp.757-761, 1995.
Fig. 2-1 ALCVD growth mechanism of AL2O3 and HfO2
.
(International SEMATECH Confidential and Supplier Sensitive, 2002)
Fig. 2-2 Scaling limits of different ALCVD Hf-Based high-k Materials.
(International SEMATECH Confidential and Supplier Sensitive, 2002)
Fig. 2-3 Scaling lim its of MOCVD HfO
2and Zr O
2. (International SEMATECH Confiden tial and Supplier Sensitive, 2002)
11
Chapter 3
Experiments of Al/HfO 2 /Si MIS Capacitor
3.1 MIS Capacitors Fabrication Process
In this thesis, isolated Al gated capacitors were fabricated to study ultra thin HfO2 gate dielectrics. Figure 3-1 shows the fabrication flow of this experiment. The starting wafer was four inch (100) orientated n-type wafer with phosphorus doped or p-type wafer with boron doped. It was one side polished and its resistivity was 5~10 ohm-cm. After standard initial RCA cleaning, wafers were put into furnace and grew a 5000Å thermal oxide layer at 1050℃. The oxide thickness was measured by a well-calibrated ellipsometer at a wavelength of 632.8 nm with the refractive index set at 1.462.
Mask #1 defined the active regions and initial clean was performed again. Then, continued with DC magnetron sputtering hafnium on the wafers and oxidized them in furnace system. The thickness of as-deposit hafnium thin films was 20 Å which was read by the sensor inside the sputtering system. During sputtering, chamber pressure was maintained around 7.6×10-3 torr and the flow rate of Ar was 24 standard cubic centimeters per minute (sccm). The oxidation conditions were 200℃, 300℃, 400℃
and 500℃ respectively for 15 or 30 minutes, as shown in Table 3-1, with oxygen flow rate 5000 sccm. After oxidation process, pure aluminum was thermally evaporated on the top side of wafers.
Mask #2 defined the top electrode. Then, we used wet etching to etch undefined Al and HfO2 films. After patterning, backside native oxide was stripped with diluted HF solution, and Al was deposited as bottom electrode. Finally, samples were sintered in pure N2 at 400℃ in furnace for 30min to recover the process induced damages. The detailed fabrication process flow was listed as follows.
1. Initial RCA cleaning.
2. Thermally grow 5000Å wet oxide at 1050℃.
3. Mask #1：define active region and then RCA clean again.
4. DC magnetron sputtering hafnium 20 Å.
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5. Thermal oxidize hafnium in furnace in an O2 ambient at 200℃, 300℃, 400℃
and 500℃ respectively for 15 or 30 minutes.
5-1. RTA treatment at 850℃ for 30 seconds.
6. Thermally evaporate 5000 Å aluminum as top electrode.
7. Mask #2：define top electrode and then wet etch undefined Al and HfO2 films.
8. Strip backside native oxide and coat 5000 Å aluminum as bottom electrode.
9. Al sintering in pure N2 at 400℃ in furnace for 30min.
After the Al/HfO2/Si MIS capacitors were prepared, we used semiconductor parameter analyzer (HP4156A) and C-V measurement (HP4284) to analysis electric characteristics (i.e. I-V, C-V, EOT, leakage current density etc.). Then we tested their reliability, including stress induced leakage current (SILC), constant current stress (CCS), constant voltage stress (CVS), Hysteresis effect.
3.2 Sputtering system
Four inch high purity hafnium target was used to deposit thin film by DC magnetron sputtering system. The sputtering conditions were as follows. In the DC sputtering process chamber, the wafers were mounted on a face-down holder which can rotate during deposition to increase film uniformity. The system was pumped down to 2×10-6 torr first. This process made the chamber clean enough and thus decreased the impurity of the deposited hafnium film. Then the deposition pressure was controlled at 7.6×10-3 torr. Before started to deposit hafnium, the surface of the hafnium target was treated by low power pre-sputtering cleaning for ten minutes. The inert gas source was argon (Ar) and its flow rate was 24 sccm. It has heavy atomic weight and could be served as a heavy iron to knock down the hafnium atoms on the target surface. Therefore, the hafnium atoms could be sputtered onto the wafers. The thickness of the deposited hafnium was read by the sensor inside the sputtering system. Then, the oxidation process of hafnium was performed by furnace system.
The DC magnetron sputtering power was set at 120 W and the corresponding deposition rate was 0.3 Å/s. The thickness of hafnium films was 20 Å.
3.3 Furnace system
13
After hafnium had been deposited on silicon, we need an oxidation process to make it become hafnium dioxide. These Si wafers deposited with hafnium films were immediately loaded into furnace tube just as the sputtering process was finished. To start with, the tube temperature was set at 200 ℃ , 300 ℃ , 400 ℃ and 500 ℃ respectively as different process conditions and sufficient N2 gas was purging continuously. After the tube temperature was stable in five minutes letter, N2 gas was closed and O2 gas was introduced. The oxygen gas flow rate was set at 5000 (sccm).
We provided sufficient oxygen gas and proper time to oxidize these films.
3.4 Rapid Thermal Annealing system
METAL RTA-AG 610 was a single-wafer lamp-heated and computer-controlled rapid thermal processing (RTP) system. Water and compressed dry air (CDA) cooling system were used to cool down the quartz chamber. High intensity visible radiation heating and cold-heating chamber walls allow fast wafer heating and cooling rate. The 12 tungsten-halogen lamps were distinguished into five groups, and the relative percentage of lamp intensity can be adjusted individually for each group to achieve uniform temperature distribution. Temperature was obtained from pyrometer and precise controlled by computer. Two gas lines were used in the system which can be switched between Ar and N2.
Before RTA process started, one minute N2 gas purge was performed to minimize the water vapor introduced during wafer loading and also swept unwanted particles induced during process. A fast heating rate of 60℃/s was chosen in this work. When anneal was complete, chamber temperature was quickly cooled down from 850℃ to 500℃ by N2 purge 30 seconds. Then, the chamber was slowly cooled down to 280℃
without N2 purge to avoid creaking of films. After five minutes later, wafers can be taken out from the chamber. By two-steps-cooling method, films’ creaks can be avoided
Wafer
Number Wafer Type Oxidation Temperature ( ℃ )
Oxidation Time (minute)
1 200 15
2
p-type
300 15
3 200 15
4
n-type
300 15
5 15 6
400
30
7 15 8
p-type
500
30
9 15 10
400
30
11 15 12
n-type
500
30
Table 3-1 The oxidation temperature and time of HfO2 films.
1. Initial RCA clean.
2. Thermally grow 5000 Å wet oxide.
3. Mask #1：define active region and RCA clean.
4. Sputtering 20 Å hafnium.
5. Thermal oxidize hafnium films in furnace.
(200℃, 300℃, 400℃ and 500℃ / 15 or 30 minutes)
5-1. RTA treatment at 850℃ for 30 seconds.
6. Thermal coating 5000 Å aluminum on top.
7. Mask #2：pattern top electrode and etch Al and HfO2.
8. Strip native oxide on backside and coat bottom Al electrode.
9. Al sintering (N2_400℃_30min).
Figure 3-1 Fabrication flow chart of ultra thin HfO2 MIS capacitor.
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Chapter 4
Electrical Characteristics of Al/HfO 2 /Si MIS Capacitors
4.1 Capacitance-Voltage Characteristics
In our experiments, we used HP2484A LCR meter to measure the 1MHz high frequency C-V characteristics of our MIS capacitors. We swept the gate bias from inversion region to accumulation region. There were three different die areas (i.e.
6.25×10-6, 2.5×10-5 and 1×10-4 cm2) for discussing area depend effects. In addition, the oxidation temperature was ranging from 200℃ to 500 with 15 or 30 minutes.℃ Table 4-1 shows the measurement results of HfO2 capacitors under different process conditions with 6.25×10-6 cm2 die area. Unfortunately, while the oxidation temperature is lower than 400 , we only℃ get the effective C-V characteristics of n-type HfO2 capacitors under 300 15minutes oxidation condition℃ . The failure in quasi-static C-V measurement is due to the leakage current higher than the displacement current for most gate bias. Under such a low oxidation temperature, hafnium atoms may react with oxygen atoms to form HfO2 but with very weak chemical bonding. We find that this weakly bonding type of HfO2 layer couldn’t bear much gate bias but it has an effective accumulation capacitance. It seems that n-type HfO2 capacitors could have stronger chemical bonding than p-type HfO2 capacitors under low oxidation temperature. Table 4-2 and 4-3 show the measurement results of HfO2 capacitors with 2.5×10-5 cm2 and 1×10-4 cm2 die area respectively.
Fig. 4-1 shows the 1MHz high frequency C-V characteristics of p-type HfO2
capacitors with different die area under 400℃-15 minutes oxidation condition. We could see that the capacitors with smaller die area have larger accumulation capacitance, but the size of die area doesn’t influence the flat band voltage (VFB).
Besides, the slopes of these three C-V curves are almost the same. Fig. 4-2 shows the 1MHz high frequency C-V characteristics of p-type HfO2 capacitors with 6.25×10-6 cm2 die area under different oxidation conditions. Under 400℃-15 minutes oxidation condition, the capacitor has the largest accumulation capacitance and the smallest
V
∣ FB∣. The higher oxidation temperature and the longer oxidation time make the more negative flat band voltage shift. There exists several types of charges, including
15
interface trapped charge (Qit), fixed oxide charge (Qf), oxide trapped charge (Qot) and mobile ion (Qm), in the dielectric layer and at the substrate interface. To simplify, we call all these charges as interface effective positive charge Qi (C/cm2). So, the flat band voltage can be expressed as follows：
( )
The influence of Qi is to introduce an equivalent negative charge within semiconductor. Because the work function difference and interface effective positive charge will both make the band near semiconductor surface bending downward, a negative voltage must be applied on metal to reach flat-band condition [1]. Thus, the more negative VFB means more positive charges were produced at the interface during oxidation process. Fig. 4-3 shows C-V characteristics of three different gate dielectrics, including SiO2, (SiO2)0.5(Si3N4)0.5 and Si3N4 [2]. ∆VFB for nitride and oxynitride devices with respect to oxide device are 0.15 and 0.04 V. Interfacial fixed charge is 7.5×1011/cm2 for nitride and 2×1011/cm2 for oxynitride. The fixed charge of the nitride film shows greater than oxynitride gate stack. This is due to increased bond-strain in the bulk and at internal dielectric interface. Increased bond-strain results in more “border traps”. Comparing fig. 4-2 to fig. 4-3, ∆VFB for HfO2 under 400℃-15 minutes oxidation condition with respect to SiO2 device is about 0.2 V. This is because of more stress in the HfO2 device, which generates more intrinsic defects, including bulk traps in film, border traps and interfacial traps. In addition, oxidation temperature affects ∆VFB seriously. The higher oxidation temperature would cause more stress in the device and generate more intrinsic defects. It may be caused by our improper cool down process. These defects directly influence the quality of the insulator layer and the substrate interface (i.e. gate leakage, carrier mobility, reliability etc.). In addition, 400 oxidation temperature makes the slope of C℃ -V curve apparently stepper than 500 oxidation tempe℃ rature. It seems oxidation time doesn’t affect the slope of C-V curve. Consequently, for p-type HfO2 capacitor, under 400℃-15 minutes oxidation condition could obtain the best C-V characteristics.
4.2 Equivalent Oxide Thickness (EOT)
From C-V characteristics, like fig. 4-1 and fig.4-2, equivalent oxide thickness (EOT) could be obtained by the following formula：
tox = εr‧ε0‧A / C
Where εr is the dielectric constant of SiO2 (εr = 3.9), ε0 is the permittivity in vacuum
16
(ε0 = 8.85×10-14 F/cm). A is the area of the capacitors (A = 6.25×10-6, 2.5×10-5 and 1×10-4 cm2) and C is the accumulation capacitance measured at V∣ G - Vt∣= 1 V at 1 MHz. According to this formula, we could calculate all the electrical EOT of our capacitors, which listed in Table 4-1, 4-2 and 4-3. We see that n-type HfO2 capacitors with 6.25×10-6 cm2 die area under 300℃-15 minutes oxidation condition have the smallest EOT of 9.2 Å. For p-type HfO2 capacitors, with 6.25×10-6 cm2 die area under 400℃-15 minutes oxidation condition have the smallest EOT of 17.3 Å. In addition, under the same oxidation condition, we find that p-type capacitors have smaller EOT than n-type capacitors. It might be attributed to that the diffusion rate of hafnium and oxygen atoms in n-type substrate is larger than in p-type substrate.
Fig. 4-4 shows EOT of p-type HfO2 capacitors with different die areas. Under every different oxidation conditions, the devices with smaller die area have the smaller EOT. It is a very strange phenomenon. Devices with different die area on the same wafer under the same oxidation condition should have the same EOT. It is probably due to that the smaller die area attracts the larger ratio of edge charges around the device and thus has larger capacitance measured by HP4284, as shown in fig 4-1. If we eliminate the edge charge effect, the devices with different die area on the same wafer have the same EOT in fact. Fig. 4-5 shows EOT of p-type and n-type HfO2 capacitors with 6.25×10-6 cm2 die area under different oxidation conditions.
Higher oxidation temperature causes larger EOT of the device. Besides, longer oxidation time also slightly increase EOT of the device. The increase of EOT might result from the increase of interfacial layer which grown in the oxidation process. As shown in fig 4-6, during oxidation process, hafnium and oxygen atoms would diffuse to substrate and form an HfSiO interfacial layer. We will discuss the possible reasons of such EOT tendency by analyzing current-voltage characteristics.
4.3 Current-Voltage Characteristics
4.3.1 Leakage Current
Fig. 4-7 shows the J-V characteristics of p-type HfO2 capacitors with different die areas (6.25×10-6, 2.5×10-5 and 1×10-4 cm2) under 400℃-15 minutes oxidation condition from 0 V to -1 V. We observed that the gate leakage current density becomes only a little larger while die area decreases. From table 4-1, 4-2 and 4-3, EOT of these three devices are 17.3 Å, 21.0 Å and 22.3 Å respectively. Fig. 4-8 shows J-V characteristics of p-type HfO2 capacitors with 6.25×10-6 cm2 die area under different oxidation conditions (400℃-15 minutes, 400℃-30 minutes, 500℃-15
17
minutes and 500℃-30 minutes) from 0 V to -1 V. The EOT of these four devices are 17.3 Å, 17.4 Å, 23.8 Å and 23.9 Å respectively. Apparently, the device under higher oxidation temperature and longer oxidation time has lower gate leakage current. In fig.
4-7, 5 Å increase of EOT (from 17.3 Å to 22.3 Å) only reduces a little gate leakage at VG = -1 V. But in fig. 4-8, 6.5 Å increase of EOT (from 17.3 to 23.8 Å) reduces gate leakage even more than 2 orders at VG = -1 V. Thus, from fig. 4-7, three similar magnitudes of gate leakage reveal that the thickness of devices with three different die area on the same wafer might be the same. As shown in fig. 4-8, the main reason of such a large repression of gate leakage between 400℃-15 minutes and 500℃-15 minutes oxidation conditions is the increase of thickness. Higher oxidation temperature could also make HfO2 film have stronger chemical bonding to effectively resist gate leakage. Besides, the devices under 500℃-15 minutes (EOT = 23.8) and 500℃-30 minutes (EOT = 23.9) oxidation condition have almost the same thickness but have about an order difference of gate leakage at VG = -1 V. Thus, the longer oxidation time mainly increases the intensity of chemical bonding.
Fig. 4-9 shows measured and simulated J-V characteristics of NMOSFET with SiO2 gate insulator. Gate leakage current density of 20 Å SiO2 gate insulator at VG = 1 V is about 3×10-2 A/cm2. From fig.4-9, however, gate leakage current density of the HfO2 capacitor with EOT = 17.3 Å at VG = -1 V is only about 3×10-4 A/cm2. Even thinner EOT of HfO2 capacitor but has less gate leakage than SiO2 device about 2 orders. Consequently, replacing SiO2 with HfO2 for gate insulator could effectively reduce gate leakage.
Then, we make plots of gate leakage versus EOT for further discussing. As shown in fig. 4-10, we could obviously find that, whether for n-type or for p-type HfO2 capacitors, gate leakage at Vg = 1 V of different die areas are almost the ∣ ∣ same, even if their EOT are not the same. With the increase of EOT, however, the gate leakage doesn’t decrease. Consequently, we think the EOT of devices with different die areas on the same wafer should be the same in fact. From fig. 4-11, we observe that, whether for n-type or for p-type HfO2 capacitors, while the oxidation temperature rises, the EOT becomes larger and the leakage becomes less. Higher oxidation temperature makes the HfSiO interfacial layer become thicker, as shown in fig. 4-6. The thicker interfacial layer causes the larger EOT of HfO2 gate insulator.
Higher oxidation temperature also makes the chemical bonding stronger. Thicker physical thickness and stronger chemical bonding both contribute to the decrease of gate leakage current. Longer oxidation time slightly increases EOT and decreases gate leakage current. In addition, another interesting phenomenon is that under the same
18
oxidation condition, n-type HfO2 capacitor has larger EOT but larger gate leakage current than p-type HfO2 capacitor. The larger EOT might result from the larger diffusion rate of hafnium in company with oxygen atoms in n-type substrate than in p-type substrate. Generally, the device with larger EOT has less leakage current. Thus, we think the HfO2 layer grown on p-type substrate has better quality of resisting gate leakage than on n-type substrate.
Fig.4-12 shows J-V characteristics of n-type and p-type HfO2 capacitors with 6.25×10-6 cm2 die area from -1 V to +1 V. For p-type, the leakage current under positive gate bias is much lower than negative case by 3 orders. For n-type, the leakage current under negative gate bias is lower than positive case by 1 order. The reverse leakage is thought to be dominated by surface leakage [3]. The surface generation current has been reported to be linearly correlated to the interface state density [4]. These interface states are caused by the dangling bonds at the Si/SiO2
interface [5][6]. This component is often masked by surface leakage, especially at low temperatures [7][8]. This is illustrated in fig. 4-13.
Fig. 4-14 shows J-V characteristics of n-type HfO2 capacitors with different die areas under 400℃-30 minutes oxidation condition from 0 V to +10 V. In this figure, we could see the devices with 6.25×10-6, 2.5×10-5 and 1×10-4 cm2 die area, generate breakdown at VG = 3.85 V, 3.50 V and 3.10 V respectively. The device with smallest die area has the biggest breakdown voltage (VBD), which means the best quality of resisting leakage current. We think more ratio of leakage current could pass through the gate insulator from edge side between HfO2 layer and isolation oxide in the device
Fig. 4-14 shows J-V characteristics of n-type HfO2 capacitors with different die areas under 400℃-30 minutes oxidation condition from 0 V to +10 V. In this figure, we could see the devices with 6.25×10-6, 2.5×10-5 and 1×10-4 cm2 die area, generate breakdown at VG = 3.85 V, 3.50 V and 3.10 V respectively. The device with smallest die area has the biggest breakdown voltage (VBD), which means the best quality of resisting leakage current. We think more ratio of leakage current could pass through the gate insulator from edge side between HfO2 layer and isolation oxide in the device