Rapid Thermal Annealing system

METAL RTA-AG 610 was a single-wafer lamp-heated and computer-controlled rapid thermal processing (RTP) system. Water and compressed dry air (CDA) cooling system were used to cool down the quartz chamber. High intensity visible radiation heating and cold-heating chamber walls allow fast wafer heating and cooling rate. The 12 tungsten-halogen lamps were distinguished into five groups, and the relative percentage of lamp intensity can be adjusted individually for each group to achieve uniform temperature distribution. Temperature was obtained from pyrometer and precise controlled by computer. Two gas lines were used in the system which can be switched between Ar and N2.

Before RTA process started, one minute N2 gas purge was performed to minimize the water vapor introduced during wafer loading and also swept unwanted particles induced during process. A fast heating rate of 60℃/s was chosen in this work. When anneal was complete, chamber temperature was quickly cooled down from 850℃ to 500℃ by N2 purge 30 seconds. Then, the chamber was slowly cooled down to 280℃

without N2 purge to avoid creaking of films. After five minutes later, wafers can be taken out from the chamber. By two-steps-cooling method, films’ creaks can be avoided

Wafer

Number Wafer Type Oxidation Temperature ( ℃ )

Oxidation Time (minute)

1 200 15

2

p-type

300 15

3 200 15

4

n-type

300 15

5 15 6

400

30

7 15 8

p-type

500

30

9 15 10

400

30

11 15 12

n-type

500

30

Table 3-1 The oxidation temperature and time of HfO2 films.

1. Initial RCA clean.

2. Thermally grow 5000 Å wet oxide.

3. Mask #1：define active region and RCA clean.

4. Sputtering 20 Å hafnium.

5. Thermal oxidize hafnium films in furnace.

(200℃, 300℃, 400℃ and 500℃ / 15 or 30 minutes)

5-1. RTA treatment at 850℃ for 30 seconds.

6. Thermal coating 5000 Å aluminum on top.

7. Mask #2：pattern top electrode and etch Al and HfO2.

8. Strip native oxide on backside and coat bottom Al electrode.

9. Al sintering (N2_400℃_30min).

Figure 3-1 Fabrication flow chart of ultra thin HfO₂ MIS capacitor.

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Chapter 4

Electrical Characteristics of Al/HfO ₂ /Si MIS Capacitors

4.1 Capacitance-Voltage Characteristics

In our experiments, we used HP2484A LCR meter to measure the 1MHz high frequency C-V characteristics of our MIS capacitors. We swept the gate bias from inversion region to accumulation region. There were three different die areas (i.e.

6.25×10^-6, 2.5×10^-5 and 1×10^-4 cm²) for discussing area depend effects. In addition, the oxidation temperature was ranging from 200℃ to 500 with 15 or 30 minutes.℃ Table 4-1 shows the measurement results of HfO2 capacitors under different process conditions with 6.25×10^-6 cm² die area. Unfortunately, while the oxidation temperature is lower than 400 , we only℃ get the effective C-V characteristics of n-type HfO2 capacitors under 300 15minutes oxidation condition℃ . The failure in quasi-static C-V measurement is due to the leakage current higher than the displacement current for most gate bias. Under such a low oxidation temperature, hafnium atoms may react with oxygen atoms to form HfO2 but with very weak chemical bonding. We find that this weakly bonding type of HfO2 layer couldn’t bear much gate bias but it has an effective accumulation capacitance. It seems that n-type HfO2 capacitors could have stronger chemical bonding than p-type HfO2 capacitors under low oxidation temperature. Table 4-2 and 4-3 show the measurement results of HfO2 capacitors with 2.5×10^-5 cm² and 1×10^-4 cm² die area respectively.

Fig. 4-1 shows the 1MHz high frequency C-V characteristics of p-type HfO2

capacitors with different die area under 400℃-15 minutes oxidation condition. We could see that the capacitors with smaller die area have larger accumulation capacitance, but the size of die area doesn’t influence the flat band voltage (VFB).

Besides, the slopes of these three C-V curves are almost the same. Fig. 4-2 shows the 1MHz high frequency C-V characteristics of p-type HfO2 capacitors with 6.25×10^-6 cm² die area under different oxidation conditions. Under 400℃-15 minutes oxidation condition, the capacitor has the largest accumulation capacitance and the smallest

V

∣ FB∣. The higher oxidation temperature and the longer oxidation time make the more negative flat band voltage shift. There exists several types of charges, including

15

interface trapped charge (Qit), fixed oxide charge (Qf), oxide trapped charge (Qot) and mobile ion (Qm), in the dielectric layer and at the substrate interface. To simplify, we call all these charges as interface effective positive charge Qi (C/cm²). So, the flat band voltage can be expressed as follows：

( )

The influence of Qi is to introduce an equivalent negative charge within semiconductor. Because the work function difference and interface effective positive charge will both make the band near semiconductor surface bending downward, a negative voltage must be applied on metal to reach flat-band condition [1]. Thus, the more negative VFB means more positive charges were produced at the interface during oxidation process. Fig. 4-3 shows C-V characteristics of three different gate dielectrics, including SiO2, (SiO2)0.5(Si3N4)0.5 and Si3N4 [2]. ∆VFB for nitride and oxynitride devices with respect to oxide device are 0.15 and 0.04 V. Interfacial fixed charge is 7.5×10¹¹/cm² for nitride and 2×10¹¹/cm² for oxynitride. The fixed charge of the nitride film shows greater than oxynitride gate stack. This is due to increased bond-strain in the bulk and at internal dielectric interface. Increased bond-strain results in more “border traps”. Comparing fig. 4-2 to fig. 4-3, ∆VFB for HfO2 under 400℃-15 minutes oxidation condition with respect to SiO2 device is about 0.2 V. This is because of more stress in the HfO2 device, which generates more intrinsic defects, including bulk traps in film, border traps and interfacial traps. In addition, oxidation temperature affects ∆VFB seriously. The higher oxidation temperature would cause more stress in the device and generate more intrinsic defects. It may be caused by our improper cool down process. These defects directly influence the quality of the insulator layer and the substrate interface (i.e. gate leakage, carrier mobility, reliability etc.). In addition, 400 oxidation temperature makes the slope of C℃ -V curve apparently stepper than 500 oxidation tempe℃ rature. It seems oxidation time doesn’t affect the slope of C-V curve. Consequently, for p-type HfO2 capacitor, under 400℃-15 minutes oxidation condition could obtain the best C-V characteristics.

4.2 Equivalent Oxide Thickness (EOT)

From C-V characteristics, like fig. 4-1 and fig.4-2, equivalent oxide thickness (EOT) could be obtained by the following formula：

tox = εr‧ε0‧A / C

Where εr is the dielectric constant of SiO2 (εr = 3.9), ε0 is the permittivity in vacuum

16

(ε0 = 8.85×10^-14 F/cm). A is the area of the capacitors (A = 6.25×10^-6, 2.5×10^-5 and 1×10^-4 cm²) and C is the accumulation capacitance measured at V∣ G - Vt∣= 1 V at 1 MHz. According to this formula, we could calculate all the electrical EOT of our capacitors, which listed in Table 4-1, 4-2 and 4-3. We see that n-type HfO2 capacitors with 6.25×10^-6 cm² die area under 300℃-15 minutes oxidation condition have the smallest EOT of 9.2 Å. For p-type HfO2 capacitors, with 6.25×10^-6 cm² die area under 400℃-15 minutes oxidation condition have the smallest EOT of 17.3 Å. In addition, under the same oxidation condition, we find that p-type capacitors have smaller EOT than n-type capacitors. It might be attributed to that the diffusion rate of hafnium and oxygen atoms in n-type substrate is larger than in p-type substrate.

Fig. 4-4 shows EOT of p-type HfO2 capacitors with different die areas. Under every different oxidation conditions, the devices with smaller die area have the smaller EOT. It is a very strange phenomenon. Devices with different die area on the same wafer under the same oxidation condition should have the same EOT. It is probably due to that the smaller die area attracts the larger ratio of edge charges around the device and thus has larger capacitance measured by HP4284, as shown in fig 4-1. If we eliminate the edge charge effect, the devices with different die area on the same wafer have the same EOT in fact. Fig. 4-5 shows EOT of p-type and n-type HfO2 capacitors with 6.25×10^-6 cm² die area under different oxidation conditions.

Higher oxidation temperature causes larger EOT of the device. Besides, longer oxidation time also slightly increase EOT of the device. The increase of EOT might result from the increase of interfacial layer which grown in the oxidation process. As shown in fig 4-6, during oxidation process, hafnium and oxygen atoms would diffuse to substrate and form an HfSiO interfacial layer. We will discuss the possible reasons of such EOT tendency by analyzing current-voltage characteristics.

4.3 Current-Voltage Characteristics

4.3.1 Leakage Current

Fig. 4-7 shows the J-V characteristics of p-type HfO2 capacitors with different die areas (6.25×10^-6, 2.5×10^-5 and 1×10^-4 cm²) under 400℃-15 minutes oxidation condition from 0 V to -1 V. We observed that the gate leakage current density becomes only a little larger while die area decreases. From table 4-1, 4-2 and 4-3, EOT of these three devices are 17.3 Å, 21.0 Å and 22.3 Å respectively. Fig. 4-8 shows J-V characteristics of p-type HfO2 capacitors with 6.25×10^-6 cm² die area under different oxidation conditions (400℃-15 minutes, 400℃-30 minutes, 500℃-15

17

minutes and 500℃-30 minutes) from 0 V to -1 V. The EOT of these four devices are 17.3 Å, 17.4 Å, 23.8 Å and 23.9 Å respectively. Apparently, the device under higher oxidation temperature and longer oxidation time has lower gate leakage current. In fig.

4-7, 5 Å increase of EOT (from 17.3 Å to 22.3 Å) only reduces a little gate leakage at VG = -1 V. But in fig. 4-8, 6.5 Å increase of EOT (from 17.3 to 23.8 Å) reduces gate leakage even more than 2 orders at VG = -1 V. Thus, from fig. 4-7, three similar magnitudes of gate leakage reveal that the thickness of devices with three different die area on the same wafer might be the same. As shown in fig. 4-8, the main reason of such a large repression of gate leakage between 400℃-15 minutes and 500℃-15 minutes oxidation conditions is the increase of thickness. Higher oxidation temperature could also make HfO2 film have stronger chemical bonding to effectively resist gate leakage. Besides, the devices under 500℃-15 minutes (EOT = 23.8) and 500℃-30 minutes (EOT = 23.9) oxidation condition have almost the same thickness but have about an order difference of gate leakage at VG = -1 V. Thus, the longer oxidation time mainly increases the intensity of chemical bonding.

Fig. 4-9 shows measured and simulated J-V characteristics of NMOSFET with SiO2 gate insulator. Gate leakage current density of 20 Å SiO2 gate insulator at VG = 1 V is about 3×10^-2 A/cm². From fig.4-9, however, gate leakage current density of the HfO2 capacitor with EOT = 17.3 Å at VG = -1 V is only about 3×10^-4 A/cm². Even thinner EOT of HfO2 capacitor but has less gate leakage than SiO2 device about 2 orders. Consequently, replacing SiO2 with HfO2 for gate insulator could effectively reduce gate leakage.

Then, we make plots of gate leakage versus EOT for further discussing. As shown in fig. 4-10, we could obviously find that, whether for n-type or for p-type HfO2 capacitors, gate leakage at Vg = 1 V of different die areas are almost the ∣ ∣ same, even if their EOT are not the same. With the increase of EOT, however, the gate leakage doesn’t decrease. Consequently, we think the EOT of devices with different die areas on the same wafer should be the same in fact. From fig. 4-11, we observe that, whether for n-type or for p-type HfO2 capacitors, while the oxidation temperature rises, the EOT becomes larger and the leakage becomes less. Higher oxidation temperature makes the HfSiO interfacial layer become thicker, as shown in fig. 4-6. The thicker interfacial layer causes the larger EOT of HfO2 gate insulator.

Higher oxidation temperature also makes the chemical bonding stronger. Thicker physical thickness and stronger chemical bonding both contribute to the decrease of gate leakage current. Longer oxidation time slightly increases EOT and decreases gate leakage current. In addition, another interesting phenomenon is that under the same

18

oxidation condition, n-type HfO2 capacitor has larger EOT but larger gate leakage current than p-type HfO2 capacitor. The larger EOT might result from the larger diffusion rate of hafnium in company with oxygen atoms in n-type substrate than in p-type substrate. Generally, the device with larger EOT has less leakage current. Thus, we think the HfO2 layer grown on p-type substrate has better quality of resisting gate leakage than on n-type substrate.

Fig.4-12 shows J-V characteristics of n-type and p-type HfO2 capacitors with 6.25×10^-6 cm² die area from -1 V to +1 V. For p-type, the leakage current under positive gate bias is much lower than negative case by 3 orders. For n-type, the leakage current under negative gate bias is lower than positive case by 1 order. The reverse leakage is thought to be dominated by surface leakage [3]. The surface generation current has been reported to be linearly correlated to the interface state density [4]. These interface states are caused by the dangling bonds at the Si/SiO2

interface [5][6]. This component is often masked by surface leakage, especially at low temperatures [7][8]. This is illustrated in fig. 4-13.

Fig. 4-14 shows J-V characteristics of n-type HfO2 capacitors with different die areas under 400℃-30 minutes oxidation condition from 0 V to +10 V. In this figure, we could see the devices with 6.25×10^-6, 2.5×10^-5 and 1×10^-4 cm² die area, generate breakdown at VG = 3.85 V, 3.50 V and 3.10 V respectively. The device with smallest die area has the biggest breakdown voltage (VBD), which means the best quality of resisting leakage current. We think more ratio of leakage current could pass through the gate insulator from edge side between HfO2 layer and isolation oxide in the device with smaller die area. The leakage current which doesn’t pass through HfO2 layer doesn’t destroy the structure of HfO2 layer. Thus, the device with less ratio of leakage current passing through the HfO2 layer could have larger breakdown voltage. Fig.4-15 shows J-V characteristics of p-type HfO2 capacitors with 6.25×10^-6 cm² die area under different oxidation conditions (400℃-15 minutes, 400℃-30 minutes, 500℃-15 minutes and 500℃-30 minutes), correspond separating EOTs with 17.3 Å, 17.4 Å, 23.8 Å and 23.9 Å, from 0 V to -10 V. Breakdown voltages of these four devices are -6.05 V, -6.30 V, -7.15 V and -7.50 V. We could find that the device with thinner thickness and weaker chemical bonding generates breakdown more easily. In addition, like SiO2, thicker HfO2 shows more abrupt breakdown characteristics compared to thinner HfO2.

Fig. 4-16 displays gate current as a function of the gate voltage for four oxide degradation stages in a 2000 µm² SiO2 NMOSFET. After SBD, a large increase of the

19

substrate current is observed in the whole voltage range [9]. Fig. 4-17 shows four oxide degradation stages of p-type HfO2 capacitors with 6.25×10^-6 cm² die area under 400 15 minutes oxidation condition.℃ Like SiO2 NMOSFET, HfO2 capacitor has four degradation stages. This hints HfO2 might have similar breakdown mechanism with SiO2.

4.3.2 Band-gap Diagram and Conduction Mechanism

Selecting a gate dielectric with a higher permittivity than that of SiO2 is an essential choice. The required permittivity must also be balanced against barrier height to limit tunneling. For electrons traveling from the silicon substrate to the gate, this barrier is the conduction band offset, ∆EC. A gate dielectric must have a sufficient

∆EC value to poly-Si, and to other gate materials, in order to obtain low off-state currents (leakage). If the experimental ∆EC is < 1.0 eV, it will likely preclude the oxide's use in gate dielectric applications because thermal emission or tunneling would lead to unacceptably high leakage currents [10]. Among the several materials that have been investigated as gate dielectrics, as shown in Table 1-3, the dielectric constant generally exhibits an inverse relationship to the energy band gap.

Fig. 4-18 shows the energy band diagram of the SiO2 MIS capacitor with Al gate.

The energy band gap of SiO2 is 8.9 eV. Fig. 4-19 shows the energy band diagram of the HfO2 MIS capacitor with Al gate. The energy band gap of HfO2 is 5.7 eV [10].

The electron affinity 2.82 eV for HfO2 is obtained from the measurement of Fowler-Nordheim tunneling current of metal/ HfO2/Si MIS capacitors [11]. Taking the work function of Al as ФAl = 4.1 eV, the barrier height of Al/ HfO2 is ФAl/ HfO2 = 1.28 eV and the barrier height of HfO2/Si is ФSi/ HfO2 = 1.13 eV.

There are many possible conduction mechanisms in insulators [12]. For SiO2, the dominate conduction mechanism was believed to be Fowler-Nordheim tunneling in the medium field (6~10MV/cm), low temperature region (T＜200 ) [℃ 13]. As the thickness scales down, it would show the direct tunneling characteristics [14]. The weak temperature dependence of this tunneling process is well-known. The schematic illumination of conduction mechanism is shown in fig. 4-20, including Schottky emission, F-N tunneling, and Frenkel-Poole emission.

The leakage current governed by the Schottky emission is as following:

JSK = A* T² exp{ -q[φB - ( qE / 4πεoεd )^1/2 ] / kT }

20

where A* is a constant, φB is the potential height on the surface, E is the electric field, ε0 is the permittivity in vacuum, εd is the dynamic dielectric constant, T is the temperature, and k is the Boltzmann constant. Fig. 4-21 shows the Schottky plot of n-type HfO2 capacitors with 6.25×10^-6 cm² die area under different oxidation conditions. The gray filled circles on each curve indicate where the individual slope of the curves becoming constant, which means the generation of Schottky emission happened. For the substrate electron injection case, the experimental results fit the Schottky emission theory well. While electric field is between 1 MV/cm to 16 MV/cm, the fitting slopes are almost constant. N-type HfO2 capacitors under 300℃-15 minutes oxidation condition begins to generate Schottky emission at VG = 0.09 V. Even for n-type capacitors under 500℃-30 minutes oxidation condition, which have largest EOT, Schottky emission occurs at very low bias VG = 0.82 V.

Fowler-Nordheim (FN) tunneling is the flow of electrons through a triangular potential barrier illustrated in fig. 4-20. Tunneling is a quantum mechanical process similar to throwing a ball against a wall often results that the ball goes through the wall without damaging the wall or the ball. It also loses no energy during the tunnel event. The probability of this event happening, however, is extremely low, but an electron incident on a barrier typically several nm thick has a high probability of transmission. The FN current (IFN) is given by the expression [15]:

⎟⎟ ⎠

considered to be constants. A and B are given as the following:

⎥⎦⎤

where mox is the effective electron mass in the oxide, m is the free electron mass, and Φ is the barrier height at the silicon-oxide interface given in units of eV in the B

expression for B. Φ is actually an effective barrier height that take into account _B barrier height lowering and quantization of electrons at the semiconductor surface.

Rearranging

I

_FN formula gives by:

21 the oxide is pure Fowler-Nordheim conduction [15]. The slop of linear F-N plot gives A and the intercept yields B. Fig. 4-22 shows F-N plot of n-type HfO2 capacitors with 6.25×10^-6 cm² die area under different oxidation conditions. The gray filled circles on each curve indicate the slopes of the each curves becoming constant, which means the generation of F-N tunneling happened. N-type HfO2 capacitors under 300℃-15 minutes oxidation condition begins to generate F-N tunneling at VG = 1.42 V. We could find that device with thinner EOT generates F-N tunneling at smaller gate bias.

It is consistent with our prediction.

The leakage current governed by Frenkel-Poole emission is as following:

JFP = B E exp{ ‧ ‧ -q[φt - ( qE / πεoεd )^1/2 ] / kT }

where B is a constant, φt is the barrier height of trap level. The Frenkel-Poole emission is due to the field-enhanced thermal excitation of trapped electrons into the conduction band. Fig. 4-23 shows Frenkel-Poole plot of n-type HfO2 capacitors with 6.25×10^-6 cm² die area under different oxidation condition. The gray filled circles on each curve indicate the slopes of the curves becoming constant, which means the generation of Frenkel-Poole emission happened. N-type HfO2 capacitors under 300℃-15 minutes oxidation condition begins to generate Schottky emission at VG = 0.21 V. While electric field is between 4 MV/cm to 16 MV/cm, the fitting slopes are almost constant, indicating Frenkel-Poole emission is one conduction mechanism of leakage current. Even for n-type capacitors under 500℃-30 minutes oxidation condition, which have largest EOT, Schottky emission occurs at very low bias VG = 0.92 V. From above, we could find that Schottky emission occurs at very low gate bias and F-N tunneling occurs at higher gate bias than both Schottky emission and Frenkel-Poole emission. In addition, n-type HfO2 capacitors under 300℃-15 minutes oxidation condition always generate Schottky emission, F-N tunneling or Frenkel-Poole emission happened earliest because of smallest EOT.

4.4 RTA Treatment

In our experiments, after oxidation process, we could have an additional RTA treatment at 850 for 30 seconds to HfO℃ 2 film. Fig. 4-24 shows 1MHz high

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