accessed using three memory cycles: program read, data read, and data write.
Three separate, mutually exclusive control signals from the CPU determine which of the three types of external memory cycle are to occur. Only one of the signals is active at any one time, making the memory interface very simple. A program read cycle is indicated when the /PSEN (active low, program strobe enable becomes active, a RAM data read cycle when /RD (active low, read) goes active, and a RAM data write cycle is indicated when /WR (active low, write) becomes active. The /PSEN signal can be directly connected to enable the program ROM, and the /RD and /WR signals can be connected to the output enable and write enable pins of the data RAM. Since the lower eight address bits are multiplexed on the data bus, they are held by a transparent latch (74x373). The processor outputs an active high enable signal, ALE (address latch enable), to control the latch. The processor, latch, program EPROM, and SRAM are shown in Figure 6-1. The timing diagrams for the three memory
cycles as shown in the processor specification, other chips in the sys-tem, beginning with the memory chips.
Memory Selection and Interfacing
Most embedded computer designs make use of EPROM for non-volatile pro-gram storage and SRAM for volatile data storage. For this example we will use one of each type: 32Kx8 UV erasable EPROM to store the program, and a 32Kx8 CMOS static RAM. The multiplexed address bits, A0..7, will be latched from the AD0..7 lines using a 74ALS373 transparent latch. Since there is only one memory of each type, no address decoding is necessary for the chips to be enabled directly from the processor memory control lines /PSEN, /RD, and /WR.
8031
Figure 6-1: Preliminary design of the CPU and memory interface.
Preliminary Timing Analysis
Critical timing parameters for the EPROM, SRAM, and address latch are shown in Tables 6-1 and 6-2 and are excerpted from the component specification sheets.
For an experienced designer, the preliminary timing analysis may consist of just a quick look at the data sheets. A limited analysis of key timing parameters will be performed first to identify any major changes that may need to be made in the design. The parameters to be evaluated here will be the CPU memory access time requirements versus the various memory maximum access time capabilities, control signal pulse widths, all related to clock speed. First, we will examine the program memory read access time, and then the data read and write access times.
The instruction fetch (program memory read) cycle of the CPU is shown in Figure 6-2.
The sequence of events is as follows:
1) ALE goes active (high), enabling the external latch to pass A0..7 through to its outputs. The 16-bit PC (program counter) value, containing the address of the next instruction byte to be fetched from EPROM, will then be used to drive the 16 address lines.
2) The lower eight address lines A0..7 are driven on Port 0 (also known as AD0..7 since it is multiplexed with A0..7 and D0..7), at the same time as A8..15 are driven on Port 2. At this point, the complete 16-bit address of the next instruction is available on Port 2 and the address latch. As soon as the address lines are stable and valid, the address access time for the memory begins. Since the address will be valid before ALE goes low, a transparent latch is used to give the memory the address as soon as possible.
Instruction Address
Instruction Cycle
PSEN RD ALE Latch Output
Address/Data Bus Instruc. Addr. Instruction Instruction Fetch Cycle
Program Memory
Data Fetch Cycle Data Memory
Data Addr. WR Data Data Address Fetch Cycle
RD Cycle
4 5
1
3
2
Figure 6-2: Instruction cycle timing diagram.
If a negative edge triggered register was used instead of a transparent latch to hold the address bits, then address bits A0..7 would not be available until a propagation time after the falling edge of ALE.
3) Once the address lines are valid, ALE goes low, latching A0..7 bits in the external address latch. This allows the multiplexed data lines to be used for data transfer without disturbing the lower eight address lines that are held in the latch for the remainder of the cycle. Since the upper eight address lines (A8..15) are not multiplexed, they remain valid for the rest of the cycle and do not need to be latched.
4) /PSEN goes active (low) to indicate that this is a program memory read cycle, enabling the EPROM to drive the data bus. This enable signal begins the program memory read access cycle time for the EPROM.
5) /PSEN goes inactive (high) signaling the end of the program read cycle and clocking the EPROM data into the processor. Because this signal is used to clock data into the CPU from the data bus, there are associated setup and hold times for the data relative to the rising edge of the /PSEN signal.
Using the preliminary design, the first parameters to be investigated are the access times. Table 6-1 gives the program memory timing parameters for the 8031. The memories that have longer access times are less expensive than the fast ones, so we would like to use the least expensive parts that will meet the specifications.
Both the address and enable access times are of interest, including all possible propagation paths for these signals. The slowest path will determine the maxi-mum clock frequency that can be used for reliable operation, up to 12 MHz, the maximum CPU clock frequency. The ALE path will be ignored for now.
All three paths must be evaluated to determine which one is the speed limiting condition. The three signal propagation paths for the program read cycle are:
a) Valid address A8..15 on Port 2, EPROM address access time b) Valid address on port 0, D to Q
delay through the latch, and EPROM address access c) /PSEN active, EPROM enable
access time
These three propagation paths are shown in Figure 6-3. Figure 6-4 shows the program memory timing diagram for the 8031.
8031
Figure 6-3: Three access propagation paths for program read.
Assuming a 12MHz clock, the timing analysis for the three paths is:
Path A
The delay from when the CPU provides a valid address A8..15 onPport 2 until the end of the EPROM address access time, resulting in valid data from the EPROM on the data bus. Figure 6-5 shows the EPROM timing diagram. The
TLHLL
TPLPH TCY
TLHLH
TPLIV
TAVIV
TAZPL TPHDX TPHDZ
TAVLL TLLAX
OSC
FLOAT
T12 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2
ALE
PSEN
RD, WR
Port 2
Port 0 A7-A0 FLOAT INSTR IN FLOAT A7-A0 FLOAT INSTR IN FLOAT
ADDRESS A15-A8 ADDRESS A15-A8 ADDRESS
OR SFR P2
Table 6-1: 8031 program memory timing parameters.
Figure 6-4: 8031 program memory timing.
Variable Clock 12 MHz Clock 1/TCLCL = 1.2 to 12 MHz
Symbol Parameter min max units min max units
TCLCL Oscillator Period 83 nS 83 833 nS
TCY Minimum Instruction Time 1.0 uS 12TCLCL nS
TLHLL ALE Pulse Width 140 nS 2TCLCL-30 nS
TAVLL Address Set Up to ALE 60 nS TCLCL-25 nS
TLLAX Address Hold After ALE 50 nS TCLCL-35 nS
TPLPH /PSEN Width 230 nS 3TCLCL-20 nS
TLHLH /PSEN, ALE Cycle Time 500 nS 6TCLCL nS
TPLIV /PSEN to Valid Data In 150 nS 3TCLCL-100 nS
TPHDX Input Data Hold After /PSEN 0 nS 0 nS
TPHDZ Input Data Float After /PSEN 75 nS TCLCL-10 nS
TAVIV Address to Valid Data In 320 nS 5TCLCL-100 nS
TAZPL Address Float to /PSEN 0 nS 0 nS
NOTE: Test Conditions T=0–70°C, Vcc= 5V±5% Port 0, ALE and /PSEN Outputs: CL = 150 pF All Other Outputs: CL = 80 pF
CPU requires that the data from the EPROM be available 320 nanoseconds (nS) (TAVIV) after being presented with a valid address. The -30 version of the EPROM has an address access time of 300 nS max. (EPROM tAA), so there is 20 nS of margin for this EPROM at this clock speed.
TAVIV - EPROM tAA = 320 - 300 = 20 nS margin
Note that the -15, -20, etc. at the top of Table 6-2 are suf-fixes that refer to the memory access times.
The CPU ALE line is connected directly to the latch enable input
of the 74ALS373 transparent latch. Table 6-3 gives timing specifications for this device. Remember that this type of latch simply passes the D inputs directly through to the Q outputs (after a propagation delay), as long as the enable
input remains high. The ‘373 type latch has an asymmetrical propagation delay from the D input to the Q output, since tPLH from D->Q is 12 nS max, and tPHL is 16 nS max. This corresponds to the first part of the propagation path B.
As can be seen in Figure 6-2, ALE goes high before the address goes valid. The delay from the enable (E) input to
Table 6-2: EPROM
Figure 6-5: EPROM timing diagram.
Parameter From To min max Unit (input) (output)
Table 6-3: Timing specifications for 74ALS373 transparent latch.
Test -15 -20 -25 -30
Parameter Symbol Conditions min max min max min max min max Units
Address access tAA /CE=/OE= VIL 170 200 250 300 nS
/CE access tCE /OE= VIL 170 200 250 300 nS
/OE access tOE /CE= VIL 10 60 10 70 10 100 10 120 nS
Output disable tDF /CE= VIL 0 50 0 50 0 60 0 105 nS
the output (Q) is only 23 nS, much less than the time the CPU takes to put its address out on the bus. The delay in the ALE path is:
TLHLL-TAVLL = 140 - 60 = 80 nS
Since the latch is enabled in 23 nS, but the address is not available from the CPU until 57 nS later, this path is not considered. In this, as in most designs, the ALE delay path is not critical, so it is ignored. This must be considered for some CPUs, such as the Dallas Semiconductor high-speed 80C320 family of microcontrollers. Path B, from D to Q, is always worth examining.
Path B
From the time a valid address is available on port 0 (the multiplexed bus), plus the maximum D to Q delay through the latch, and the EPROM address access time, until valid data is on the bus.
The CPU allows the same total of 320 nS delay time for this path as above.
In this case however, there is the additional delay of the latch that reduces the time available to the memory. The latch is specified for a maximum D to Q delay, tP D->Q of 16nS worst case. So from the 320 nS available, 16 nS is used by the latch, and 300 nS is used by the EPROM, leaving only four nanoseconds of margin!
TAVIV - EPROM tACC - Latch tP D->Q = 320 - 300 - 16 = 4 nS margin This is a slim, but acceptable margin, as long as the device outputs can drive the actual loads on their outputs. If the load capacitance exceeded the speci-fied test load capacitance usually listed in the notes in the timing section, then the rise/fall time would be extended, possibly throwing this design out of the specified limits at the full 12 MHz clock speed.
Path C
For Path C, we need to evaluate the delay between the time the CPU enables the program memory and when the memory instruction output appears on the bus. The enable access time is from the activation of /PSEN, which enables the EPROM chip enable (/CE), until the EPROM provides a stable and valid instruction on the data bus.
Once again, the design margin is the time allowed by the CPU, less the time taken by the external circuits. The CPU allows TPLIV or 150 nS.
TPLIV - EPROM tCE = 150 - 300 = -150 nS NEGATIVE design margin!
When /PSEN is directly connected to the EPROM /CE line, the CPU provides 150 nS (TPLIV) for the EPROM enable access time, but the -30 EPROM tCE is 300 nS, which is 150 nS TOO SLOW!
At this point, we have several options:
• Decrease the CPU clock speed.
• Buy a faster EPROM.
• Change the wiring: connect /PSEN to /OE instead of /CE.
Let’s examine these three alternatives more closely.
1) Reduce the clock speed of the CPU to conform to the EPROM’s chip enable access time. This has the obvious disadvantage that the processor will run more slowly.
2) Buy an EPROM with faster chip enable access time. Faster parts cost more and, in this case, the fastest device in the table has a chip enable access time of 170 nS, which is still too slow.
3) Rewire the /PSEN line to EPROM output enable input (/OE) and connect the chip enable (/CE) to ground. This does not require slowing the chip or using a faster, more expensive memory.
There is one other solution that is not available on the standard 8051 processor:
the use of “wait states” which stretch the memory cycle timing by one or more clock cycles. The standard 8051 family parts do not incorporate this feature, but the high-speed versions do. The 80C320 family of high-speed microcon-trollers from Dallas Semiconductor does allow wait states. These devices have internal registers that can be programmed to stretch memory cycles as needed to accommodate slower memories. Some other types of processors require external hardware to insert wait states.
Comparing all options, the simplest solution is probably 3). Let’s see what happens to the Path C timing design margin calculation when we use that approach. In this version, the CPU’s /PSEN line drives the EPROM’s /OE input, with the /CE grounded. As before, the CPU allows TPLIV or 150 nS,
but in this case we use the EPROM’s output enable access time, tOE. Looking back at the EPROM specifications, we find that for the slowest (-30) part, the worst-case value for tOE is 120 nS.
TPLIV - EPROM tOE = 150 - 120 = +30 nS design margin
When /PSEN is directly connected to the EPROM /OE line, the CPU provides 150 nS (TPLIV) for the EPROM enable access time, and the -30 EPROM tOE is 120 nS, which is more than fast enough. This design change allows the CPU to run at the full 12MHz rating. The example shows how we may have to change the design in order to optimize the timing, and the iterative nature of the design process.
As in everything else, there are some drawbacks and implications for this approach that need to be considered:
• The EPROM is always enabled when the /CE input is grounded, so only one EPROM can be used this way. This has the disadvantage that the EPROM draws its maximum operating power constantly.
• Use of /CE to enable the device reduces power consumption, which is important for battery powered applications, especially when there are multiple devices. Enabling with the /CE input allows for the use of mul-tiple memory chips in the system by using a memory address decoder to decode the appropriate address range. The decoder output can drive the selected memory device /CE input lines one at a time, just as we saw in the previous module on memory address decoding. That way only one of the memory devices is powered at a given time. The memories’ /OE lines would be connected to the processor’s /PSEN signal output, so that slower memories could still be used. As is the case for other specs, the speed or power consumption of the system can be optimized.
This concludes our example, but it is evident that there are many other timing specifications that must be evaluated for a given design. Fortunately, the same methods we have used here are applicable to the other timing specifications and devices used in a typical embedded controller system. This completes the preliminary evaluation of the program fetch cycle memory access times, which are often among the most difficult to meet. The next step is to analyze the data memory cycle timing.