Gate arrays are fabricated with a fixed array of gates and the wiring is defined by the user when the chip is manufactured. The advantage of this approach is that the chips can be fabricated up to the point where the interconnecting wires are placed on the chip, ready for a custom interconnect. Since most of the processing is completed before the connections for any particular design are placed on the chip, these “almost finished” devices can be produced and stockpiled without any interconnects. The final interconnect can be added to define a given design, resulting in a customized version of a nearly standard part. Gate arrays are often used when the production volume is too low to justify a full custom design, but high enough so that a user programmable device is not cost effective.
User programmable logic devices (PLDs) are a family of devices that are all manufactured in the same way, and can be customized using a special pro-gramming process much like an EPROM. An EPROM can be used to implement arbitrary logic functions by using the address lines as inputs and data lines as outputs. Thus, a 1Mx8 EPROM could have eight independent logic outputs that can be any boolean function of any of the 20 input address bits. The fully completed truth table is programmed into the EPROM so that each unique input pattern will result in the appropriate data at the outputs. EPROMs are not often the best choice for the kind of logic required in most designs because of their speed and relative complexity, which translates to performance and price.
Other types of devices have been designed specifically for use in those appli-cations. There is a wide range of devices available, from fuse-linked two-level combinatorial logic and EPROM registered logic arrays, to arrays of logic blocks programmed with SRAM memory in each block. These devices span a range of complexity from one hundred to more than ten thousand usable gates.
These families of devices are referred to as programmable logic arrays (PLA), programmable array logic (PAL, a registered trademark of AMD Inc.), and other trademarked names.
Field programmable gate arrays (FPGAs) are a cross between gate arrays and PLDs. They have an array of logic with user programmable interconnections.
FPGAs are generally used where the desired logic function is too large to fit in a sum-of-products device, and the volume is too low to justify the use of a gate array or custom logic. FPGAs are available in sizes large enough to implement an entire CPU.
Introduction to Programmable Logic
The most common types of programmable logic are two level (AND-OR) logic chips implementing a sum-of-products logic function on each output.
An example sum of products form in standard notation is: F = AB + CDE The notation used in this book for the example above is: F = A*B + C*D*E.
The conventions we will follow include:
• Logic AND is denoted by an asterisk: *
• Logic OR is denoted by a plus sign: +
• Logic inversion (NOT) by a slash: /
The examples above would require three gates: one two-input AND gate, one three-input AND gate and a two- input OR gate to combine the AND gates’
outputs. (Other references may use different notation, such as & for logic AND, or a minus sign - for inversion, e.g.: F = A & B + -C.)
There are several varieties of two level programmable logic devices, with most of the variations relating to the type of output. Some devices have output flip-flops to allow storage and sequential logic, and some have tri-state drivers.
The outputs of some of these devices can be defined at the time they are pro-grammed as inverting, non-inverting, latched, bi-directional, asynchronous and other configurations. The pattern used to program the device is referred to as a fuse map because the original chips used fuse linked memory and the map represents the pattern of blown fuses.
Technologies: Fuse-Link, EPROM, EEPROM, and RAM Storage Fuse-link PLDs consist of an array of fuses that make connections between the inputs and the logic gates inside the chip. When the chip is programmed, the unwanted fuses are “blown open” to leave only the desired connections.
Fuse-link devices are implemented using bipolar logic so they are very fast, and consume a lot of power. Obviously they can only be used once, so they are not as desirable for prototyping purposes as an erasable device. Erasable parts, built using the same technology as EPROM, EEPROM, and RAM data storage for the arrays are available and carry with them the same characteristic advantages and disadvantages as their respective memory types.
Architectures
The first user programmable logic array chips had two levels of asynchronous logic. They were organized with two arrays of programmable fuse links, one connecting the inputs to an array of AND gates and the other connecting the AND gate outputs to an array of OR gates driving the output pins. This type of device allows arbitrary sum-of-products logic functions to be implemented limited only by the number of AND and OR gate inputs, and the I/O pins.
Programmable array logic devices are similar to PLA devices except that there is only one fuse array connecting the inputs to the AND gate array. The con-nections between the AND and OR gates in the PAL are fixed by the design of the PAL. Both PLAs and PALs are made with either active high or active low outputs. It is important to note that the arrays and inputs are not necessarily identical; some OR gates in a PAL may have more inputs than others on the PAL, for example.
Field programmable gate arrays have a more general architecture, and are not limited to the sum-of-products form. FPGAs have programmable intercon-necting wires, logic blocks, and I/O pins. The connections and logic in FPGAs are defined by use of either static RAM, E/EEPROM or anti-fuses. Anti-fuses are like fuses, except that they have a high resistance in the unprogrammed state and when programmed their resistance becomes much lower. The anti-fuse is programmed to make a connection by forcing a current through the anti-fuse. Anti-fuse FPGAs are based on an array of gates and wires that can be selectively shorted with the anti-fuse acting as a one time programmable short circuit. FPGAs are almost exclusively implemented in CMOS technol-ogy because of the high logic density to keep the chip power and temperature to reasonable levels. Static RAM based FPGAs are composed of logic blocks with embedded volatile static RAMs that must be loaded with configuration data every time they are powered on. The logic functions and interconnection information is stored in volatile static RAM. The configuration can be loaded from an EPROM or EEPROM directly or via a CPU before they are used.
Relatively large supply currents are drawn by bipolar PLDs, so CMOS versions have been made available to reduce the power consumption requirements. Most of the CMOS PLDs are actually mixed NMOS and CMOS logic, so their power dissipation is not as low as pure CMOS. Use of a PLD in a battery-powered application will generally require a pure CMOS PLD to maximize battery life.
Erasable (E/EE) versions are available from several vendors, which are par-ticularly useful in the development and debug of a new design when things change frequently. The fuses are replaced with floating gate switches with essentially the same construction as the EPROM and EEPROM memory cells described earlier. The EPROM versions of these parts are sold in windowed packages so they can be erased just like a UV EPROM, as well as non-windowed packages that can only be programmed once (one-time programmable, or OTP).
The EE versions of these parts are erased electrically before they are programmed.
Small programmable logic devices consist of an array of programmable connec-tions, or fuses, interconnecting the input signals with a number of AND gates, followed by an array of connections between the AND gates and some OR gates, resulting in one or more “sum-of-products” logic outputs. The notation used to illustrate the fusible interconnections between the inputs, gates, and outputs is shown in Figure
signal to gates that have a large number of inputs. Instead of showing every gate input, a single line represents multiple inputs, and an “x” is placed at points where the gate inputs are connected to one of the PLD input signals.
Figure 7-2
Figure 7-1: PAL logic diagram shorthand notation.
Input Buffer Input Lines
Figure 7-2: Simplified PAL logic diagram.
be organized. The simplest approach is to use a PROM memory as a program-mable logic device, using the address lines as input and the data lines as output.
Figure 7-3 shows a PROM memory, with an array of AND gates connected to decode
con-nections in the AND array. The top AND gate decodes address zero, enabling the pattern programmed in the top row of fuses to be presented at the output.
This pattern is the 4-bit word of data stored in location zero as a pattern of programmed fuses.
The advantage of using a PROM as a PLD is it can implement any logical function of the inputs, regardless of complexity of the logic function to be represented. This is because each possible permutation of the inputs corre-sponds to one memory location, and the PROM is essentially a physical implementation of the complete logic truth table. Unfortunately, the number of bits in the memory grows exponentially with the number of inputs. Since most practical logic functions do not have very many product terms on average, the memory is very sparsely filled with data. This means most of the circuitry is effectively wasted.
X X X X
X = Fuse-Link Crosspoint Connection
• = Fixed Connection AND Array (Fixed)
n Outputs Figure 7-3: Typical PROM as PLD architecture.
Programmable Logic Arrays
The PLA is a very flexible logic device, as it allows both the AND as well as the OR arrays to be programmed by the user. Figure 7-4 illustrates the archi-tecture of a typical PLA.
The PLA allows the imple-mentation of almost any OR gates, and output pins.
While the PLA architecture allows more efficient utili-zation of the resources on the chip, it is also more difficult to program, as a PLA with two arrays.
PAL-Style PLDs
While there is a wide variety of programmable logic available, the most preva-lent low cost version used in embedded designs is the PAL, a variation of the PLA sum-of-products chip. Consisting of a programmable AND (product) array and a factory-defined OR (sum) array, it is very similar to a standard memory device. As a result, many memory programmers can also be used to program PALs. This is a key reason for the success of these devices, along with the availability of software to ease in designing the fuse patterns for implementing specific users designs.
In a typical PAL, the inputs and their logical complements are provided to each of the AND gates through a programmable array of fuse connections.
PLA — 4 IN - 4 OUT - 16 Products
X = Fuse-Link Crosspoint Connection AND Array (Programmable)
X X X X X X X X
Figure 7-4: Typical PLA architecture.
The connections between the AND and OR gates are fixed by the manufacturer, and in most cases, some of the outputs are also fed back to the input array.
Figure 7-5 shows the the logic and fuse con-figuration used in most PAL devices. It has four inputs and four outputs which are non-inverting sums of four products.
Most small PLD parts use a numbering convention that makes it easier to determine the configuration of the logic. The number is usually composed of three parts: the number of inputs to the array, output circuit type, and number of outputs. Thus a PAL with the part number 16L8 has 16 inputs to the AND array (not necessarily that many input pins), and eight active low outputs (L), while a 12H6 has 12 inputs, and six active high (H) outputs. A device number with an “R” in it has an output register, and a “V” indicates variable or user programmable out-puts. Some of the pins may
A
Figure 7-5: Example of PAL fuse programming.
PLA — 4 IN - 4 OUT - 16 Products
AND Array (Programmable)
X X X X X X X X
X = Fuse-Link Crosspoint Connection
• = Fixed Connection
Figure 7-6: Typical PAL organization.
be shared inputs and outputs. Not all of the outputs are necessarily of the same type, however. The 16R4, for example, has four registered outputs and four asyn-chronous (un-registered) outputs. The V parts have a special output “macro-cell”
that can be programmed to be asynchronous (un-clocked), synchronous (clocked), inverted, non-inverted, feedback internally to the AND array, and so on.