Chapter 5 A Programmable Clock Generator for Sub- and Near-Threshold DVFS
5.7 Design Implementation
The proposed clock generator is implemented in UMC 65nm standard CMOS technology. Its major characteristics are operation in sub- and near-threshold regions and PVT compensation for locking range of clock generator. The clock generator can work correctly within +/- 10% voltage variation, -25°C to 125°C, and all process corners. The layout view of proposed clock generator is shown in Figure 5.26.
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Figure 5.26 Layout view of proposed clock generator
5.8 Simulation Results
The proposed programmable clock generator for sub/near-threshold DVFS system is implemented in UMC 65nm CMOS technology. It can operate in the voltage range from 0.2V to 0.5V. At 0.2V, the frequency of reference clock is 156 KHz; it consumes 0.18 uW with maximum output frequency 625 KHz. At 0.5V, the frequency of reference clock is 5 MHz; it consumes 5.17 uW with maximum output frequency 20 MHz. Figure 5.27 and Figure 5.28 show the operation waveforms of the proposed clock generator at 0.2V and 0.5V. Table 5.3 gives the summary.
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Figure 5.27 The operation waveform at 0.2V with 4X output clock
Figure 5.28 The operation waveform at 0.5V with 4X output clock Sub/Near-threshold Programmable Clock Generator
Supply Voltage 0.2~0.5V
Process UMC 65nm CMOS
Area 0.077×0.125mm2
Reference Clock 156KHz @ 0.2V
5MHz @ 0.5V Max. Output Frequency 625KHz @ 0.2V
20MHz @ 0.5V Min. Output Frequency 19.5KHz @ 0.2V
625KHz @ 0.5V
Output Jitter 60ns @ 625KHz CLKOUT, 0.2V 4ns @ 20MHz CLKOUT, 0.5V Power Consumption 0.18uW @ 625KHz CLKOUT, 0.2V
5.17uW @ 20MHz CLKOUT, 0.5V Table 5.3 Summary of proposed clock generator
Figure 5.29 ~ Figure 5.32 show the PTV compensation for the locking range of clock generator. Before compensation, due to the effects of environmental variations,
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the reference clock is not in the locking range. Thus the clock generator is not able to output multiplied clock. After PVT compensation, the reference clock is in the locking range for various environmental conditions.
(a) (b)
Figure 5.29 PVT compensation for locking range of clock generator at 0.2V TT corner (a) before compensation (b) after compensation
(a) (b)
Figure 5.30 PVT compensation for locking range of clock generator at 0.2V FF corner (a) before compensation (b) after compensation
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(a) (b)
Figure 5.31 PVT compensation for locking range of clock generator at 0.5V TT corner (a) before compensation (b) after compensation
(a) (b)
Figure 5.32 PVT compensation for locking range of clock generator at 0.5V FF corner (a) before compensation (b) after compensation
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Chapter 6
Conclusions and Future Work
6.1 Conclusions
The unified logical effort models considering voltage and temperature variations are proposed, which cover all MOS operation ranges including strong-, moderate- and strong-inversion range. These models have been established in UMC 90-, 65-nm, PTM 65-, 45- and 32-nm CMOS technologies. They are used on two test vehicles to estimate the path delay. Simulation results show that the logical effort average modeling error is no more than 8.40%. A thermally robust buffered clock tree using logical effort compensation is proposed. By tuning the logical effort of clock buffer to a fixed value, the buffer delay keeps the same, thereby reducing temperature-induced clock skew. With the adoption of tunable-width inverter, the logical effort can be controlled. The proposed thermally robust clock tree has been built in UMC 65-nm CMOS technology, which shows that the clock skew is reduced by up to 97.8%, and 72.2% in average. A programmable clock generator for sub- and near-threshold DVFS system is proposed. The clock generator’s output frequency is from 1/8X to 4X times of reference clock. It is able to adjust fluctuated locking range of the clock generator in various PVT conditions. At 0.2V, it consumes only 0.18uW with a 156KHz reference clock. The proposed clock generator has been implemented in UMC 65-nm CMOS technology. It is suitable for use of sub- and near-threshold DVFS system.
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6.2 Future Work
Wireless medical microsensors are usually with two different operating modes:
Low-Power Mode and Performance Mode because the well-known signals of the main characteristics of cardiac activity, e.g. heart rate and ECG, are at a very low rate.
More than 99% operating time of sensor nodes are operating in low-power mode to record various physiological signals throughout its life time while only less than 1%
operating time in performance mode to process and transmit real-time informative cardiovascular parameters to a host. This low-power-mode-dominated scenario is capable of further reducing total energy consumption if dynamic voltage frequency scaling (DVFS) technique is applied. The benefit of DVFS technique is attributed to the quadratic savings in active CVDD2f power.
The proposed programmable clock generator is used for dynamic voltage frequency scaling system which is operated in sub/near-threshold region. Figure 6.1 shows the sub/near-threshold DVFS system, it is composed of two switched-capacitor (SC) DC-DC converters, decoupling capacitors (DeCaps), the proposed clock generator, level shifters (LS), DVFS controller, PVT sensors, supply switch, and near/sub-threshold 8T SRAM-based FIFO. The clock generator is equipped with two frequency dividers, thereby able to output two multiplied clock. CLK_r is for the read clock, and CLC_w is for write clock in FIFO.
In Performance Mode, heart rate information is transmitted to a host. The supply voltage of FIFO is switched to VddH for high performance operation, and CLK_w and CLK_r are scaled up to a frequency that the function error will not happen according to PVT conditions sensed by PVT sensors. The PVT sensors were
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Performance Mode, the sub/near-threshold dynamic frequency voltage scaling system can save large power.
Figure 6.1 Sub/near-threshold DVFS system
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Vita
謝忠穎 Chung-Ying Hsieh
PERSONAL INFORMATION
Birth Date: May 27, 1986
Birth Place: Changhua, TAIWAN
E-Mail Address: johnny.ee97g@g2.nctu.edu.tw
EDUCATION
09/2008 – 07/2010 M.S. in Electronics Engineering, National Chiao Tung University Thesis: PVT-Robust ULV Clock System Design for
Sub/Near-Threshold Green Technologies
09/2004 – 06/2008 B.S. in Engineering Science, National Cheng Kung University
PUBLICATIONS
Chung-Ying Hsieh, Ming-Hung Chang, Shang-Yuan Lin, and Wei Hwang, “Logical Effort Models with Voltage and Temperature Extensions in Super-/Near-/Sub-threshold Regions” IEEE Asia Pacific Conference Circuits and Systems, May. 2010. (Submitted)
PATENTS
Chung-Ying Hsieh, Ming-Hung Chang, and Wei Hwang, “A thermally robust buffered clock tree using logical effort compensation” US/TW Patent Pending (submitted) Chung-Ying Hsieh, Ming-Hung Chang, and Wei Hwang, “A programmable clock generator for sub- and near-threshold DVFS system” US/TW Patent Pending (submitted)