Chapter 6 Conclusions and Future Work
6.2 Future Work
Wireless medical microsensors are usually with two different operating modes:
Low-Power Mode and Performance Mode because the well-known signals of the main characteristics of cardiac activity, e.g. heart rate and ECG, are at a very low rate.
More than 99% operating time of sensor nodes are operating in low-power mode to record various physiological signals throughout its life time while only less than 1%
operating time in performance mode to process and transmit real-time informative cardiovascular parameters to a host. This low-power-mode-dominated scenario is capable of further reducing total energy consumption if dynamic voltage frequency scaling (DVFS) technique is applied. The benefit of DVFS technique is attributed to the quadratic savings in active CVDD2f power.
The proposed programmable clock generator is used for dynamic voltage frequency scaling system which is operated in sub/near-threshold region. Figure 6.1 shows the sub/near-threshold DVFS system, it is composed of two switched-capacitor (SC) DC-DC converters, decoupling capacitors (DeCaps), the proposed clock generator, level shifters (LS), DVFS controller, PVT sensors, supply switch, and near/sub-threshold 8T SRAM-based FIFO. The clock generator is equipped with two frequency dividers, thereby able to output two multiplied clock. CLK_r is for the read clock, and CLC_w is for write clock in FIFO.
In Performance Mode, heart rate information is transmitted to a host. The supply voltage of FIFO is switched to VddH for high performance operation, and CLK_w and CLK_r are scaled up to a frequency that the function error will not happen according to PVT conditions sensed by PVT sensors. The PVT sensors were
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Performance Mode, the sub/near-threshold dynamic frequency voltage scaling system can save large power.
Figure 6.1 Sub/near-threshold DVFS system
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Vita
謝忠穎 Chung-Ying Hsieh
PERSONAL INFORMATION
Birth Date: May 27, 1986
Birth Place: Changhua, TAIWAN
E-Mail Address: johnny.ee97g@g2.nctu.edu.tw
EDUCATION
09/2008 – 07/2010 M.S. in Electronics Engineering, National Chiao Tung University Thesis: PVT-Robust ULV Clock System Design for
Sub/Near-Threshold Green Technologies
09/2004 – 06/2008 B.S. in Engineering Science, National Cheng Kung University
PUBLICATIONS
Chung-Ying Hsieh, Ming-Hung Chang, Shang-Yuan Lin, and Wei Hwang, “Logical Effort Models with Voltage and Temperature Extensions in Super-/Near-/Sub-threshold Regions” IEEE Asia Pacific Conference Circuits and Systems, May. 2010. (Submitted)
PATENTS
Chung-Ying Hsieh, Ming-Hung Chang, and Wei Hwang, “A thermally robust buffered clock tree using logical effort compensation” US/TW Patent Pending (submitted) Chung-Ying Hsieh, Ming-Hung Chang, and Wei Hwang, “A programmable clock generator for sub- and near-threshold DVFS system” US/TW Patent Pending (submitted)