Design Metrics Evaluation

For evaluation of ME designs, there are several important design metrics under consid-eration. For ME algorithm development, the design metrics for evaluation are: (1) number of operations, (2) quality of the algorithm in terms of PSNR, (3) memory access bandwidth [33]. However, to evaluate an ME hardware architecture, there are 6 major design metrics for consideration as follows [33].

• Quality (Q): The quality metric is to evaluate the motion search performance be-tween full search (FS) and fast ME (FME) algorithm. The FME algorithms reduce

18 Chapter 2: Review of Power Constrained Motion Estimation Designs

Figure 2.1: Block motion estimation.

Chapter 2: Review of Power Constrained Motion Estimation Designs 19

the computation complexity by search candidates reduction or matching criterion simplification, etc. However, it suffers quality loss due to the complexity reduction for poor search performance. The quality loss is usually measured by Peak Signal Noise Ratio (PSNR) denoted as

where I_C is the current frame,I^b_C(m, n) is the reconstructed image of current frame, N_h and N_v are the frame width and height. Thus, to have a fair comparison of different ME algorithms or hardware architectures, the quality metric (Q) is defined as the PSNR difference between FS and FME denoted as

Quality Metric (Q) = P SNR_FME− P SNR_FS (dB). (2.4)

To apply this metric for fair design evaluations in later sections, the PSNR is mea-sured under search range of [-16, +15].

• Throughput (T): The throughput metric is to measure the processing speed of the hardware architecture to see if it can meet the real-time requirement. To quantify the processing speed, the throughput metric is defined as the required number of cycles for one macroblock (MB) of block matching denoted as

Throughput Metric (T) = NCMB(cycles) (2.5)

, where NCMB represents the required cycles for one MB of block matching. Al-though the throughput is application dependent, and there is no need to over-design the hardware, the throughput metric is still an important parameter to measure the

20 Chapter 2: Review of Power Constrained Motion Estimation Designs

hardware design performance. The more cycles the design takes to meet the real-time requirement, the slower the processing speed. If the processing speed is too slow, the applications are limited to those devices target on processing low resolution of video sequences. To apply this metric for fair design evaluations in later sections, the throughput is measured in the number of clock cycles under search range of [-16, +15].

• Silicon area (A): The chip size is determined by the hardware silicon area and the VLSI technology. That means the chip size is not available until the chip is really designed. However, we can have a more efficient way to estimate the silicon area on the architectural level by measuring the equivalent gate counts for ME designs.

The gate counts includes the number of logic gates for memories and design logics denoted as

Area Metric (A) = A_Memory+ A_Logic. (2.6) , where AMemory is the silicon area for memory including Synchronous Random Ac-cess Memory (SARM) and/or register files, and ALogic is the silicon area for all the ME hardware logics except memories. In this thesis, we will use gate counts as the silicon area for the evaluation of the ME designs.

• Hardware Utilization (U): Hardware utilization or hardware efficiency [33] is to evaluate the hardware utilization ratio in percentage by calculating the active cycles and idle cycles in designs. This metric can also be used to evaluate the design over-heads. The higher the utilization ratio, the lower the overheads in the ME hardware designs. That means a design is a highly efficient design if its hardware utilization ratio is high.

Chapter 2: Review of Power Constrained Motion Estimation Designs 21

Utilization Metric (U) = NC_MB(Active)

NCMB(Active) + NCMB(Idle) = NC_MB(Active) NCMB

(%).

(2.7)

• I/O Bandwidth (B): The I/O bandwidth is to evaluate the amount of data transmis-sion between off-chip memories and ME processing core. Since most of the ME designs put frame buffers in off-chip memories, the access to the off-chip memories is unavoidable. Thus, the I/O bandwidth will directly affect the design throughput and hardware utilization ratio. If the bandwidth requirement is high, the ME design will take longer cycles in waiting data before the motion search begins. This will lead to poor throughput and poor hardware utilization since there are many hardware idle cycles existed. In this thesis, the metric for I/O bandwidth evaluation is defined as the number of read cycles and write cycles from off-chip memories denoted as

Bandwidth Metric (B_I/O) = NC_read+ NC_write(bytes) (2.8) , where NC_read and NC_write are read and write cycles respectively. The unit is the number of bytes required for the bus access under the search range of [-16, +15].

• Power consumption (P): Power consumption is the most critical issue in ME de-signs, and power constrained designs have wider applications in mobile or portable devices. To evaluate ME designs, the power consumption metric is defined as the total power consumption for memory and hardware logics and is denoted as

Power Consumption Metric (P) = P_Memory+ P_Logic(mW). (2.9) , where PMemoryis the power consumption for memory, and PLogicis the power con-sumption for the ME hardware logics. In this thesis, the ME designs is evaluated

22 Chapter 2: Review of Power Constrained Motion Estimation Designs

using this power consumption metric with the unit of milli-watt (mW). To provide a fair comparison basis, we use the normalized power consumption [26] by mapping the original power consumption to the equivalent power consumption for 0.18 µm denoted as

NormalizedPower Consumption Metric (P_nom) = P × 0.18²

Process² × 1.8² Voltage².

(2.10)