E. Evaluation on Power-Distortion Performance
5.2 Future Work
The future work is to extend the proposed low power and power adaptive ME designs to Scalable Video Coding (SVC) standard [68]. The SVC standard is developed based on H.264/AVC standard[55], but has 2 major features of temporal and spatial scalability for video streaming applications.
The temporal scalability is to allow scalability in temporal domain to change the frame rates, and this feature is constructed based on Motion Compensated Temporal Filtering (MCTF) and Hierarchical B-Pictures approaches. To extend our work to support temporal scalability, the proposed binary motion search architecture can benefit from this scalability feature due to the data for block matching are in binary format. Hence, both the complexity and bus bandwidth are able to be reduced. However, the video quality may be an issue due to the long distance search using binary format may lead to imprecise prediction and poor motion compensated performance.
The spatial scalability is to allow scalability in spatial domain to support different video resolutions in single bitstream. The challenge is to improve the prediction performance from low to high or high to low resolutions with another exhaustive search for power sav-ings. To extend our work to support spatial scalability, the proposed binary motion search architecture can benefit from this scalability feature due to the data for block matching are in binary format. Hence, both the complexity and bus bandwidth are able to be reduced.
However, similar problems in the video quality may be an issue due to the downsampling process cause the aliasing for binary image to find less imprecise prediction as compared to the conventional 8-bit search.
Therefore, our next step is to study the relationship for motion vectors from temporal
Chapter 5: Conclusions and Future Work 129
and spatial scalability, and propos the new algorithm and architecture to support both the features.
Bibliography
[1] N. Chaddha, and T. H. Y. Meng, “A low-power video decoder with power, memory, bandwidth and quality scalability,” in IEEE workshop on VLSI signal processing, pp.
451-460, Oct. 1995.
[2] J. Jung, and A. Bourge, “Power-scalable video encoder for mobile devices based on collocated motion estimation,” Proceedings of SPIE, 2004.
[3] L. Lu, and V. Sheinin, “Rate and decoding power constrained video coding scheme for mobile multimedia players,” in Proc. IEEE ICIP, pp. 2861-2864, Oct. 2004.
[4] Y. Liang, Z. He, and I. Ahmad, “Analysis and design of power constrained video en-coder,” in Proc. IEEE 6th CAS Symp. on Emerging Technologies: Mobile and Wireless Comm., pp. 57-60, May 2004.
[5] C.-J. Lian, S.-Y. Chien, P.-C. Tseng, L.-G. Chen, “Power aware multimedia: concepts and design perspectives,” IEEE Circuits and Systems Magazine, pp. 26-34, April-June 2007.
[6] M. Mizuno, et al., “A 1.5-W Single-Chip MPEG-2 MP@ML Video Encoder with Low Power Motion Estimation and Clocking,” IEEE J. Solid State Circuits, vol. 32, pp. 1807-1816, Nov. 1997.
[7] S. Kumaki, et al., “A 99-mm2 0.7-W Single-Chip MPEG-2 422P@ML Video, Au-dio, and System Encoder With a 64-Mb Embedded DRAM for Portable 422P@HL Encoder System,” IEEE J. Solid State Circuits, vol. 37, pp. 450-454, March 2002.
[8] Y.-W. Huang, et al., “A 1.3 TOPS H.264/AVC single chip encoder for HDTV appli-cations,” Proc. ISSCC, pp. 128-129, 2005.
[9] Fujitsu. http://www.fujitsu.com/downloads/PR/2007/20070521-01a.pdf [10] Zoran Coach 10. http://www.zoran.com/IMG/pdf/COACH 10.pdf [11] Sanyo. http://www.sanyo.co.jp/koho/hypertext4-eng/0708/0830-1e.html [12] TI. http://focus.ti.com/docs/toolsw/folders/print/tmdh264e.html
130
Bibliography 131
[13] http://shdesigns.org/batts/battcyc.html
[14] TI DaVinci. http://focus.ti.com/docs/solution/folders/print/267.html
[15] Power management of TI DaVinci. http://focus.ti.com/docs/pr/pressrelease.jhtml?prelId=sc06194 [16] J.-C. Tuan, T.-S. Chang, and C.-W. Jen, “On the data reuse and memory bandwidth
analysis for full search block matching VLSI architecture,” IEEE Trans. Circuits and Systems for Video Technique, vol. 12, pp. 61-72, Jan. 2002.
[17] E. Brockmeyer, et al, “Low power memory storage and transfer organization for the MPEG-4 full pel motion estimation on a multimedia processor,” IEEE Trans. on Mul-timedia, vol. 1, pp. 202-216, June 1999.
[18] M. Takahashi, et al., “A 60-MHz 240-mW MPEG-4 Videophone LSI with 16-Mb Embedded DRAM,” IEEE J. Solid State Circuits, vol. 35, pp. 1713-1721, Nov. 2000.
[19] M. Mizuno, et al., “A 1.5-W Single-Chip MPEG-2 MP@ML Video Encoder with Low Power Motion Estimation and Clocking,” IEEE J. Solid State Circuits, vol. 32, pp. 1807-1816, Nov. 1997.
[20] F. Mombers, et al., “Image: A low cost, low power video processor for high quality motion estimation in MPEG-2 encoding,” IEEE J. Solid State Circuits, vol. 44, pp.
774-783, August 1998.
[21] W. Badawy, and M. A. Bayoumi, “A low power VLSI architecture for mesh-based video motion tracking,” IEEE Trans. Circuits and Systems II-Analog and Digital Sig-nal Processing, vol. 49, pp. 488-504, July 2002.
[22] Y. Hamamato, et al., “A low-power single-chip MPEG2 (Half-D1) video codec LSI for portable consumer product applications,” IEEE Trans. Consumer Electronics, vol.
45, pp. 496-500, August 1999.
[23] V. L. Do, and K. Y. Yun, “A low-power VLSI architecture for full-search block-matching motion estimation,” IEEE Trans. Circuits and Systems for Video Technol-ogy, vol. 8, pp. 393-398, August 1998.
[24] Y. Yatabe, et al., “An MPEG2/4 dual codec with sharing motion estimation,” IEEE Trans. Consumer Electronics, vol. 51, pp. 660-664, May 2005.
[25] S. Saponara, and L. Fanucci, “Data-adaptive motion estimation algorithm and VLSI architecture design for low-power video systems,” IEE Proc. Comput. Digit. Tech., vol. 151, Jan. 2004.
[26] T.-C. Chen, et al., “Fast algorithm and architecture design of low-power integer mo-tion estimamo-tion for H.264/AVC” IEEE Trans. Circuits and Systems for Video Technol-ogy, vol. 17, pp. 568-577, May 2007.
132 Bibliography
[27] S. Kawahito, et al., “Low-power motion vector estimation using iterative search block-matching methods and a high-speed non-destructive CMOS image sensor,”
IEEE Trans. Circuits and Systems for Video Technology, vol. 12, pp. 1084-1092, Dec.
2002.
[28] M. Jiang et al., “Low-power systolic array processor architecture for FSBM video motion estimation,” IEE Electronics Letters, vol. 42, Sep. 2006.
[29] R. Gao, D. Xu, and J. P. Bentley, “Reconfigurable hardware implementation of an im-proved parallel architecture for MPEG-4 motion estimation in mobile applications,”
IEEE Trans. Consumer Electronics, vol. 49, pp. 1383-1390, May 2003.
[30] W.-M. Chao, et al., “A novel hybrid motion estimator supporting diamond search and fast full search,” in Proc. IEEE ISCAS, May 2002.
[31] “ISO/IEC 14496-5:2001 Final Committee Draft, “MPEG01/N4025.
[32] “Video coding for low bit rate communication, “ITU-T Rec. H.263, 1998.
[33] P. Kuhn, “Complexity analysis and VLSI architectures for MPEG-4 motion estima-tion,” Boston, MA, Kluwer, 1999.
[34] M. M. Mizuki, U. Y. Desai, I. Masaki, and A. Chandrakasan, “A binary block match-ing architecture with reduced power consumption and silicon area requirement,” in Proc. IEEE ICASSP, pp. 3248-3251, May 1996.
[35] S.-H. Wang, et al., “Platform based design of all binary motion estimation with bus interleaved architecture,” in Proc. IEEE Int. Symposium on VLSI-DAT, pp. 241-244, April 2005.
[36] M. Miyama, et al., “A sub-mW MPEG-4 motion estimation processor core for mobile video application,” IEEE J. Solid State Circuits, vol. 39, pp. 1562-1570, Dec. 2004.
[37] Y.-W. Huang, S.-Y Chien, B.-Y. Hsieh, and L.-G. Chen, “Global elimination algo-rithm and architecture design for fast block matching motion estimation,” IEEE Trans.
Circuits and Systems for Video Technology, vol. 14, pp. 898-907, June 2004.
[38] H.-M. Jong, L.-G. Chen, T.-D. Chiueh, “Parallel architectures for 3-step hierarchi-cal search block-matching algorithm,” IEEE Trans. Circuits and Systems for Video Technology, vol. 4, pp. 407-416. Aug. 1994.
[39] J. -F. Shen, T.-C. Wang and L.-G. Chen, “A novel low power full search block match-ing motion estimation design for H.263+,” IEEE Trans. Circuits and Systems for Video Technology, vol. 11, pp. 890-897, July 2001.
Bibliography 133
[40] S. Y. Yap and J. V. McCanny, “A VLSI architecture for variable block size video motion estimation,” IEEE Trans. Circuits and Systems II: Express Briefs, vol. 51, no.
7, pp. 384-349, July 2004.
[41] J.-H. Luo, C.-N. Wang, and T. Chiang, “A novel all-binary motion estimation (ABME) with optimized hardware architectures,” IEEE Trans. Circuits and Systems for Video Technology, vol.12, no. 8, pp. 700-712, Aug. 2002.
[42] C. D. Vleeschouwer, T. Nilsson, K. Denolf, and J. Bormans, “Algorithmic and archi-tectural co-design of a motion-estimation engine for low power video devices,” IEEE Trans. Circuits and Systems for Video Technology, vol.12, no. 12, pp. 1093-1105, Dec.
2002.
[43] B.-C. Song, and K.-W. Chun, ”Multi-resolution block matching algorithm and its VLSI architecture for fast motion estimation in an MPEG-2 video encoder,” IEEE Trans. Circuits and Systems for Video Technology, vol. 14, pp 1119-1137, Sep. 2004.
[44] W. Burleson, P. Jain, and S. Venkatraman, “Dynamically parameterized algorithms and architectures to exploit signal variations for improved performance and reduced power,” IEEE International Conf. on Acoustics, Speech, and Signal Processing, pp.
901-904, 2001.
[45] S. Mietens, P. H. N. de With, and C. Hentschel, “Computational-complexity adaptive motion estimation for mobile MPEG encoding,” IEEE Trans. Consumer Electronics, vol. 50, pp. 281-291, Feb. 2004.
[46] S. -Y. Huang, C.-Y. Cho, and J.-S. Wang, “Adaptive fast block matching algorithm by switching patterns for sequences with wide range motion content,” IEEE Trans.
on Circuits and Systems for Video Technology, vol. 15, no. 11, pp. 1373-1384, Nov.
2005.
[47] S. -S. Lin, P. C. Tseng, C. P. Lin, and L. G. Chen, “Multi-mode content-adaptive motion estimation algorithm for power-adaptive video coding systems,” Proc. IEEE Workshop on Signal Processing Systems, pp. 239-244, 2004.
[48] T. Li, S. Li and C. Shen, “A novel configurable motion estimation architecture for high efficiency MPEG-4/H.264 encoding,” Proc. IEEE ASP-DAC, pp. 1364-1367, 2005.
[49] Y. Wang, Y. Wang, and H. Kuroda, “A globally adaptive pixel decimation algorithm for block motion estimation,” IEEE Trans. Circuits and Systems for Video Technology, vol. 10, no. 6, pp 1006-1011, Sep. 2000.
[50] V. G. Moshnyaga, “A new computational adaptive formulation of block matching motion estimation,” IEEE Trans. Circuits and Systems for Video Technology, vol. 11, no. 1, pp 118-124, Jan. 2001.
134 Bibliography
[51] S.-H. Wang, C. N. Wang, and T. Chiang, “A complexity adaptive variable-bit-depth motion estimation,” Proc. IEEE International Conf. on Consumer Electronics, pp.
233-234, 2005.
[52] A. Takagi, K. Nishikawa, and H. Kiya, “Low-bit motion estimation with edge en-hanced images for low power MPEG encoder,” Proc. IEEE International Symposium on Circuits and Systems, pp. 505-508, 2001.
[53] A. M. Tourapis, O. C. Ou, M. L. Liou, C. W. Bay, and H. K Kowloon, “Predictive mo-tion vector field adaptive search technique (PMVFAST) - enhancing block matching motion estimation,” Proc. International Conf. on Visual Communication and Image Processing, pp. 883-892, 2001.
[54] A. M. Tourapis, “Enhanced predictive zonal search for single and multiple frame motion estimation,” Proc. International Conf. on Visual Communication and Image Processing, pp. 1069-1079, 2002.
[55] “Draft of version 4 of ISO/IEC 14496-10,” ISO/IEC JTC1/SC29/WG11, MPEG05/N7081, April 2005.
[56] H.-W. Cheng and L.-R. Dung, “A content based methodology for power adaptive motion estimation architecture,” IEEE Trans. Circuits and Systems II-Express Briefs, vol. 52, pp. 631-635, Oct. 2005.
[57] Z.-L. He, C.-Y. Tsui, K.-K. Chan, and M.-L. Liou, “Low-power VLSI design for motion estimation using adaptive pixel truncation,” IEEE Trans. Circuits and Systems for Video Technology, vol. 10, pp 669-678, Aug. 2000.
[58] A. Takagi, S. Muramatsu, and H. Kiya, “Motion estimation with power adaptation and its VHDL model,” Proc. IEEE ICIP, pp. 118-121, 2000.
[59] M. Pedram and J.M. Rabaey, “Power aware design methodologies,” Kluwer Aca-demic Publishers, 2002.
[60] B. Natarajan, V. Bhaskaran, and K. Konstantinides, “Low-complexity block-based motion estimation via one-Bit transforms,” IEEE Trans. Circuits and Systems for Video Technology, vol. 7, no. 4, pp 702-706, Aug. 1997.
[61] P. H. W. Hong and O. C. Au, “Modified one-bit transform for motion estimation,”
IEEE Trans. Circuits and Systems for Video Technology, vol. 9, pp.1020-1024, Oct.
1999.
[62] X. Lee and Y.-Q. Zhang, “A fast hierarchical motion-compensation scheme for video coding using block feature matching,” IEEE Trans. Circuits and Systems for Video Technology, vol. 6, pp. 627-635, Dec. 1996.
Bibliography 135
[63] X. Song, T. Chiang, X. Lee, and Y.-Q. Zhang, “New fast binary pyramid motion estimation for MPEG2 and HDTV encoding,” IEEE Trans. Circuits and Systems for Video Technology, vol. 10, pp. 1015-1028, Oct. 2000.
[64] G. Magklis et al., ”Dynamic frequency and voltage scaling for a multi-clock-domain microprocessor,” IEEE Micro, vol. 23, pp. 62-68, Nov. 2003.
[65] J. H. Lee, and N. S. Lee, “Variable block size motion estimation algorithm and its hardware architecture for H.264/AVC,” Proc. IEEE International Symposium on Cir-cuits and Systems, pp. 741-744, 2004.
[66] C. Y. Chen, et al., “Analysis and architecture design of variable block size motion estimation for H.264/AVC,” IEEE Trans. Circuits and Systems I - Regular papers, vol. 53, pp. 578-593, March 2006.
[67] C.-M. Ou, C.-F. Lee, and W.-J. Hwang, “An efficient VLSI architecture for H.264 variable block size motion estimation,” IEEE Trans. Consumer Electronics, vol. 51, pp. 1291-1299, Nov. 2005.
[68] J.-R. Ohm, “Advances in scalable video coding,” Proceedings of the IEEE, vol. 93, no. 1, pp. 42-56, Jan. 2006.
[69] M. Bhardwaj, R. Min, and A. Chandrakasan, “Power-aware systems,” Proc. IEEE 34th asilomar conference on signals, systems and computers, pp. 1695-1701, Oct.
2000.
[70] L. Mazzoni, “Power-aware design for embedded systems,” IEE electronics systems and software, pp. 12-17, Oct. 2003.
[71] Z. He, et al., “Power-rate-distortion analysis for wireless video communication under energy constraints,” IEEE Trans. Circuits and Systems for Video Technology, vol. 15, no. 5, pp 645-658, May 2005.
Shih-Hao Wang
Contact
Information Engineering Building IV - 529R Voice: 03-5712121-54228 Institute of Electronics Fax: 03-5731791
National Chiao Tung University E-mail: shwang.ee90g@nctu.edu.tw Hsinchu, Taiwan 30010 R.O.C. WWW: cwww.ee.nctu.edu.tw/~vdo90843
Research Interests
Video Compression, Video Signal Processing, VLSI Design on Multimedia
Education National Chiao Tung University, Hsinchu, Taiwan ROC Ph.D., Institute of Electronics, September 2007
• Dissertation: “Algorithm and Architecture Design of Motion Estimation for Power Con-strained Video Coding Systems”
• Advisor: Tihao Chiang
M.S., Electrical and Control Engineering, June 2001
• Thesis: “Wavelet Tree Based Watermarking for Copyright Protection”
• Advisor: Yuan-Pei Lin
National Tsing Hua University, Hsinchu, Taiwan ROC B.S., Power Mechanical Engineering, June, 1999
• Ranked 2nd in class
Tainan First Senior High School, Tainan, Taiwan ROC Ranked 1st in class & 5th in that grade
Honors and Awards
Nomination in Marquis Who’s Who in Asia, 2007.
Outstanding Ph.D. student scholarship, 2004. (awarded by EE, NCTU) Academic achievement award and scholarship, 1996.
Academic Experience
National Chiao Tung University, Hsinchu, Taiwan ROC
Ph.D. candidate Sep. 2002 - Sep. 2007
Algorithm and architecture design of motion estimation
• Low power bi-directional binary motion estimation architecture.
• Power aware motion estimation design using configurable iterative binary searches.
Video transcoding
• A FGS multi-layers to single layer transcoder.
• A unified MPEG-4 FGS to MPEG-1/2/4 single layer transcoder.
H.264 decoder system
• A FPGA prototyping solution (ARM based platform).
• A novel software-hardware co-design architecture (QCIF 10fps real-time decoding).
MPEG-4 codec system
• TI DSP based video codec solution.
• A codec system with on-line (not real-time) MPEG-4 encoder/decoder system from video cap-turing to TV display.
Digital watermarking
• A robust and blind digital watermarking technique based on wavelet characteristics for secure information embedding.
• Journal publication in IEEE Trans. on Image Processing.
Teaching Assistant Sep. 1999 - Sep. 2003
Introduction to Digital Signal Processing (1999 Fall) Digital Signal Processing (2000 Fall)
Digital Compression (2001 Spring) Multimedia Communication (2003 Spring)
Professional Experience
Ambarella Taiwan Ltd., Hsinchu, Taiwan.
Member of Technical Staff June, 2004 - Present
H.264 algorithm development & Firmware programming.
Part-time Engineer Oct., 2003 - June, 2004
H.264 algorithm development.
Computer Skills • IC CAD Tools: Verilog, Design Compiler, SOC Encounter, Prime POwer, etc.
• FPGA CAD Tools: Xilinx ISE, Quartus, Synplify, etc.
• Languages: C/C++, Matlab, etc.
著作目錄
z 期刊論文
1. S.-H. Wang, W.-H. Peng, Y.-W. He, G.-Y. Lin, C.-Y. Lin, S.-C. Chang, C.-N.
Wang, and T. Chiang, “A software-hardware co-implementation of MPEG-4 advanced video coding decoder with block level pipelining,” Journal of VLSI Signal Processing Systems, vol. 41, no. 1, pp. 93-110, Jan. 2005.
2. S.-H. Wang, W.-L. Chen, and Tihao Chiang, “An efficient FGS to MPEG-1/2/4 single layer transcoder with R-D optimized multi-layer streaming technique for video quality improvement,” Journal of the Chinese Institute of Engineers, vol. 30, no.6, pp. 1059-1070, 2007.
3. S.-C. Chang, W.-H. Peng, S.-H. Wang, and T. Chiang, “A Platform based Bus-interleaved Architecture for Deblocking Filter in H.264/MPEG-4 AVC,”
IEEE Trans. Consumer Electronics, vol. 51, no. 1, pp. 249-255, Feb. 2005.
4. S.-H. Wang, and Y.-P. Lin, “Wavelet tree quantization for copyright protection watermarking,” IEEE Trans. Image Processing, vol. 13, no. 2, pp. 154-165, Feb.
2004.
z 審查中期刊論文
1. S.-H. Wang, and T. Chiang, “A power adaptive motion estimation IP core design using iterative binary search,” IEEE Trans. Circuit and System for Video Technology, 2006.
2. S.-H. Wang, S. -H. Tai, and T. Chiang, “A low power and bandwidth efficient motion estimation IP core design using binary search,” IEEE Trans. Circuit and System for Video Technology, 2006.
z 國際會議論文
1. S.-H. Wang, W.-H. Peng, Y. He, G.-Y. Lin, C.-Y. Lin, S.-C. Chang, C.-N. Wang, and T. Chiang, “A Platform Based MPEG-4 Advanced Video Coding Decoder with Block Level Pipelining,” Proc. IEEE ICICS-PCM, Singapore, Nov. 2003.
2. S.-H. Wang, W.-L. Tao, W.-H. Peng, C.-N. Wang, and T. Chiang, “Platform based design of all binary motion estimation (ABME) with bus interleaved architecture,” Proc. IEEE International Symposium on VLSI Technology, System and Applications, Hsinchu, April 2005.
3. S.-H. Wang, C.-N. Wang, and T. Chiang, “A complexity aware variable-bit-depth motion estimation,” Proc. IEEE International Conference on Consumer Electronics, Las Vegas, Jan. 2005.
4. S.-C. Chang, W.-H. Peng, S.-H. Wang, and T. Chiang, “A platform-based de-blocking filter design with bus interleaved architecture for H.264,” Proc. IEEE International Conference on Consumer Electronics, Las Vegas, Jan. 2005.
5. S.-H. Wang, and Y.-P. Lin, “Blind watermarking using wavelet tree quantization,”
Proc. IEEE International Conference on Multimedia and Expo, Lausanne, August, 2002.
z MPEG 視訊標準會議文件
1. S.-H. Wang, C.-N. Wang, Yi-Shin Tung, T. Chiang, and H. Sun, “ISO/IEC JTC1/SC 29/WG 11 M9951: AHG report on editorial convergence of MPEG-4 reference software,” Oct. 2003.
2. S.-H. Wang, C.-N. Wang, Y.-S. Tung, T. Chiang, and H. Sun, “ISO/IEC JTC1/SC 29/WG 11 M9632: AHG report on editorial convergence of MPEG-4 reference software,” July 2003.
3. S.-H. Wang, C.-N. Wang, Y.-S. Tung, T. Chiang, and H. Sun, “ISO/IEC JTC1/SC 29/WG 11 M9355: AHG report on editorial convergence of MPEG-4 reference software,” March 2003.
4. S.-H. Wang, C.-N. Wang, G.-Y. Lin, T. Chiang, and H. Sun, “ISO/IEC JTC1/SC 29/WG 11 M9073: AHG report on editorial convergence of MPEG-4 reference software,” Dec. 2002.
5. S.-H. Wang, C.-N. Wang, T. Chiang, and H. Sun, “ISO/IEC JTC1/SC 29/WG 11 M8886: Proposed text of proposed draft technical reports of ISO/IEC PDTR 14496-7 for optimized simple profile reference software, ” Oct. 2002.
6. S.-H. Wang, C.-N. Wang, T. Chiang, and H. Sun, “ISO/IEC JTC1/SC 29/WG 11 M8884: AHG report on editorial convergence of MPEG-4 reference software,” Oct.
2002.
7. S.-H. Wang, C.-N. Wang, Tihao Chiang, and H.F. Sun, “ISO/IEC JTC1/SC 29/WG 11 M8603: AHG report on editorial convergence of MPEG-4 reference software,”
July 2002.
8. S.-H. Wang, Y.-C. Lin, C.-N. Wang, T. Chiang, and H. Sun, “ISO/IEC JTC1/SC 29/WG 11 M8408: AHG report on editorial convergence of MPEG-4 reference software,” May 2002.
9. S.-H. Wang, C.-N. Wang, T. Chiang, and H. Sun, “ISO/IEC JTC1/SC 29/WG 11 M8041: AHG report on editorial convergence of MPEG-4 reference software,”
March 2002.
z
專利
1. M.-Y. Huang, T.-L. Su, S.-H. Wang, C.-N. Wang and T. Chiang, “MPEG-4 streaming system with adaptive error concealment,” 美 國 專 利 ， 專 利 號 20060104366.
z 審查中專利
1. S.-H. Wang, L. Kohn, and T. Chiang, “Mode decision using approximate 1/2 pel interpolation,” 美國專利. (Filed on Nov. 23, 2005).
2. S.-C. Chang, W.-H. Peng, S.-H. Wang, and T. Chiang, “A Platform Based Bus-interleaved Architecture for Deblocking Filter in H.264/MPEG-4 AVC,” 美 國專利. (Filed on March 24, 2005)