Detail placement and routing design

When we select a non-placed node u and a node set V= {vi | vi have been placed on reconfigurable hardware and have edge from or to u}, first we can classify u according to whether u is an I/O node that means u needs to transfer data with CPU or memory. Because we have two different assumptions for I/O node placement, classification of u is necessary.

Further we can classify V according to the number of elements in V. When u is not an I/O node, we describe in CASE I. When u is an I/O node, it is described in CASE II. And classification of V will be both described in CASE I and CASE II.

CASE I: u is a non-I/O node

We describe different methods for different classifications of node set V according to its number of elements as follows. CASE I.1 describes the situation of one element in node set V, and CASE I.2 describes that of more than one element in node set V.

CASE I.1: Only one element in node set V={v}, v’s position on reconfigurable hardware is the source of the routing path for (u,v).

For the fewer tracks added, the fewer wiring area added, and for saving routing time, we will

fewer added tracks, routing paths with more added tracks would not be found out. Because routing paths with fewer routing requirement have been found, it is unnecessary to find routing paths with more routing requirement. The follow four steps are detail method for CASE I.1 to route (u,v) and to place u on reconfigurable hardware.

Step I.1.1: no track added

Use maze routing as mentioned in section 2.3.1, limit no track can be added, and routing should be stop in the first empty logic block. In the process, find all possible routing paths, and the end of any one routing path must be an empty logic block for u to be a possible position.

Step I.1.2: If no routing path found in Step1.1, add one track

Use maze routing, limit only one track can be added, and stop in the first empty logic block. In the process, find all possible routing paths, and the end of any one routing path must be an empty logic block for u to be a possible position.

Step I.1.3: If no routing path selected in Step1.1 and Step1.2, add two tracks

Use maze routing, allow two tracks can be added, and stop in the first empty logic block. In this step, to add two tracks to find all possible routing paths is the worst case, because a vertical track and a horizontal track would lead a source of a routing path to any destination. In the process, find all possible routing paths, and the end of any one routing path must be an empty logic block for u to be a possible position.

Step I.1.4: Place u

For the end of the selected routing path, the upper empty logic block has higher priority than the empty lower logic block, and the left empty logic block have higher priority than the right empty logic block. Select the highest priority empty logic block to place u.

CASE I.2: Multiple elements in node set V={v_i| vi have been placed on reconfigurable hardware and have edge from or to u}, and apply e_i=(u,v_i).

In this case, there exists more than one source must reach the same destination. In the other word, more than one edge must be assigned its suitable routing path that make u have a unique position and the wiring area added fewest in this case. If every e_i is assigned a routing path with the minimal routing requirement, there may exist many positions for u. We continue to use method in CASE I.1, but route to the farthest possible empty logic blocks to give more routing paths for every e_i. From these routing paths, select suitable routing path for every e_i to find the unique position to place u. The follow steps are detail method for CASE I.2 to route every (u,v_i) and to place u on reconfigurable hardware.Step I.2.1: Route every e_i base on the

routing method in the CASE I.1, but the farthest possible empty logic blocks is the routing end. Every empty logic block in the scope of possible routing paths would be put in candidate set_i

Step I.2.2: find the intersection set of candidate sets CASE I.2.1: the intersection is not empty

In the intersection set, select the logic block, which have the shortest distance with every v_i to place u.

CASE I.2.2: the intersection is empty

Step I.2.2.1: Find the logic block (lb₁) that exists at most candidate sets, and apply . Then try to place u at lb1 and route e

i 1

1 candidateset ~candidateset

lb ∈ _i+1 ~ e_n.

Step I.2.2.2: On reconfigurable hardware, find the logic block (lb2) which have the shortest distance with every v_i . Then try to place u at lb2, and route every e I

Step I.2.2.3: compare the routing requirements of step I.1.2.1and step I.2.2.2 if routing requirement of step I.1.2.1 < routing requirement of step I.2.2.2 then place u at lb1

CASE II: u is an I/O node

In hardware assumption, we have two different assumptions in connection with I/O pins. These two different assumptions influence the placement of node u when no element in V. We describe two different placements for u as follows.

Assumption 1 Without I/O limit: Any logic block can transfer data with CPU and memory

In this assumption, we find two different cases:

Case 1 is that empty logic blocks exist in the four sides of the reconfigurable hardware, whether u can be placed on any one of these empty logic blocks with/out tracked added will be described.

Case 2 is that no empty logic blocks exist in the four sides of the reconfigurable hardware; whether replace and reroute preceding nodes and edges to make smaller wiring area will be described.

Case 1: try to place u on the empty logic blocks in the four sides of the reconfigurable hardware

That will be two situations happened. One is Case 1.1: no track added. The other is Case 1.2: tracks must be added, and reroute may be used to reduce new added tracks. These situations are described as follows.

Case 1.1: no track added when try route

We use routing methods of CASE I to try route (u,v) or every (u,vi) and limit u to be placed on empty logic blocks in the four sides of the reconfigurable hardware. If no track added when try route, this will be the best situation for u with I/O need with CPU r memory. Because it is unnecessary for u to use extra track segments to transfer data with

CPU or memory. So we can place u on the empty logic block in the four sides of the reconfigurable hardware with the minimal routing requirement to route (u,v) or every (u,vi).

Case 1.2: track added when try route

In this situation, we want to find whether u can be placed on the empty inside logic blocks of the reconfigurable hardware and no new track added when route (u,v) or every (u,v_i) using methods of CASE I . If not, preceding routing paths around empty logic blocks in the four sides of the reconfigurable hardware may be reroute. The rerouting is try to make u can be placed on an empty logic block in the four sides of the reconfigurable hardware and (u,v) or every (u,vi) can be routed with fewer routing requirement. The follow steps are detail method description.

Step 1.2.1: try route to find the routing path (rp1) with the minimal routing requirement (try to place u on empty logic blocks in the four sides of the reconfigurable hardware)

Step 1.2.2: try to place in the empty inside logic blocks of the reconfigurable hardware then try route to find the routing path (rp2) with the minimal routing requirement

If no area added, use rp2 to route and place the I/O node If area added:

Try to reroute the routing paths around the empty logic blocks of the four sides of the reconfigurable hardware to try route to find the routing path (rp3) with the minimal routing requirement for the I/O node’s in/out edge

If no area added, use rp3 to route and place the I/O node

If area added, use the minimal routing path in {rp1, rp2, rp3} to route and place

Case 2: no empty logic blocks in the four sides of the reconfigurable hardware In this case, we first try to place u on empty inside logic blocks of the reconfigurable hardware and route (u,v) or every (u,v_i) to get routing paths with minimal routing requirement. Then we try to backtrack the data flow graph, to find a node (non-I/O node), which have placed on the logic block in the four sides of the reconfigurable hardware. To see whether the routing requirement can be fewer than place u on empty inside logic blocks of the reconfigurable hardware and route (u,v) or every (u,v_i), after backtrack to release a logic block for u to place. The detail steps are as follows.

Step 2.1: try to place the I/O node in the inside empty logic blocks of the reconfigurable hardware then try route to find the routing paths with the minimal routing requirement Step 2.2: backtrack the data flow graph to replace and reroute

Backtrack to the placed non-I/O node, which are placed on the logic block in the four sides of the reconfigurable hardware

Try to release the occupied logic block to place u and rip up the non-I/O node’s edges’ routing paths.

Replace the node’s position and reroute the edgesFind a replaced node that the area

will be added minimal after replaced and reroute and place u and route u or every (u,v_i) Step 2.3: compare the routing path in Step 2.1 and Step 2.2, accept the routing path with less routing requirement then place the I/O node

Assumption 2 With I/O limit: Limit the logic blocks in the four sides of reconfigurable hardware for I/O

In this assumption, when an I/O node is selected to place on the reconfigurable hardware, its possible position will be limit on the empty logic blocks in the four sides of the reconfigurable hardware. And behind this limitation, we use the routing methods in CASE I to route (u,v) or every (u,v_i). Non-I/O node still can be placed on any logic blocks, so these non-I/O nodes may exhaust the logic blocks in the four sides of the reconfigurable hardware. In this situation, we assign an initial placement for roots of a data flow graph before main placement and routing to prevent that non-I/O nodes exhaust the logic blocks in the four sides of the reconfigurable hardware

The first row of the logic block array work is assigned to roots. The initial placement for roots is as follows.

Step1: Allocate the first row of the logic block array to every root according to its descendants

Sort the roots by its descendants (from more to less)

Sequentially allocate successive logic blocks to every root from left to right of the logic blocks of the first row

Step2: Place every root sequentially in the middle of the logic blocks allocated to it

CHAPTER 4 SIMULATION ENVIRONMENT AND

SIMULATION RESULTS

In this chapter, we will describe our simulation environment and show the simulation results. For loop’s order, we will prove give a loop precedence to placement and routing is better. For nodes order, the simulation result of three evaluations mentioned in section 3.5 with six different priorities will tell us which is the best for wiring area. The end, the influence of different limits for I/O nodes will be shown and the best result of our design will compare with VPR.