Related work: Versatile Place and Route (VPR) tool [3][5]

Many placement and routing tools use the basic algorithms in section 2.2 and section 2.3 for their implementation goals, such as to minimize the required wiring length (wire-length-driven), to balance the wiring density across the FPGA (routability-(wire-length-driven), or to maximize circuit speed (timing-driven). In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools. In this thesis, we will take VPR to compare with our design.

2.4.1 Placement algorithm

VPR uses the simulated annealing algorithm mentioned in section 2.2 for placement. A linear congestion cost function provides the best results in a reasonable computation time. The

In the above formulation, the summatio functional form of this cost function is

n is over all the nets in the circuit. For each net, bb_x )]

and bby denote the horizontal and vertical spans of its bounding box, respectively. The q(n) is correction factor which compensates for the fact that the bounding box wire length model underestimates the wiring necessary to connect nets with more than three terminals. Its value depends on the number of terminals of net n; q is 1 for nets with 3 or fewer terminals, and slowly increases to 2.79 for nets with 50 terminals. For example, a net with just two or three terminals will have a correction factor of 1.0 as shown in Figure 2-3. The crossing count of a

four terminal net is about 1.08, since extra wiring is need to reach the fourth terminal, as shown in Figure 2-3. The correction factors for different fanout nets were determined by creating thousands of Steiner trees for randomly distributed net terminals and averaging the correction factor for each of the different fanout nets. Table 2-2 lists the correction factors for nets with up to fifty terminals. Cav,x(n) and Cav,y(n) are the average channel capacities (in tracks) in the x and y directions, respectively, over the bounding box of net n. This cost function penalizes placements, which require more routing in areas of the FPGA that have narrower channels.

Figure 2-3 Examples of correction factors [5]

Num. Terminals Correction Factor Num. Terminals Correction Factor

2~3 1.00 15 1.69

4 1.08 20 1.89

5 1.45 25 2.87

6 1.22 30 2.23

7 1.28 35 2.39

8 1.34 40 2.54

9 1.40 45 2.66

10 1.45 50 2.79

Ta e 2-2 Correction factors for nets with up to fifty terminals [5]

VPR’s router is based on the Pathfinder negotiated congestion algorithm. Basically, this algor

bl

2.4.2 Routing algorithm

ithm initially routes each net by the shortest path it can find, regardless of any overuse of wiring segments or logic block pins that may result in route fail. An iteration of the router

consists of sequentially ripping-up and re-routing (by the lowest cost path found) every net in the circuit. The cost of using a routing resource is a function of the current overuse of that resource and any overuse that occurred in prior routing iterations. By gradually increasing the cost of oversubscribed routing resources, the algorithm forces nets with alternative routes to avoid using oversubscribed resources, leaving only the net that most needs a given resource behind.

VPR contains two routers: one router is routability-driven, and the other router is timing-drive

for custo

finder algorithm routes nets using a breadth-first maze routing algorithm.

A co

= A(i,j)*d(n) + [1 – A(i,j)] * Cost(n) (2.1)

n. We describe VPR’s routability-driven router because it completely devotes to solve congestion without delay time considering. This is the same with our design. The routability-driven routing algorithm in VPR is very similar to the breadth-first routability-routability-driven Pathfinder algorithm, with a few important changes and enhancements.

The Pathfinder algorithm is based upon Nair’s method of iterative maze routing m integrated circuits. During each iteration, every net is ripped-up and re-routed, in the same order during each iteration. During early iterations, nets are allowed to share routing resources with other nets. As the iterations proceed, the sharing of routing resources is penalized, increasing gradually with each iteration. After a large number of iterations, the nets will negotiate among congested resources to try and find a way to successfully route the circuit, allocating key resources to the nets that need them the most. By re-routing all of the nets during each iteration, nets that do not absolutely require congested routing resources can also be relocated.

The basic Path

st function is applied to each node (routing resource) to try and minimize congestion and the delay of more critical nets. The cost function, C(n), applied to each node n by the maze router is:

C(n)

A(i,j) is the slack ratio from the source of net i to the j^th sink of net i. The congestion cost is

he present congestion penalty, p(n), is calculated by VPR as:

where , capacity(n) is the maximum

e b(n) is the base cost of usin n ( th in

historical congestion penalty based upon the over-use of node n during previous routing iterations, and p(n) is the present congestion penalty based on the over-use of node n during the current routing iteration. If a connection lies on the critical path, then A(i,j) will equal 1.0, and cost function (2.1) will be weighted completely towards optimizing delay. If a connection lies on a path with a large slack, A(i,j) will approach 0, and the cost function (2.1) will be heavily weighted towards minimizing congestion.

VPR’s routability-driven algorithm sets A

co tely routability-driven. In the other word, cost function (2.1) becomes congestion cost function (2.2). And for avoiding having to normalize b(n) and h(n), the congestion cost function used by VPR is:

Cost(n) = b(n) * h(

VPR sets the bases costs of almost all of the routing resources to 1. the only ons are input pins, which are given a base cost of 0.95. This causes the router to expand any input pins reached first and speeds up the routability-driven router by up to 1.5 to 2 times.

T

p(n) = 1 + max(0, [occupancy(n) + 1-capacity(n)] * pfac) occupancy is the number of nets presently using node n

number of nets that can legally use node n, and pfac is a value that scales the present congestion penalty. The present congestion penalty is updated whenever a net is ripped-up and re-routed.

The historical congestion penalty, h(n), is calculated by VPR as:

where i al congestion penalty.

{

)

( n

=

h

is the iteration number, and h_fac is a value that scales the historic The historical congestion penalty is updated after a routing iteration.