Chapter 2 Transmitter Architecture…
2.2 Direct-conversion transmitter
The direct-conversion transmitter only performs a single frequency conversion to RF as illustrated in Fig. 2.2. In this case, modulation and up-conversion occur in the same circuit. The direct-conversion transmitter is
usually preferred in a fully integrated design, because it avoids the need for an off-chip IF filter and demands only a single frequency synthesizer.
Fig. 2.2 Direct-conversion transmitter
The architecture of Fig. 2.2 suffers from an important drawback: local
pulling or injection pulling. This issue arises because the PA output is a modulated waveform with high power and a spectrum centered around the LO frequency. If the high power signals feedback to the local oscillator through coupling or radiation, it becomes the noise injection to the oscillator. The problem worsens if the PA is turned on and off periodically to save power.
The phenomenon of LO pulling is alleviated if the PA output frequency is sufficiently higher or lower than the oscillator frequency. For quadrature
modulation scheme, this can be accomplished by “offsetting the LO frequency” as shown in Fig. 2.3(a)(b).
(a)
(b)
Fig. 2.3 Offset the LO frequency (a) By adding two LO (b) by multiplying LO
Other issues of direct-conversion transmitter are not as critical as mentioned in the above discussion. First, the power control allocated at RF is harder to maintain accuracy and consumes more power. Second, the quadrature modulation occurs at RF frequency, thus I and Q matching become worse.
Chap 3.
Circuit Implementation
3.1 Circuit block diagram
Fig 3.1 shows a block diagram of the transmitter front-end using direct conversion architecture, the modulated I/Q baseband (BB) signal is directly mixed with a local frequency at the desired transmitted channel frequency. However, this architecture suffers from the VCO pulling due to the leakage of the power
amplifier (PA) output. This drawback can be overcome by proper shielding (or separating) local oscillator and PA.
Fig 3.1 Block diagram of the transmitter front-end
In order to reduce size and cost of the transmitter, how to achieve a higher degree of integration of RF circuitry is one of the key design issues. The
transmitter front-end is comprised of two baluns, a local driver amplifier, two quadrature phase generators, an I/Q quadrature modulator (Gilbert cell mixer) and a three-stage pre-amplifier. The I/Q modulator take differential base-band input BB_I and BB_Q, frequency up-converts with the quadrature LO signals, and sums the output signals. On-chip inductors are used as loads at the mixer output to increase the voltage swing. The pre-amplifier boosts the output power to a level capable of driving the external power amplifier.
Precise quadrature LO signals are important for the direct conversion architecture. Any amplitude mismatches or phase differences apart from 90o between LO_I and LO_Q causes degradation in the error vector magnitude (EVM). This design contains quadrature phase generators to reduce the amplitude mismatch and phase error. The purpose of LO amplifier is twofold: to improve the isolation between the mixer and LO, therefore reducing injection pulling of the LO, and to provide large LO level to optimize the mixer linearity and noise performance.
3.2 Specification
The 802.11a standard provides a total bandwidth of 300MHz in the 5GHz UNII band (5.15 to 5.825GHz), so operating in the 5 to 6 GHz which covers all the UNII frequency bands is our design goal [1]. The maximum allowed transmit
power is 16, 23, and 29dBm, respectively, for channels residing in the lower, middle and upper band. The specification of middle band is chosen in our design.
Thus, the maximum output power through antenna is
P
antenna_out,max =23dBmwhich contains a 6-dB antenna gain. Hence, the final transmit power before antenna should be below
P
TX_OUT,max =23−6=17dBmThe transmitter output power is thus determined as 16dBm with 1-dB margin.
Notice that this value is the average output power. The peak-to-average power ratio (PAPR) is the problem to be concerned for OFDM system. In the worst case, suppose 52 peaks for the sinewaves add together, the PAPR will be 10log(52) ≈ 17dB. However, in practice, The PAPR is as low as 6 dB may meet the EVM and packet error rate (PER) requirement of the IEEE 802.11a specifications. Thus, the peak output power is
With the Pout and gain of each stage, the output power of each module is obtained in Table 3.1. In general, the OP-1dB is the maximum operation boundary.
After calculation, the OP-1dB of preamp and quadrature mixer are 4dBm and -11dBm, respectively. The relationship between OP-1dB and OIP3 can be
obtained
The link budget of the entire transmitter system is listed in Table 3.1 and the specifications of transmitter front-end are summarized in Table 3.2.
Table 3.1 Link budget of the entire transmitter
Parameters BPF1 T/R PA BPF2 Pre Amp Mixer LPF DAC Unit
Gain -1 -2 22 -1 15 -5 -2 dB
Pout,avg 14 15 17 -3 -2 -17 -12 -10 dBm
Pout,peak 22 24 25 3 4 -13 dBm
OP-1dB 22 24 25 4 -11 dBm
OIP3 35 14 -1 dBm
Table 3.2 Specifications of the transmitter front-end Parameters Specifications Frequency Range 5-6 GHz
Conversion Gain 10 dB
IIP3 4 dBm
OIP3 14 dBm
OP1dB 4 dBm
Sideband rejection >30 dB Carrier rejection >30 dB
3.3 Balun design
With today’s CMOS IC technology, it can provide high frequency active devices for RF applications, but high quality passive components (e.g., inductors and transformer) present serious challenges for integration. Although significant progress toward the integration of high quality inductors has been reported, practical planar monolithic inductors achieves only moderate performance due to resistive losses in the metal traces and in the underlying substrate.
In this section, two types of baluns (balance to unbalance) which are suitable for CMOS implementation are described. A monolithic transformer comprising two coupled inductors occupies less area and exhibits a higher quality factor (Q) than LC-balun in differential circuits. However, modeling and parameter
extraction of monolithic transformer is more difficult than the other. It also needs 3D electromagnetic simulator and spends much more time on simulation.
On-chip LC-balun is shown in Fig. 3.2. It is easy to be designed and fabricated in IC processes. Therefore, the LC-balun is used in our chip. The insertion loss of the LC-balun is higher
Fig. 3.2 LC-balun
than the monolithic transformer and need carefully design.
We will analyze this circuit by reducing it into two simple half-circuits driven by symmetric source, and redrew the
circuit as shown in Fig. 3.3. Note that the port impedances differ from Fig. 3.2.
(RG
’ = 2R
G, and R
L’ = 1/2R
L ) The balun is designed for the band around 5.5GHz. The frequency response of LC-balun is illustrated in Fig. 3.4, indicating that the phase error between port 2 and port 3 is less than 1.5o and the amplitude mismatch is less than 0.5 dB.m2freq=
3.4 Quadrature generation design
Quadrature signals can be generated from a local oscillator in several different ways. The most common is the RC-CR
network as shown in Fig. 3.5 [2].
Consider a sinusoidal with frequency
ω
applied at the input Vin , the outputs Vout1 andV
out2 isFig.3.5 RC-CR network
RC
and hence
Thus, Vout1 and Vout2 have 90o phase difference at all frequencies, but the output amplitudes are equal only at
ω = 1/(RC). Usually, it is difficult to achieve
the accurate value of on-chip passive components and therefore amplitudemismatches arise. The amplitude mismatch, which is sensitive to variations in RC value, can be suppressed by limiting amplifiers.
Note that capacitive paths between the two outputs introduce phase error, demanding careful layout. Amplitude mismatches between the load capacitance also contribute to phase error.
Another issue in the circuit of Fig. 3.5 is the harmonic component of Vin . Suppose Vin
= A
1cosω t + A
n cos nω t, and therefore
)
The result indicates that it has a phase imbalance between Vout1 and Vout2. Moreover, the magnitude of the harmonics also experiences unequal gains through the two paths, introducing amplitude mismatches at the output. If the LO
harmonics are significant, the RC-CR network must be preceded by a lowpass filter.
The simulation results of RC-CR network are shown in Fig. 3.6, showing that the phase error is less than 0.5o and the mismatch is less than 1 dB between 5 and 6GHz.
Fig. 3.6 Phase difference and amplitude mismatch
3.5 Mixer design
Mixers perform frequency translation by multiplying two signals (and their harmonics). Up-conversion mixers employed in the transmit path have two
distinctly inputs, called the base-band (BB) port and the local oscillator (LO ) port.
Several up-conversion mixer topologies that can be realized in CMOS IC processes are presented. Since balanced mixer designs are more desirable due to its lower spurious outputs, higher
common-mode noise rejection and higher port-port isolation, only balanced type mixer are discussed in
this section[14].
Fig 3.7 Single-balanced mixer
The single-balanced mixer shown in Fig. 3.7 is the simplest approach that can be implemented in most IC processes. The single balance mixer offers a desired single-ended RF input and it does not require a balun at the input.
However, the drawback of single-balance mixer has low 1db compression point, low port-to-port isolation, low IIP3 and high input impedance.
If higher noise figure can be tolerated such as transmitter, the micro-mixer in Fig. 3.8 offers the best IIP3 due to its third-order harmonic distortion cancellation
mechanism. With proper biasing, the input impedance can be set close to 50 ohms which eliminates external matching network. However, using this topology, it would be difficult to increase the gain or reduce the noise figure. It achieves
reasonable port-to-port isolation and eliminates the balun by using a current mirror.
Because having three transistors in stack, limits the maximum signal swing and result in a lower output 1-dB compression point.
Fig.3.8 Micro-mixer
The Gilbert cell (double-balanced) mixer was invented in the 60’s, but it still remains to be the most popular mixer circuit. A basic mixer circuit is shown in Fig.
3.9. Baseband (BB) signal is applied to the lower terminals of the stack, and LO
signal is connected to the upper ones. Thus RF signal is obtained as an output. It can prove high conversion gain and high port-to-to isolation. The linearity is reasonably good. Typically, the RF filter preceding this mixer is single-ended so a balun is needed to convert the single-ended signal to differential signal. However, balun having low insertion loss is very difficult to implement in IC processes.
Fig. 3.9 Gilbert cell mixer
The distortion in RF signal is dominated by the lower BB differential pair rather than the upper LO differential pairs. This is because the BB signal is not a single tone signal [13]. Thus, harmonic distortions in the lower differential pair will cause intermodulation distortion, and these intermodulated components may appear at the same frequency of a wanted channel. This intermodulation distortion can be suppressed by improving the linearity of the mixer itself. Hence linearity is
an important parameter for the evaluation of a mixer performance, and it is usually indicated by 1 dB compression point and third-order intercept pointer (IP3).
The lower differential pair, called source coupled differential pair, is redrawn in Fig. 3.10. The general
relationship between the input signal Vd and the output current Id of the circuit is described as follows [3][13]
Fig 3.10 Source coupled
⎥⎥ which is called a fundamental in general. The rest higher order term (V
(
βISS /4)
0.5Vdd3
, V
d5,
V
d7, …), on the other hand , are distortion components that are not desirable and are often called harmonics. Eq. (3.11) reveals that the linearity of the sourcecoupled pair increases, if tail current source ISS increases. Because the effect is slight, other linearization techniques have been developed.
A differential pair can be degenerated as shown in Figs 3.11 (a) and (b) [3].
In Fig. 3.11 (a), ISS
flows through the degeneration resistors, thereby consuming
voltage headroom of ISSR
S / 2. The circuit of Fig. 3.11 (b), on the other hand, does not involve this issue but it suffers from a slightly higher noise and offset voltage because the two tail current sources introduce some differential error and noise.Fig. 3.11 Source degeneration applied to a differential pair
Resistive degeneration requires accuracy resistors, which is unavailable in today’s IC technologies. As depicted in Fig.3.13, the resistor can be replaced by a NMOS operating in deep triode region. Recall the I-V relationship of the NMOS in triode region
( )
⎥⎦⎤ neglected and equivalent RON is obtained.D n ox
(
GS t)
However, for large input swings, M3 may experience substantial change in its on-resistance. The circuit of Fig. 3.13(a) can be further modified as Fig. 3.13(b).
As the gate voltage of M1 becomes more positive than the gate voltage of M2 , transistor M3 stays in the triode region because VD3
= V
G3- V
G1 whereas M4 eventually enter the saturation region because its drain voltage rises and its gate and source voltage fall. Thus, the circuit remains relatively linear even if one degeneration device goes into saturation.
Fig. 3.12 Source degeneration with NMOS
The proposed mixer is illustrated in Fig. 3.13. Because quadrature modulation is required in modern digital communications, the mixer can be divided into two parts: in-phase and quadrature phase part. The in-phase and quadrature phase signal is combined by inductor load at output. The output of the mixer is chosen differential topology because it can eliminate even-order term harmonic distortion and have better common-mode rejection. The output of the mixer is ac-coupled and directly connected to the pre-amplifier input. The matching network of the inter-stage between mixer and preamplifier is not
required because the impedances of mixer output and preamplifier input are close to conjugate match.
Fig. 3.14 and Fig. 3.15 show the performance of the proposed mixer. It achieves a -5.2dB conversion gain at 5.5GHz with 37.2 dB third-order harmonic rejection and the flatness is less than 0.5dB between 5 and 6 GHz. The proposed mixer dissipates 12.6mW which draws 7mA from 1.8V power supply.
Fig. 3.13 The proposed mixer
5.2E9 5.4E9 5.6E9 5.8E9
5.0E9 6.0E9
3.6 Pre-amplifier design
The pre-amplifier is used to boost the output power and to drive external high power amplifier. The proposed pre-amplifier, which consists of a three-stage differential amplifier, is shown in Fig. 3.23. For simplifying analysis, each stage will be discussed individually as follows.
3.6.1 First stage amplifier
The first stage amplifier is shown in Fig. 3.16. The circuit topology is full symmetric, so the half-circuit concept is used for simplifying analysis. Fig. 3.17 shows the equivalent half-circuit of Fig.3.16. It is called the cascode amplifier with single tuned load[5]. The cascode amplifier with tuned load provides selective amplification of
wanted signals and a d of degradation of unwante signals. The use of inductor
L
egree d
es lso
1 and L4 not only increas the headroom but a
cancels the parasitic drain- source and gate-source
Fig. 3.16 The first stage amplifier
capacitance. We can resonate out this capacitance with an appropriate choice of inductance and obtain a maximum gain at arbitrary frequency
ω
0. The casc topology (Mode
1
/M
2, M
11/M
12) eliminates the Miller effect and improves theamplifier reverse isolation. The NMOS M3
/ M
13 operate in deep triode region and its equivalent resistance RON is obtained by Eq.(3.13).Fig 3.17 Equivalent half circuit of Fig. 3.16
of magnitude function with frequency is shown in Fig.
3.18. The peak magnitude response occurs at the resonant frequency
e
where Le is the parallel inductor, Ce is the parasitic capacitance. The -3dB bandwidth is
It must be noted that Eq.(3.16) is certainly true only at low frequencies. At RF/microwave frequencies, the scattering (S) parameters, which are related to incident and reflected power, are more suitable to describe the two-port network.
This simplified schematic of a single stage amplifier is shown in Fig. 3.19.
We can define the transducer power gain GT, which quantifiers the gain of the amplifier placed between source and load [4].
( ) ( )
Fig. 3.19 Simplified schematic of a single stage amplifier
For amplifier designer, how to decide the reflection coefficients is an important issue. As examples, in a design requiring maximum transducer power gain, the reflection coefficients are selected as follows [7]
0)
In a high power amplifier design, the reflection coefficients are selected as follows
OP L =Γ
Γ (3.20)
where ΓOP is the load reflection coefficients of maximum power.
In a low-noise design, the reflection coefficients are selected as follows
opt S =Γ
Γ (3.21)
where Γopt is the optimum noise reflection coefficients.
In a wideband amplifier design, it is usually necessary to reduce the
gain-bandwidth constrains associated with the impedance to be matched by using resistive feedback or by loading the device with shut or series resistance [4][6]. To
design a wideband amplifier, two different design approaches are used: frequency compensated matching network and negative feedback. Frequency compensated matching network introduce an impedance mismatch to compensate for the
frequency variation. Negative feedback allows a flat gain response and reduces the input and output VSWR over a wide frequency range. In our design, we sacrifice the impedance matching to get wider bandwidth. We also utilize negative
feedback approach, for example, M3
/ M
13 contributes a series feedback.3.6.2 Second stage amplifier
The second stage amplifier, shown in Fig. 3.20, shares the same circuit topology as the first stage amplifier but remove two cascade NMOS. It can allow higher signal swing. As mentioned above, the circuit analysis is similar to the first stage amplifier.
Fig 3.20 The second stage amplifier
3.6.3 Last stage amplifier
The last stage amplifier, serve as a power amplifier, is illustrated in Fig. 3.21.
In order to increase the amplifier efficiency, the last stage operates in Class AB mode whose conduction angle is less than 180o. This circuit, is called a push-pull amplifier, consists of four NMOS devices (M6
/M
7, M
16/M
17) to share the load current. The inductors (L3/L
6) play the role of a RF choke providing DC biasing.The trace width of inductors must be wide enough to support large current density.
Fig. 3.21 puts a balun transformer together and redraws the circuit as shown in Fig.
3.22.
Fig.3.21 The last stage amplifier
Fig. 3.22 Equivalent circuit of Fig. 3.21
The theoretical efficiency for true Class B operation with sinusoidal signals is 78.5%, which is greater than the 50% theoretical maximum obtainable with Class A operation. Although efficiencies near the theoretical limits are obtainable at low frequencies, it is difficult to achieve more than 50% efficiency at
microwave frequencies. There are few Class B amplifiers in the microwave region proposed. This was due the fact that when an MOSFET is biased near pinch-off region, its gain is substantially less than when it is operated at maximum gain point. The efficiency and linearity of Class AB amplifier are intermediate between those of a Class A and Class B amplifiers.
3.6.4 Proposed pre-amplifier
The proposed pre-amplifier employs a fully differential three-stage amplifier as shown in Fig. 3.23. The fully
differential topology has several advantages as follows: lower substrate noise and sensitivity, doubled signal swing, and linearization of transfer function
(elimination the even harmonics). The cost will be higher power consumption. A three-stage amplifier offers sufficient gain and large bandwidth.
Fig 3.24 demonstrates the frequency response of the proposed pre-amplifier. It achieves 20 dB transducer power gain at 5.5 GHz. Notice that the transducer power gain in upper bands is designed higher to compensate the frequency variation of a up-conversion mixer.
Fig. 3.23 The proposed pre-amplifier
m1RFfreq=
dB(S(2,1))=20.0225.500E9
5.2E9 5.4E9 5.6E9 5.8E9
5.0E9 6.0E9
16 17 18 19 20
15
21 m1
RFfreq
dB(S(2,1))
Fig 3.24 Frequency response of the proposed pre-amplifier
3.7 Simulation results
The simulation results of the entire transmitter front-end are shown in this section. Fig.3.25 exhibits the harmonics of in-band spectrum at 5.5GHz. This diagram tells us that sideband rejection is 38.7dB, carrier rejection is 33.4dB and three-order harmonic rejection is 36.9dB. Fig.3.26 and Fig. 3.27 show the in-band spectrum at 5GHz and 6GHz respectively. The harmonics of out-of-band spectrum are shown in Fig 3.28. Indicating that it achieves 23.2dB out-band rejection.
The simulation results of the entire transmitter front-end are shown in this section. Fig.3.25 exhibits the harmonics of in-band spectrum at 5.5GHz. This diagram tells us that sideband rejection is 38.7dB, carrier rejection is 33.4dB and three-order harmonic rejection is 36.9dB. Fig.3.26 and Fig. 3.27 show the in-band spectrum at 5GHz and 6GHz respectively. The harmonics of out-of-band spectrum are shown in Fig 3.28. Indicating that it achieves 23.2dB out-band rejection.