Chapter 3 Circuit Implementation
3.6 Pre-amplifier design
3.6.4 Proposed pre-amplifier
The proposed pre-amplifier employs a fully differential three-stage amplifier as shown in Fig. 3.23. The fully
differential topology has several advantages as follows: lower substrate noise and sensitivity, doubled signal swing, and linearization of transfer function
(elimination the even harmonics). The cost will be higher power consumption. A three-stage amplifier offers sufficient gain and large bandwidth.
Fig 3.24 demonstrates the frequency response of the proposed pre-amplifier. It achieves 20 dB transducer power gain at 5.5 GHz. Notice that the transducer power gain in upper bands is designed higher to compensate the frequency variation of a up-conversion mixer.
Fig. 3.23 The proposed pre-amplifier
m1RFfreq=
dB(S(2,1))=20.0225.500E9
5.2E9 5.4E9 5.6E9 5.8E9
5.0E9 6.0E9
16 17 18 19 20
15
21 m1
RFfreq
dB(S(2,1))
Fig 3.24 Frequency response of the proposed pre-amplifier
3.7 Simulation results
The simulation results of the entire transmitter front-end are shown in this section. Fig.3.25 exhibits the harmonics of in-band spectrum at 5.5GHz. This diagram tells us that sideband rejection is 38.7dB, carrier rejection is 33.4dB and three-order harmonic rejection is 36.9dB. Fig.3.26 and Fig. 3.27 show the in-band spectrum at 5GHz and 6GHz respectively. The harmonics of out-of-band spectrum are shown in Fig 3.28. Indicating that it achieves 23.2dB out-band rejection.
Fig. 3.29 and 3.30 illustrates the frequency response of the conversion gain and the output power, respectively. As the figure indicates, the conversion gain equals 13.8 dB at 5.5GHz, and the flatness is less than 3 dB over the entire band.
Fig. 3.31 and 3.32 shows the output P1dB, IIP3 and OIP3 which are 10.5dBm, 5dBm and 15dBm, respectively. The entire transmitter front-end dissipates 54mW
which draws 30mA from 1.8V power supply.
m5freq=
Fig. 3.28 Harmonics of out-band spectrum
m1LOfreq=
5.2E9 5.4E9 5.6E9 5.8E9
5.0E9 6.0E9
Fig 3.29 Frequency response of the conversion gain
m4LOfreq=
5.2E9 5.4E9 5.6E9 5.8E9
5.0E9 6.0E9
Fig 3.30 Frequency response of the output power
m1Power_BB=
Fig 3.31 Ouput-1dB compression point
-18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18
3.8 Other applications
In this section, we utilize the same architecture of the transmitter, but change and optimize the component values for dual band and ultra-wide band applications.
3.8.1 Dual band (2.4GHz)
Fig.3.33 exhibits the harmonic of in-band spectrum at 2.45GHz. The sideband rejection is 7.8dB, carrier rejection is 38.7dB, three-order harmonic rejection is 45.3dB and the conversion gain is 10.2dB. The harmonic of out-band spectrum is shown in Fig 3.34. It reaches an 8.6dB out-band rejection.
m1freq=
Fig 3.33 Harmonics of in-band spectrum at 2.45GHz
m5freq=
Fig 3.34 Harmonics of out-band spectrum
3.8.2 UWB Band (10GHz)
The harmonic of in-band spectrum at 9.5GHz is shown in Fig. 3.35. As the diagram indicates that sideband rejection is 37.2dB, carrier rejection is 30.7dB, three-order harmonic rejection is 35.7dB and the conversion gain is 6.1dB. Fig 3.36 shows the harmonic of out-band spectrum. It achieves a 32.9dB out-band rejection.
Fig 3.35 Harmonics of in-band spectrum
m5freq=
Fig 3.36 Harmonics of out-band spectrum
Chap 4.
Layout Considerations
4.1 Chip layout considerations
Someone said that making a layout is an art by itself. Some layouters claim that they have made a good layout when the layout-versus-schematic (LVS) check shows no error messages. This is a necessary, but not sufficient condition for a good RF layout. Poor layout causes the performance degradation of the circuits, or even result in wrong working. There are some design rules helping us to make a better layout, as follows.
First of all, in order to avoid the phenomenon of LO pulling, the RF output stage (PA) should be physically far away from the LO circuits. But it is difficult to do that in our chip. To minimize the effect, RF output stage and LO circuits are placed perpendicularly to each other. In IC processes, “guard rings” can also be employed to reduce the coupling.
Next, the fully differential topology is used in our design, the mismatch and symmetry should be concern. The common-centroid configuration is employed to
reduce device mismatch due to the effect of gradient. Moreover, the trace length of the connections for each stage must keep as equal as possible to minimize phase error.
Finally, how to determine the trace width of those connections is an
important issue. For DC paths, it should be wide enough to support large current.
For RF paths, the parasitic capacitor will be increased, if we increase the trace width. However, narrow trace raises parasitic inductor and the metal resistor. To solve this problem, we will introduce a transmission concept. For a lossless transmission line, the characteristic impedance is obtained as
C
Z0 = L (4.1)
where L is series inductance per unit length and C is shunt capacitance per unit length. Many CAD tools can provide the characteristic impedance of the planar transmission lines (e.g., coplanar waveguide, microstrip and stripline etc.).
Our design employs a 50 Ω microstrip line, which characters are listed as follows:
dielectric constant ε = 4.1 (SiO2), the height is 2.1µm. Thus the width of a microstrip line can be obtained as 4 µm.
Consider the case of a bend in a microstrip line, is illustrated in Fig.4.1. The straightforward right-angle bend has a parasitic discontinuity capacitance. This effect could be minimized by mitering the corner. The optimum value of the miter
length a, depends on the characteristic impedance and the bend angle, but a value of a = 1.8W is often used in practice. The chip layout is shown in Fig. 4.2, and the chip area occupied 2.5×2.5 mm2.
Fig. 4.1 Bend of a microstrip line
Fig. 4.2 Chip layout of the transmitter front-end
4.2 Package and ESD considerations
The 20-pin QFN package provided by SPIL is employed in our design as illustrated in Fig. 4.3. To prevent crosstalk due to adjacent pin coupling, the RF pins (LO and RF_out pin) are surrounded by ground wire, and the LO pins is allocated away from the RF_out pin. Fig 4.4 shows the simplified package model for each pin. Each pin exhibits a finite self-inductance which is about 1-nH.
Multiple bond wires and pins are used to decrease the equivalent inductance and resistance on the VDD and ground pins. A large on-chip capacitor, which is composed of four MIM
capacitors in this chip, is used to stabilize the difference between VDD and ground, and reduce the risk of inter-stage coupling.
Fig. 4.3 Pin definition
Fig. 4.4 Package model for each pin
Electrostatic discharge (ESD) may result in CMOS devices permanent damage without protection circuits. Fig. 4.5 shows the most popular ESD protection circuits in commercial using. The diode chains clamp the external discharge to ground or VDD, and a large gate ground NMOS will break down once enormous potential across VDD and ground. The ESD protection circuits provided by UMC ensure 3.6KV in human body mode (HBM) test but induce about 40fF capacitances in each pin. The ESD
parasitic capacitances and the bond-wire inductors must be considered together during simulation.
Fig. 4.5 ESD protection circuit
4.3 PCB layout considerations
The transmitter chip is mounted on the PCB board as shown in Fig. 4.6. The layer stack-up structure of a PCB is illustrated in Fig. 4.7. The loss tangent (δ=
0.0021) and dielectric constant stability for RO4003 material is superior to FR-4, so that RO4003 severs as the dielectric material (εr= 3.38) between layer 1 and layer 2. As mentioned above, the microstrip characteristic impedance could be obtained by CAD tools (APPCAD 3.0, Agilent), as shown in Fig. 4.8. We obtain the width of transmission line equals 17 mil. Layer 2 and layer 3 provide large and low impedance power planes. The area of the power planes near the chip look like a good, high frequency capacitor and help with decoupling.
The design rules of PCB layout are similar to the chip layout. The RF output port should be put away from the LO port. For differential paths, equal length and symmetric layout is essential. In order to reduce transmission loss, mitering corners on microstrip traces are formed and the microstrip length is as short as possible.
Fig. 4.6 PCB board
Fig. 4.7 Layer stack-up of PCB
Fig. 4.8 Calculation of a microstrip characteristic impedance
Chap 5.
Measurement
Fig.5.1 shows the essential instruments which characters are listed as
follows:
Spectrum analyzer (PSA, Agilent E4446A) 3Hz ~44GHz ×1 Signal generator (ESG, Agilent E4438C) 250K~6.0GHz ×2 Signal generator (ESG, Agilent E4432B) 250K~3.0GHz ×2 Power supply (Agilent E3610A) 0~8V 3A, 0~15V 2A ×1
Fig. 5.1 Instrument overview
Supply ESG (250K~ 3G)
PSA
ESG (250K~ 6G)
5.1 Harmonic test
5.1.1 Instrument setup
The equipments are connected as shown in the Fig. 5.2, and use the
following procedure to set up those instruments for measuring the harmonics of the transmitter IC. Note that the 10MREF_OUT terminal of ESG1 must be
connected to the 10MREF_IN of ESG2.
1. Set up the Spectrum analyzer parameters as follows: Center frequency = 5.5 GHz, Span = 100MHz, Amplitude = 10dBm, RBW = 300 KHz.
2. Set up the ESG1/ESG2 parameters: Frequency = 10MHz, Level = -7dBm.
3. Because the I and Q channel signals have 90o phase difference, it is necessary to calibrate the phase before the measurement. Using the following steps (4~5) to do that.
4. Adjust the ESG2 Phase until the lower and upper sideband harmonics are equal, as shown in Fig. 5.3. Recode the phase
θ
1.5. Assign the ESG2 Phase
θ
2=θ
1-90o.6. For the ESG3, set up the parameter as follows: Frequency = 5.5GHz,
Level = 1.5dBm.
Fig. 5.2 Instrument configuration for harmonic test
Fig. 5.3 Phase calibration
5.1.2 Results
Fig 5.4 exhausts the measured transmitter in-band spectrum when the
10MHz quadrature signals are applied to the input terminals of the BB_I and BBQ.
Fig. 5.4 shows that it archives a sideband rejection of 34.3dB, a carrier rejection of 32.4dB and a third-order harmonic rejection of 31.1dB.
The out-of-band spectrum is illustrated in Fig.5.5, and it tells that the out-of-band rejection equal 51.8dB.
Fig. 5.4 In-band spectrum
Fig. 5.5 Out-of-band spectrum
5.2 Frequency response test
5.2.1 Instrument setup
Connect the equipments as shown in the Fig.5.2, and use the following
procedure to set up these instruments for measuring the frequency response.
1. Set up the spectrum analyzer parameters as follows: Center frequency = 5.5 GHz, Span = 1.5GHz, Amplitude =10dBm, RBW = 300KHz,
Trace> Maxhold mode.
2. Set up the ESG1/ESG2 following parameters: Frequency = 10MHz,
Level = -7dBm, and the phase difference = 90
o between the ESG1 andESG2
3. For the ESG3, set the Level = 1.5dBm and sweep Frequency from 5GHz to 6GHz.
5.2.2 Results
The frequency response of the output power is displayed in Fig. 5.6. The flatness remains below 4.1 dB over the entire band. The frequency response of the conversion gain is obtained by a MATLAB program for calculation and plotting as shown in Fig. 5.7. The conversion gain equals 10.5 dB at 5.5GHz. It must be noted that the cable loss (about 1.5dB) must be considered during the calculation.
Fig. 5.6 Frequency response of output power
5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6 7.5
8 8.5 9 9.5 10 10.5 11 11.5 12
frequency (GHz)
Conversion gain (dB)
Fig. 5.7 Frequency response of conversion gain
5.3 Output P1-dB test
5.3.1 Instrument setup
Connect the equipment as shown in the Fig. 5.2, and use the following procedure to set up those instruments for measuring output 1-dB compression
point.
1. Set up the spectrum analyzer parameters as follows: Center frequency = 5.5 GHz, Span = 100MHz, RBW = 300 KHz, Amplitude = 10dBm 2. Set up the ESG1/ESG2 following parameters: Frequency = 10MHz,
Level = -7dBm and the phase difference = 90
o between the ESG1 and ESG2.3. For the ESG3, set the Frequency = 5.5GHz and sweep Level from -20 to 0dBm.
5.3.2 Results
The measured data are recorded and plotted by MATLAB as shown in Fig.5.8. It indicates that the output 1-dBompressioin point occurs at 3.8dBm when the BB_power of -5dBm is applied.
-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0
Output P1dB = 3.74dBm Input P1dB = -5dBm
P11m linear
Fig. 5.8 OP-1dB compression point
5.4 IIP3 and OIP3 test
5.4.1 Instrument setup
The equipments are connected as shown in the Fig.5.2, and use the following procedure to set up those instruments for measuring IIP3 and OPI3.
1. Set up the spectrum analyzer parameters as follows: Center frequency =
5.5 GHz, Span = 100MHz, RBW = 300 KHz, Amplitude = 10dBm 2. Set up the ESG1/ESG2 parameters: Frequency = 10MHz, Level =
-7dBm and the phase difference = 0o between the ESG1 and ESG2.
3. For the ESG3, set the Frequency = 5.5GHz and sweep Level from -20 to 0dBm.
5.4.2 Results
The IIP3 and OIP3 point can be found by a simple MATLAB program. The measured data are recorded and plotted as shown in Fig.5.9. As the figure indicates, the IIP3 and the OIP3 is about 8dBm, 13.4dBm, respectively.
-20 -15 -10 -5 0
-60 -50 -40 -30 -20 -10 0 10
Output (dBm)
BB power (dBm)
Output IP3 = 13.4056dBm
Input IP3 = 8dBm P11m
P13p
Fig. 5.9 IIP3 and OP3
5.5 Transmit spectrum mask test
5.5.1 Instrument setup
Connect the equipments as shown in the Fig.5.10. The BB_I/BB_Q port is connected to the I /Q _output connector of ESG1. In order to control the ESG1 for creating an 802.11a OFDM waveform, Agilent Signal Studio software is launched.
The Agilent Signal Studio configuration is illustrated in Fig. 5.11. After
downloading the 802.11 OFDM signal to the ESG1 by the LAN or GPIB interface, use the following procedure to set up the spectrum analyzer (PSA) parameters for
measuring the spectrum mask.
1. Press MODE > Spectrum analysis.
2. Press Frequency Channel > 5.5 GHz
3. Press Mode Setup > Radio Std > More 1 of 3 > More 2 of 3 > 802.11a,
Measure > More 1 of 2 > Spectrum Emission Mask, and Meas Setup
> Optimize Ref Level.
Fig. 5.10 Instrument configuration for spectrum mask test
Fig. 5.11 Signal studio setup
5.5.2 Results
Fig. 5.12 displays the measured transmitter output spectrum while transmitting a -7.22dBm 54Mb/s QAM64 modulated signal. Because the PSA power measurement is averaging the power of the bursted transmission, the actual power can be calculated using the following equation
Power = Displayed Total Pwr +10 × log (duty cycle) + cable loss (5.1)
The actual output power is about -4.7dBm, if the duty cycle is 80 %.Fig. 5.12 IEEE 802.11a standard spectrum
5.6 System test
5.6.1 Instrument setup
The MIMO (multiple input multiple output) system can transmit or receive simultaneously two or more path signals by multiple antennas to overcome
multi-path phenomenon. The transmitter chips are verified in the MIMO system as shown in Fig. 5.13. The diagram only shows the connection of path one signal, another path signal is directly connected by a cable. The data rate of entire system is about 40 Kb/s, which is limited by the DSP (base-band processor) performance.
Fig. 5.13 Instrument configuration for system test