Effective Mobility Extraction

The effective mobility in MOSFET devices is a key parameter to describe the carrier transport and a also probe to study the electric properties of a two-dimensional carrier system. In order to extract the

µ

_eff, one of the most powerful methods is the combination of split capacitance-voltage (C-V) measurments, which are to deal with the used inversion and depletion charges, and linear I_d-V_gs measurements [6]. Fig. 10 schematically shows the equivalent circuit of a MOSFET device. If we take the R_sd into account in (2.1), the drain and source voltages are rewritten [21]

(3.10)

V

_ds

− I

_d

R

_sd

= V

_ds

'

(3.11)

I R

_sd

V '

device is operated in the linear region (Vgs-Vth >> Vds). The series resistances can be considered nearly the same between the drain and source. With the formulas (3.10) and (3.11), the C_ox(V_gs-V_th-0.5V_ds) factor in (2.1) is kept

The inversion charge Q_inv under strong inversion condition, which is used in evaluating

µ

_eff and E_eff, can be approximately expressed [22]：

⎟ ⎠

The approximation made in (3.13) is frequently employed to extract the mobility, but it leads to large errors in extracting mobility around the Vth. There are two essential approahes to improve the accuracy of (3.13) in extracting

µ

_eff [20]. One is to measure the gate-to-channel capacitance Cgc and obtain the Qinv from the voltage integral of the C_gc [4], [6], [23]. The second approach is to perform a split C-V measurement to get C-V characteristics, then comparing the experimental and the simulated C-V characteristics (via Poisson-Schrödinger

self-consistent simulations) to obtain the Q_inv.

Futhermore, it must be noted that the V_th through calculated Q_inv may not be exactly equal with that of Id(V_gs), especially for different devices. For this reason, we can extract the

µ

_eff more accurately by shifting Q_inv characteristics such as to compensate for the Vth discrepancy [4], [20]. Finally, the expression of

µ

_eff can be deduced from (2.1), (3.10), and the obtained Qinv：

(3.14)

⎟ ⎟

⎠

⎞

⎜ ⎜

⎝

⎛

⎟⎟ ⎠

⎞

⎝

⎛

) (V Q

1 V

) (V I W L

g inv ds

gs eff d

eff

= ⎜⎜ '

μ

Chapter 4

Experimental Data and Interpretations

The halo-implanted bulk n-channel MOSFET devices with the gate width of 10µm, 1µm, 0.6µm, and 0.24µm under investigation were fabricated in a state-of-the-art manufacturing process. The major parameter extractions are focused on the nMOSFET devices with the channel length from 0.05µm to 0.1µm. Fig. 11 schematically shows the flowchart summarizing the procedures of

µ

_eff extraction. In the flowchart diagram, the bold, solid line, and dashed dots blocks indicate the expreimental data, extracted parameters, and simulated results during the measurements, respectively.

The objective for the C-V measurement is extracting the oxide thickness t_ox, the dopant concentration of poly gate N_poly and substrate N_sub, and the effective channel length Leff of the devices. The C-V characteristics of an nMOSFET device are measured by means of the HP4284A LCR meter, followed by parameter extraction by comparing the measured and simulated C-V characteristics of an nMOSFET device. With the extraction results shown in Fig.

12, we get t_ox = 1.215 nm, N_poly = 4×10¹⁹ cm^-3, and N_sub = 4×10¹⁷ cm^-3.

I-V measurement includes Id-Vgs and Ig-Vgs characterizations for an nMOSFET device. The I_d-V_gs and I_g-V_gs experimental data are obtained by HP4156B semiconductor parameter analyzer, which are adopted for the extractions of series resistance R_sd, threshold voltage V_th, oxide thickness t_ox, effective channel length Leff, and the dopant concentration of the drain extension NDE.

After performing the I-V measurement, the first task is to extract the V_th for nMOSFET devices. The comparision between the V_th extracted by extrapolation line in the linear region (ELR) method and that by second-derivative (SD)

method is shown in Fig. 13, which indicates more obvious difference of V_th values with shorter channel devices. Because the R_sd extraction via the V_th values in ELR method shows more consistent results than that with the Vth

values extracted by SD method generally, the subsequently extraction procedures of Rsd and

µ

eff would use the Vth values extracted by ELR method.

Fig. 14 and 15 present the L_eff extraction results for the W/L = 1μm/0.1 μm nMOSFET device by both the channel-resistance method and the shift-and-ratio (S&R) method. The channel-resistance method fails because there is no explicit intersect point of the Rtot-L characteristics for different gate voltages, and the Leff

extraction results from the S&R method appear to be overestimated. Thus, we continue to try L_eff extraction with the capacitive method. The experimental C_gc(V_gs) curves for several nMOSFET devices with a largest width plotted in a logarithm scale are plotted in Fig. 16. The L_eff extracted by the constant ΔL method and the individual ΔL method are displayed in Fig. 17 and 18, respectively. The corresponding L_eff values for L = 1um are 61.57nm and 75.45nm. Furthermore, the EDT method is adopted for narrower and shorter devices under which the capacitive method can not work well. Fig. 19 demonstrates the example of EDT method for the W/L = 1μm/0.1 μm nMOSFET device, which leads to L_eff = 72nm by comparing the measured (triangular symbol) Ig-V_gs characteristics with the simulated (solid curve) under accumulation conditions. Subsequently, the statistical analysis of the relations between ΔL and gate length and width is shown in Fig. 20 and 21, respectively.

The figures reveal that the EDT method can preserve considerable accuracy for the narrower and shorter devices. Fig. 22 exhibits the L_eff behavior with different gate lengths. It must be noted that the difference between L_eff and L becomes larger with shorter channel length.

After finishing the Leff extraction, we proceed with the Rsd extraction by the constant-mobility method. As demonstrated in Fig. 23, the R_sd value for the W/L

= 1μm/0.1 μm nMOSFET device is extracted by estimating the value with the universal curve at high E_eff. Fig. 24, 25, and 26 show that the R_sd values apparently reduce with shorter devices, and have no visible dependence on the width and overlap length.

When the L_eff and R_sd are extracted further, we can accurately carry out the

µ

eff extraction for highly scaled nMOSFET devices accordingly. Fig. 27 displays the resulting

µ

eff curves of the W/L = 1μm/0.1μm nMOSFET device with raw data also shown are corrected L_eff , R_sd, and both L_eff & R_sd corrected. The variations of the peak mobility induced by overlap length for nMOSFET devices with different length and width are shown in Fig. 28 and 29, respectively. They illustrate that the mobility variations caused by overlap length are bigger with short devices but seem to be a weak function of the width. The variations of the mobility induced by R_sd at V_gs = 1.5V (higher E_eff) for nMOSFET devices with different length and width are also illustrated in Fig. 30 and 31. As can be clearly seen, the variations of the mobility result from the Rsd seemingly decrease with shorter length because the Rsd values reduce slightly with decreasing gate length. In addition, the R_sd induced mobility variations are connected with ΔL factor, rather than the width. At the end, the comparision between the raw and the corrected µ_eff values at V_gs = 1.5V are exhibited in Fig.

32 and 33 for different lengths and widths. The corrected µeff value for L = 0.1 µm nMOSFET device arises because the deviation caused by R_sd is worse than that of ΔL. However, with device length scaling, the deviation caused by ΔL is larger than that by Rsd for highly scaled devices. From Fig. 32 and 33, the µeff

deviations tend to increase with reduced device length; nevertheless, it appears that the deviations are independent of the device width.

Chapter 5 Conclusion

The novel key parameter extractions for highly scaled MOSFET devices have been systematically executed. First, the Rsd extraction with constant-mobility method neither considers the mobility dependence on channel length nor requires the precise values of mobility and channel length. Moreover, it provides immunity against process variation. Second, the problems of the L_eff extraction with capacitive method such as the gate leakage issue and the equipment detection limit, have been solved with the EDT method. Furthermore, for more accurate extraction of process parameters such as N_sub, N_poly, N_DE, Q_inv, and t_ox, the EDT method and split C-V measurement can complement each other.

Because of the above-mentioned reasons, the

µ

_eff eventually can be extracted accurately. Moreover, the extraction methods also furnish the convenient and fast approaches that do not need to perform measurements in a large device sample size.

References

[1] S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFET's,”

IEEE Electron Device Letters, vol. 18, no. 5, pp. 209-211, May 1997.

[2] L. F. Register, E. Rosenbaum, and K. Yang, “Analytic model for direct tunneling current in polycrystalline silicon-gate metal–oxide–semiconductor devices,” Applied Physics Letters, vol. 74, no. 3, pp. 457-459, January 1999.

[3] N.Yang,W.K. Henson, J.R.Hauser, and J.J.Wortman, “Modeling Study of Ultrathin Gate Oxides Direct Tunneling Current and Capacitance Measurements in MOS Devices,”

IEEE Transactions on Electron Devices, vol. 46, no. 7, pp. 1464-1471, July 1999.

[4] F. Lime, C. Guiducci, R. Clerc, G. Ghibaudo, C. Leroux, and T. Ernst, “Characterization of effective mobility by split C(V) technique in N-MOSFETs with ultra-thin gate oxides,” Solid State Electronics, vol. 41, pp. 1147-1153 (2003).

[5] Y. T. Hou, M. F. Li, Y. Jin, and W. H. Lai, “Direct tunneling hole currents through ultrathin gate oxides in metal-oxide-semiconductor devices,” Journal of Applied Physics, vol. 91, no. 11, pp. 258-264,January 2002.

[6] S. Severi, L. Pantisano, E. Augendre, E. S. Andrés, P. Eyben, and K. D. Meyer, “A Reliable Metric for Mobility Extraction of Short-Channel MOSFETs,” IEEE Transactions on Electron Devices, vol. 54, no. 10, pp. 2690-2698, October 2007.

[7] X. Liu, J. Kang, and R. Han, “Direct tunneling current model for MOS devices with ultra-thin gate oxide including quantization effect and polysilicon depletion effect,” Solid State Communications, vol. 125, pp. 219-223 (2003)

[8] J. Suiik, P. Olivo, and B. Riccb, “Quantum-Mechanical Modeling of Accumulation Layers in MOS Structure,” IEEE Transactions on Electron Devices, vol. 39, no. 7, pp.

[9] K. N. Yang, H. T. Huang, M. J. Chen, Y. M. Lin, M. C. Yu, S. M. Jang, Douglas C. H.

Yu, and M. S. Liang, “Characterization and Modeling of Edge Direct tunneling (EDT) Leakage in Ultrathin Gate Oxide MOSFETs,” IEEE Transactions on Electron Devices, vol. 48, no. 6, pp. 1159-1164,June 2001.

[10] D. W. Lin, M. L. Cheng, S. W. Wang, C. C. Wu, and M. J. Chen, “A Constant-Mobility Method to Enable MOSFET Series-Resistance Extraction,” IEEE Electron Device Letters, vol. 28, no. 12, pp. 1132-1134, December 2007.

[11] D. Fleury, A. Cros, K. Romanjekl, D. Roy, F. Perriert, B. Dumontt, and H. Brut,

“Automatic extraction methodology for accurate measurement of effective channel length on 65nm MOSFET technology and below,” IEEE International Conference on Microelectronic Test Structures, Tokyo, Japan, pp. 89-92, March 2007.

[12] J. G. J. Chern, P. Chang, R. F. Motta, and N. Godinho, “A New Method To Determine MOSFET Channel Length,” IEEE Electron Device Letters, vol. EDL-1, no. 9, pp.

170-173, September 1980.

[13] G. Niu, J. D. Cressler, S. J. Mathew, and S. Subbanna, “A Channel Resistance Derivative Method for Effective Channel Length Extraction in LDD MOSFET’s,” IEEE Transactions on Electron Devices, vol. 47, no. 3, pp. 648-650,March 2000.

[14] Yuan Taur, “MOSFET Channel Length ： Extraction and Interpretation,” IEEE Transactions on Electron Devices, vol. 47, no. 1, pp. 160-170, March 2000.

[15] M. Fathipour, E. Fathi, B. Afzal, and A. Khakifirooz, “An improved shift-and-ratio Leff

extraction method for MOS transistors with halo/pocket implants,” Solid State Electronics, vol. 48, pp. 1829-1832 (2004).

[16] C. W. Eng, W. S. Lau, Y. Y. Jiang, D. Vigar, K. C. Tee, L. Chan, V. S. W. Lim, and A.

Trigg, “Improving the Accuracy of Modified Shift-and-Ratio Channel Length Extraction Method Using Scanning Capacitance Microscopy,” Japanese Journal of Applied Physics,

vol. 43, no. 4B, pp. 1869-1872, 2004.

[17] Frank Stern, “Self-Consistent Results for n-Type Si Inversion Layers” Physical Review B, vol. 5, no. 12, pp. 4891-4899, June 1972.

[18] J. Maserjian and G. P. Petersson, “Tunneling through thin MOS structure：Depedence on energy (E-k),” Applied Physics Letters, vol. 25, no. 1, pp. 50-52, July 1974.

[19] A. O. Conde, F. J. G. Sanchez, J. J. Liou, A. Cerdeira, M. Estrada, and Y. Yue, "A review of recent MOSFET threshold voltage extraction methods," Microelectronics Reliability 42 (2002) pp.583–596.

[20] J. R. Hauser, "Extraction of Experimental Mobility Data for MOS Llevices," IEEE Transactions on Electron Devices, vol. 43, no. 11, pp. 1981-1988, November 1996.

[21] J.C. Guo, S. S. Chung, and C. C. Hsu, "A New Approach to Determine the Effective Channel Length and the Drain-and-Source Series Resistance of Miniaturized MOSFET's," IEEE Transactions on Electron Devices, vol. 41, no. 10, pp.

1811-1818,October 1994.

[22] K. Chen, H. C. Warm, J. Dunster, P. K. Ko, C. Hu, and M. Yoshida, "MOSFET Carrier Mobility Model Based on Gate Oxide Thickness, Threshold and Gate Voltages,"

Solid-State Electronics, vol. 39, no. 10, pp. 1515-1518, 1996.

[23] K. Romanjek, F. Andrieu, T. Ernst, and G. Ghibaudo, "Improved Split C–V Method for Effective Mobility Extraction in sub - 0.1µm Si MOSFETs," IEEE Electron Device Letters, vol. 25, no. 8, pp. 583-585,August 2004.

[24] K. N. Yang, H. T. Huang, M. J. Chen, Y. M. Lin, M. C. Yu, S. S. M. Jang, D. C. H. Yu, and M. S. Liang,"Edge Hole Direct Tunneling Leakage in Ultrathin," IEEE Transactions on Electron Devices, vol. 48, no. 12, pp. 2790-2795, December 2001.

W

L

_eff

L

_TN

L

_TN

L

_Gate

n

⁺

p-well

Oxide

V

_g

= -V

_DD

n

⁺

W

L

_eff

L

_TN

L

_TN

L

_Gate

n

⁺

p-well

Oxide

V

_g

= -V

_DD

n

⁺

W

L

_eff

L

_TN

L

_TN

L

_Gate

n

⁺

p-well

Oxide

V

_g

= -V

_DD

n

⁺

Fig. 1

R

_d

R

_s

R

_ch

L

_Gate

L

_eff

scaling

R

_d

R

_s

R

_ch

L

_Gate

L

_eff

tot sd

R R

R

_d

R

_s

R

_ch

L

_Gate

L

_eff

scaling

R

_d

R

_s

R

_ch

L

_Gate

L

_eff

tot sd

R R

Fig. 2

L

_eff

L

_Gate

n

⁺

p-well Oxide n

⁺

Source/Drain diffusion extensions L

_eff

L

_Gate

n

⁺

p-well Oxide n

⁺

Source/Drain diffusion extensions

Fig. 3

Gate Length L (µm)

Measured T o tal Resistance R

tot

(Ω )

ΔL

R

_ext

V

^g

=6 V V

^g

=8 V

V

^g

=1 2V Extracting L

_eff

with

Channel - Resistance Method

Gate Length L (µm)

Measured T o tal Resistance R

tot

(Ω )

ΔL

R

_ext

V

^g

=6 V V

^g

=8 V

V

^g

=1 2V Extracting L

_eff

with

Channel - Resistance Method

Fig. 4

Energy reference point

SiO₂ n⁺-poly gate at accumulation condition

Triangular Potential n⁺-poly gate at accumulation condition

~~

2DEG

~ ~ ~ ~

n⁺-Poly Gate SiO₂ Source/ Drain Diffusion Extension

qV

_GD

qV

_DE

qV

_ox

= qt

_ox

F

_ox

qV

_poly

E

_c

@ E

_fn

E

_v

E

_c

E

_v

E

₁

E

_fn

I_EDT

Q

2DEG

~ ~

~ ~ ~ ~ ~ ~

n⁺-Poly Gate SiO₂ Source/ Drain Diffusion Extension

qV

_GD

qV

_DE

qV

_ox

= qt

_ox

F

_ox

qV

_poly

E

_c

@ E

_fn

E

_v

E

_c

E

_v

E

₁

E

_fn

I_EDT

Q

Fig. 6

~~ ~~

n⁺-Poly Gate SiO₂ S/D Diffusion Extension

EF

n⁺-Poly Gate SiO₂ S/D Diffusion Extension

EF

F

_ox

, t

_ox

, N

_DE

Input

variable parameters

V

_ox

, Q, V

_DE

, F

_Si

E

₁

T

_WKB

, T

_R

, N

_DE

V

_poly

V

_g

Output J

_EDT

simulated results

F

_ox

, t

_ox

, N

_DE

Input

variable parameters

V

_ox

, Q, V

_DE

, F

_Si

E

₁

T

_WKB

, T

_R

, N

_DE

V

_poly

V

_g

Output J

_EDT

simulated results

Fig. 8

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0

25 50 75 100 125 150 175

at V

_bs

= 0V at V

_bs

= -0.5V at V

_bs

= -1V at V

_bs

= -1.5V

Raw Data

nMOSFET

W/L=1

μ

m/0.1

μ

m

,

V

_ds

=0.025V

E

_eff

(MV/cm)

μ ef f (c m

2

/V s)

Fig. 9

V _ds V _gs

R _D R _S

I _d V _gs ’

V _ds ’ V _ds V _gs

R _D R _S

I _d V _gs ’

V _ds ’

Fig. 10

I_g- V_gsData

C-V Measurement I-V MeasurementI-V Measurement

L_eff L_eff

-2 -1 0 1 0

1 2

3

nMOSFET W/L=1

0μ

m/1

μ

m

C

_measured

C

_simulated

Gate Voltage V_gs (V) Capacitance (μF/cm2 )

N

poly

= 4.0x10

¹⁹

/cm

³

N

sub

= 4.0x10

¹⁷

/cm

³

t

ox

= 1.215 nm

Fig. 12

0.05 0.06 0.07 0.08 0.09 0.10 0.15

0.20 0.25 0.30 0.35 0.40

nMOSFET V

_ds

=0.025V

Gate Length L(μm) Threshold Voltage V th (V)

W = 1

μ

m with ELR method W = 1

μ

m with SD method W = 0.6

μ

m with ELR method W = 0.6

μ

mwith SD method W = 0.24

μ

m with ELR method W = 0.24

μ

m with SD method

Fig. 13

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0

1000 2000 3000 4000 5000

Measured Total Resistance R tot(Ω)

nMOSFET

W =1

μ

m V

_ds

=0.025V

Gate Length L (μm)

at V

_gs

= 0.6V

at V

_gs

= 0.9V at V

_gs

= 1.2V at V

_gs

= 1.5V

Fig. 14

0.05 0.06 0.07 0.08 0.09 0.10 0.05

0.06 0.07 0.08 0.09 0.10 0.11 0.12 0.13 0.14 0.15

L

eff

extraction with S&R method nMOSFET

W =1

μ

m V

_ds

=0.025V

Effective Channel Length L eff(μm)

Gate Length L (μm)

Fig. 15

-1.0 -0.5 0.0 0.5 1.0 10⁰

10¹ 10²

Gate Voltage V_gs (V)

nMOSFET

W = 1

0μ

m L = 1

μ

m L = 0.24

μ

m L = 0.1

μ

m

Gate-to-Channel Capacitance C gc(fF)

Fig. 16

0.0 0.2 0.4 0.6 0.8 1.0 1.2 0

20 40 60 80 100 120 140 160 180

Gate Length L (μm)

nMOSFET

W = 1

0μ

m

Max (C gc

)

(fF)

Exp. Data

Linear Fit of Exp. Data

Overlap Length

δ

L~38.43nm

is extracted by constant

δ

L method L

_eff

= 61.57nm for L = 0.1

μ

m

Fig. 17

0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 25

30 35 40 45 50

Overlap Length δL (nm)

Gate Length L(μm)

Overlap Length δL~24.55nm for L=0.1μm is extracted byindividual δLmethod L_eff = 75.45nm for L = 0.1 μm

nMOSFET W = 1

0μ

m

Fig. 18

-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 10^-11

10^-10 10^-9 10^-8 10^-7 10^-6 10^-5

L

_eff

~ 72.0nm

Gate Voltage V_gs (V) Edge Direct Tunneling current I g(A)

I

_g,measured

I

_g,simulated

t

ox

= 1.215 nm N

DE

= 1.0x10

¹⁹

/cm

³

L

TN

= 14.0 nm

δ

L = 28.0nm nMOSFET

W/L = 1

μ

m/0.1

μ

m

Fig. 19

0.05 0.06 0.07 0.08 0.09 0.10 10

15 20 25 30 35 40 45

Gate Length L (μm)

t

ox

= 1.215 nm

N

DE

= 1.0x10

¹⁹

/cm

³

nMOSFET

Gate

Width = 1

μ

m

Gate

Width = 0.6

μ

m

Gate

Width = 0.24

μ

m

Overlap Length δL (nm)

Fig. 20

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 10

15 20 25 30 35

40 Gate

Length = 0.1

μ

m

Gate

Length = 0.065

μ

m

Gate

Length = 0.05

μ

m

Gate Width W (μm)

Overlap LengthδL (nm)

t

_ox

= 1.215 nm N

DE

= 1.0x10

¹⁹

/cm

³

nMOSFET

Fig. 21

0.05 0.06 0.07 0.08 0.09 0.10 0.01

0.02 0.03 0.04 0.05 0.06 0.07 0.08

nMOSFET

Gate

Width = 1

μ

m

Gate

Width = 0.6

μ

m

Gate

Width = 0.24

μ

m

Effective Channel Length L eff(μm)

Gate Length L(μm)

Fig. 22

0.6 0.8 1.0 1.2 1.4 0

200 400 600 800 1000 1200 1400 1600 1800 2000

Series Resistance R sd(Ω−μm)

Gate Voltage V_gs (V)

at V

_bs

= -0.5V

at V

_bs

= -1V at V

_bs

= -1.5V

R

_sd

~ 279.79 (Ω−μ m)

nMOSFET

W/L=1

μ

m/0.1

μ

m V

_ds

=0.025V

Fig. 23

0.05 0.06 0.07 0.08 0.09 0.10 100

150 200 250 300 350 400

nMOSFET V

_ds

=0.025V

Gate

Width = 1

μ

m

Gate

Width = 0.6

μ

m

Gate

Width = 0.24

μ

m

Gate Length L(μm) Series Resistance R sd(Ω−μm)

Fig. 24

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 100

150 200 250 300 350 400

nMOSFET V

_ds

=0.025V

Gate

Length = 0.1

μ

m

Gate

Length = 0.065

μ

m

Gate

Length = 0.05

μ

m

Gate Width W (μm) Series Resistance R sd(Ω−μm)

Fig. 25

22 24 26 28 30 32 34 100

150 200 250 300 350 400

nMOSFET W = 1

μ

m

Overlap Length δL (nm) Series Resistance R sd(Ω−μm)

Fig. 26

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0

50 100 150 200 250

300

R

_sd

~ 279.79 Ω L

_eff

~ 0.072 μ m

Raw data Leff corrected Rsd corrected L_eff & R_sd corrected

nMOSFET

W/L=1

μ

m/0.1

μ

m

,

V

_ds

=0.025V

E

_eff

(MV/cm)

μ ef f (c m

2

/Vs )

Fig. 27

-50.89%

-27.85%

-67.91%

0.05 0.06 0.07 0.08 0.09 0.10

0

0.05 0.06 0.07 0.08 0.09 0.10

0

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0

50 100 150 200 250 300 350 400 450 500 550

nMOSFET V

_ds

=0.025V

Gate Width W (μm)

P e a k M o b ility (c m

2

/V s )

^{L = 0.1μmw/o Leff corrected}

L = 0.1μmwith L_eff corrected L = 0.065μmw/o L_eff corrected L = 0.065μmwith L_eff corrected L = 0.05μmw/o L_eff corrected L = 0.05μmwith L_eff corrected

Fig. 29

+54.21%

+57.68%

+44.29%

0.05 0.06 0.07 0.08 0.09 0.10

0

0.05 0.06 0.07 0.08 0.09 0.10

0

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0

50 100 150 200 250 300 350 400

nMOSFET V

_ds

=0.025V

L = 0.1μmw/o R_sd corrected L = 0.1μmwith R_sd corrected L = 0.065μmw/o R_sd corrected L = 0.065μmwith R_sd corrected L = 0.05^μmw/o R_sd corrected L = 0.05μmwith R_sd corrected

Gate Width W (μm)

M o b ility

@ V gs=1.5V(cm2 /Vs)

Fig. 31

-24.22%

+13.14%

-53.83%

0.05 0.06 0.07 0.08 0.09 0.10

0

0.05 0.06 0.07 0.08 0.09 0.10

0

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0

50 100 150 200 250 300 350 400

nMOSFET V

_ds

=0.025V

L = 0.1μmraw

L = 0.1μmR_sd, L_eff corrected L = 0.065^μmraw

L = 0.065μmR_sd, L_eff corrected L = 0.05μmraw

L = 0.05^μmR_sd, L_eff corrected

Gate Width W (μm)

M o b ility

@ V gs=1.5V(cm2 /Vs)

Fig. 33

在文檔中 針對高度微縮金氧半場效電晶體的參數精確萃取方法 (頁 27-0)