針對高度微縮金氧半場效電晶體的參數精確萃取方法

國

立

交

通

大

學

電機學院微電子奈米科技產業研發碩士班

碩

士

論

文

針對高度微縮金氧半場效電晶體的參數精確萃取方法

Accurate Parameter Extraction Methods for Highly Scaled MOSFETs

研 究 生：陳彥銘

指導教授：陳明哲 教授

針對高度微縮金氧半場效電晶體的參數精確萃取方法

Accurate Parameter Extraction Methods for Highly Scaled MOSFETs

研 究 生：陳彥銘 Student：Yen-Ming Chen

指導教授：陳明哲 Advisor：Prof. Ming-Jer Chen

國 立 交 通 大 學

電機學院微電子奈米科技產業研發碩士班 碩 士 論 文

A Thesis

Submitted to College of Electrical and Computer Engineering National Chiao Tung University

in partial Fulfillment of the Requirements for the Degree of

Master in

Industrial Technology R & D Master Program on Microelectronics and Nano Sciences

July 2008

Hsinchu, Taiwan, Republic of China

針對高度微縮金氧半場效電晶體的參數精確萃取方法

學生：陳彥銘 指導教授：陳明哲博士 國立交通大學電機學院產業研發碩士班 摘 要 這篇論文主要列出幾種特別適合高度微縮之金氧半場效電晶體的新穎 參數萃取方法。首先，三個關鍵製程參數（即是閘極多晶矽摻雜濃度、閘 極氧化物物理厚度，以及通道摻雜濃度）能經由兩種方法的電容-電壓相符 萃取出來：一種是 Shrödinger-Poisson 方程式解算以及另一種三角位能近似 法。然後使用一種新的常數-遷移率方法萃取源極/汲極串聯電阻，此方法不 像傳統方法般複雜，只需要對單一測試元件作簡單直流量測即可。我們進 而能由改良的方法論達成定量地區別遮罩級通道長度跟冶金級通道長度。 甚至源極/汲極擴張以及其摻雜濃度也能用邊緣直接穿隧技術萃取得。最 終，通道中的載子遷移率以及臨界電壓都能直接準確地萃取出來。

Accurate Parameter Extraction Methods for Highly Scaled MOSFETs

Student：Yen-Ming Chen Advisors：Dr. Ming-Jer Chen

Industrial Technology R & D Master Program of Electrical and Computer Engineering College

National Chiao Tung University

Abstract

This thesis mainly addresses several novel parameter extraction methods that are particularly suitable for highly scaled MOSFETs. First of all, the three key process parameters (namely, the gate polysilicon doping concentration, the gate oxide physical thickness, and the channel doping concentration) are extracted via C-V fitting by means of the two methods: one of the Shrödinger-Poisson equation solving and one of the triangular potential approximation. Then a new constant-mobility method is adopted to extract the source/drain series resistance Rsd, which, unlike the conventional counterparts, requires only simple DC measurements on a single test device. Once Rsd is extracted, we can quantitatively distinguish between the gate length at the mask level and the channel metallurgical length, which is achieved with the improved methodology. Even the source/drain extension and its doping concentration can be extracted using the edge direct tunneling technique. Finally, the carrier mobility in the channel, as well as the threshold voltage, can be straightforwardly extracted.

誌

謝

在碩士兩年多的生涯裡，從碩一專注修課的歲月、碩二遭逢幾位親人 相繼辭世哀慟的日子，以迄畢業之前步入半工半讀過渡的時光，當中要感 謝很多人的鼓勵、協助、輔導與支持。能夠完成這篇論文，首先由衷感謝 我的指導教授陳明哲老師，在我研究毫無頭緒時的方向指引、遭遇瓶頸時 的循循善誘、慌張軟弱時的體察開導；甚至准假參與親人悼念習俗時的關 懷開釋，在在讓我心裡充滿無盡的感激。 在實驗室做研究時，由於實驗室夥伴的用心引導，讓我從中學到不少 珍貴的資產。謝振宇學長在電流量測上的啟蒙以及在論文上「用力」的指 導；李建志學長的義氣照顧、教導及關心；許智育學長在電流、電容量測 上的經驗傳承；呂立方在處理數據及模擬上的協助與建議；林以唐跟梁惕 華在寫程式建立模型上的幫助；周佳弘在儀器出問題時的盡力協助；也要 感謝李韋漢、湯侑穎、簡鶴年、宋東壕、陳又正、陳以東等夥伴平時在日 常生活上的輔助，讓我沉悶的實驗室生活多了些溫暖。 最後要感謝的是，一路上在背後支持的家人。如果說實驗室是提供我 研究上的幫助，而家人就是提供我心理上的建設。在研究過程遇到困難、 著急及不知所措時，家人總會給予心理上的安撫，進而提供實際行動上的 建議，讓我在跌跌撞撞的研究過程中，總能安然渡過。 謹以此篇短小的感言，表達我心中無止盡的感謝，獻給每一位在我研 究生涯中，接觸到的每個人，感謝您們。

Content

Abstract (Chinese) ……… i Abstract (English) ……… ii Acknowledgement ……… iii Content ……… iv Figure Captions ……… v Chapter 1 Introduction……… 1

Chapter 2 Effective Channel Length Extraction………. 4

2.1 Definition of Effective Channel Length………. 4

2.2 Classical Current-based Leff Extraction Methods……. 4

2.2.1 Channel-Resistance Method………... 4

2.2.2 Shift-and-Ratio Method……….. 5

2.3 Capacitive Method………. 7

2.3.1 Constant ΔL Method……… 8

2.3.2 Individual ΔL Method……….. 8

2.4 Edge Direct Tunneling and Modeling Description…… 9

Chapter 3 Key Parameters Extraction………. 14

3.1 Threshold Voltage Extraction……… 14

3.2 Series Resistance Extraction……….. 14

3.3 Effective Mobility Extraction………. 17

Chapter 4 Experimental Data and Interpretations………... 20

Chapter 5 Conclusion……….. 23

Figure Captions

Fig. 1 Schematic diagram showing the edge direct tunneling leakage current path for an nMOSFET device under accumulation conditions...27

Fig. 2 Schematic description of the increasingly important Rsd portion of the

total resistance for MOSFET devices during the scaling. ...28

Fig. 3 Schematically shown Leff defined as the distance between the source

and drain diffusion extensions at the silicon surface. ...29

Fig. 4 Schematic illustration of Channel - Resistance Leff extraction method

through a relation between measured linear region resistance Rtot and

gate length. ...30

Fig. 5 The detailed triangular potential profile for nMOSFET devices...31

Fig. 6 Schematic energy band diagram for an n+ poly gate/SiO2/drain

extension structure showing the voltage balance relationship in accumulation. ...32

Fig. 7 Schematic of the band diagram for edge direct tunneling from accumulated n+ poly gate to depleted drain diffusion extension. The accumulated well is modeled with a triangular potential one. The wave function for electrons is partially reflected at each potential discontinuity. ...33

Fig. 9 The relations between the measured µeff and the Eeff at the Si/ SiO2

interface under different Vbs conditions. The µeff converges toward one

universal curve when Eeff is sufficiently high. ...35

Fig. 10 Schematic illustration of the Rsd equivalent circuit along with the cross

section of an nMOSFET device. ...36

Fig. 11 Depicted flowchart summarizing the procedures of µeff extraction. ....37

Fig. 12 Comparsion of the measured (triangular symbol) and simulated (solid curve) C-V characteristics of an nMOSFET device. ...38

Fig. 13 The Vth extraction results from ELR method and SD method for

different nMOSFET devices. ...39

Fig. 14 The Le f f extraction result of an nMOSFET device with

Channel-Resistance method. ...40

Fig. 15 The Leff extraction result of an nMOSFET device with shift-and-ratio

method. ...41

Fig. 16 The experimental Cgc(Vgs) curves for several nMOSFET devices as

plotted in a logarithm scale. ...42

Fig. 17 The ΔL extraction result of an nMOSFET device with constant ΔL

Fig. 18 The ΔL extraction result of an nMOSFET device using individual

ΔL method with a proportionality relationship...44

Fig. 19 Comparsion of the measured (triangular symbol) and simulated (solid curve) Ig-Vgs characteristics under accumulation conditions of an

nMOSFET device...45

Fig. 20 The relations between ΔL of nMOSFET devices resulting from EDT

method and gate length. ...46

Fig. 21 The relations between ΔL of nMOSFET devices resulting from EDT

method and gate width. ...47

Fig. 22 The Leff behavior for nMOSFET devices resulting from EDT method.

...48

Fig. 23 Vgs dependences of Rsd under different Vbs condtions. Erroneous Rsd

values appear in the low Vgs region because the "constant mobility"

criterion is not satisfied when the Eeff is not sufficiently high. ...4 9

Fig. 24 Plot of the Rsd versus gate length of the nMOSFET devices...50

Fig. 25 Plot of the Rsd versus gate width of the nMOSFET devices...51

Fig. 26 Statistical analysis of the Rsd variations with different SDE overlap

Fig. 27 The µeff curves of the W/L = 1µm/0.1µm nMOSFET device with raw

data, Leff corrected, Rsd corrected, and Leff & Rsd corrected. ...5 3

Fig. 28 Displaying the peak mobility variations induced by ΔL versus gate

length of the W = 1 µm nMOSFET devices...54

Fig. 29 Statistical analysis of the peak mobility variations induced by ΔL

with different gate width devices. ...55

Fig. 30 Displaying the µeff @Vgs = 1.5V variations induced by Rsd versus gate

length of the W = 1 µm nMOSFET devices...56

Fig. 31 Statistical analysis of the µeff @Vgs = 1.5V variations induced by Rsd

with different gate widths...57

Fig. 32 Comparision between the raw and the corrected µeff @Vgs = 1.5V

values versus gate length of the W = 1 µm nMOSFET devices. ...5 8

Fig. 33 Comparision between the raw and the corrected µeff @Vgs = 1.5V

Chapter 1

Introduction

In today's integrated circuit industry, the metal-oxide-semiconductor (MOS) devices are moving toward nanoscale to reduce cost and improve performance. In order to scale MOS devices to smaller dimensions while maintaining good control of the short-channel effect, the conventional transistor scaling theory requires that the gate oxide thickness (tox) be reduced as the minimum channel

length is scaled down. According to the National Technological Roadmap for Semiconductors (NTRS), the scaling trend for gate dielectrics is such that for sub - 100 nm generation devices, an equivalent gate oxide thickness of less than 2.0 nm will be required. This gives rise to several issues such as excess gate leakage current, degradation of mobility, C(V) and Id(Vg) characterization

difficulties, etc [1]-[4].

The extraction of key MOS devices parameters such as the effective channel length (Leff), the source/drain (S/D) series resistance (Rsd) and the

mobility of highly scaled devices are of fundamental importance for the analysis of developed MOSFET technologies. However, with the scaling of MOS devices, the increasing gate leakage current will cause more problems such as C-V measurement, the standby power consumption of a highly integrated chip, etc [1]-[6]. The leakage current flowing across the MOS structure usually includes Fowler-Nordheim (FN) tunneling current and direct tunneling (DT) current. With thinning oxide layer, direct tunneling bocomes the main mechanism for the leakage current [7]. By this reason, a reliable and computation efficient physical model for characterizing the direct tunneling current of devices is necessary.

condition, there is no inversion layer formed between the source and drain diffusion extension under the oxide/silicon-substrate interface. The dominant off-state leakage component of electron from the polysilicon to underlying n-type S/D diffusion extension is called edge direct tunneling (EDT). In order to study the edge direct tunneling current in MOS devices, there are two approaches such as the self-consistent Shrödinger-Poisson equation and the triangular potential approximation. Under the accumulation conditions, the electrons are confined in the narrow potential well close to the accumulated semiconductor interface. The tight confinement leads to a splitting of the energy levels into subbands for motion in the direction normal to the silicon surface, which must be treated quantum-mechanically (QM). That is, the electronic properties of the accumulation layer behave as two-dimensional electron gas (2DEG) [1], [8]. The EDT model used in this thesis is based on the triangular potential approximation for the first time derived for the oxide field (Fox) at the

gate edge by accounting for electron subband in the quantized accumulation poly-silicon surface. This model relates the Fox to gate-to-drain voltage (VDG),

oxide thickness (tox), and doping concentration of drain diffusion extension (NDE)

[9]. Once Fox is known (input), EDT I-V data will be reproduced consistently

with the model. The tunneling path size (W × LTN) and the NDE will be extracted

with properly fitting. Finally, the Leff is gotten with the formula：

(1.1)

L

_eff

=

L

−

2L

_TN

In MOSFET devices, the S/D series resistance Rsd leads to excess potential

drop and degraded drive capacity. As MOSFET devices scale, the Rsd portion of

the total resistance in MOSFET devices increases and consequently the drive current degradation is more serious in highly scaled devices as shown in Fig. 2. The traditional current-based Rsd extraction methods based on the hypothesis

that the carrier mobility or the channel dopant concentration is independent of the channel length might be unsuitable for today's MOSFET technology because process variations may induce nonuniform channel dopant profiles. In order to extract Rsd accurately, the constant-mobility method proposed in [10] that

provides immunity against process variation and needs not to know the carrier mobility and Leff is adopted. As the Leff and Rsd are extracted accordingly, the

Chapter 2

Effective Channel Length Extraction

2.1 Definition and Meaning of Effective Channel Length

The effective channel length (Leff) - defined by the inversion layer length is

a measure of the “effective” current carrying capability of the MOSFET device [6], [11]. Fig. 3 shows schematically that Leff is also defined as the distance

between the source and drain diffusion extensions at the silicon surface. In addtion, Leff is an important parameter for both process monitor and device

design of MOSFET devices.

2.2 Classical Current-based Leff Extraction Methods

2.2.1 Channel-Resistance Method

For MOSFET devices operated in linear region (low-drain bias region), the gate-controlled current is given by

(2.1)_{gs th ds ds} eff ox eff d

C

V

V

V

V

I

= μ

×

×

⎜

−

−

⎟

2

1

L

W

⎠

⎞

⎝

⎛

When biased in the linear region and slightly below threshold voltage region of MOSFET devices, the formula (2.1) can be approximated to the form

(2.2)

(

gs th

)

ds eff ox eff d

V

V

L

C

I

= μ

×

×

W

V

−

The channel resistance of a MOSFET device in the linear region is therefore proportional to the channel length as given by [12]

(2.3)

)

V

(V

W

C

L

R

_ch

=

th gs ox eff eff

−

×

×

×

μ

The total resistance of a MOSFET device reads

(2.4) _{ext ch} d ds total

R

R

R

=

=

+

I

V

where Rext includes the contact resistance, series resistance, and other resistances

involved in measurement equipments.

After measuring the Id-Vgs characteristics for MOSFET devices with

different channel length, extracting the total resistances with different gate bias and then plotting the relation between total resistance and channel length under different gate biases are shown in Fig. 4. By an extrapolation from the intersection point, we can eventually get the channel length reduction ΔL on the intercept point on the x-axis. And the Rext can be obtained at the intercept on

the y-axis as in Fig. 4.

Although this Leff extraction method looks easy, but it may fail for highly

scaled MOSFET devices with some issues. First, this method assumes the effective mobility is independent of the channel length. This leads to unrealistic values for the extracted effective channel length in short-channel devices. Second, the literature [13] points out that the lines in Fig. 4 are difficult to intersect at a certain point, thus causing unprecise results.

2.2.2 Shift-and-Ratio Method

This method is based on the same channel resistance concept by assuming the effective mobility to be a common function of (Vgs-Vth) for MOSFET

(2.5)

R

o_tot

( )

V

_gs

=

R

_sd

+

L

o_eff

f V

(

_gs

−

V

_tho

)

(2.6)

_R

_toti

( )

_V

_gs

=

_R

_sd

+

_L

i_eff

_f

(

_V

_gs

−

_V

_thi

)

where superscript i represents the short-channel device and o refers to the long-channel device. Further differentiating equations (2.5) and (2.6) with respect to Vgs and neglecting the Rsd part under the assumption that Rsd is either

independent or a weak function of Vgs so its derivation can be ignored, we

obtain (2.7)

( )

(

)

gs o th gs o eff gs o tot gs o

V

V

V

L

S

=

V

R

V

d

df

d

d

−

=

(2.8)

( )

(

)

gs i th gs i eff gs i tot gs i

V

V

V

L

S

=

V

R

V

d

df

d

d

−

=

The ratio of (2.7) to (2.8) is (2.9)

( )

gs i th gs i eff gs o th gs o eff gs i gs o gs

V

)

V

(V

L

V

)

V

(V

L

V

S

V

S

V

r

=

d

df

d

df

−

−

=

)

(

)

(

with equation (2.9), the So(Vgs) and Si(Vgs) become simliar functions if Vto=Vti

and Leffi could be easily extractd from the ratio So(Vgs)/ Si(Vgs) = Leffo / Leffi @ L/

Leffi. However, Vto generally is not equal to Vti. By this reason, this method

(2.10)

(

)

)

(

)

(

min gs i gs o gs min

V

S

V

S

V

,

r

δ

δ

−

≡

After meeting the minimum standard direvation of r(δ, Vgs) with δ = δmin, Leffi

can be extracted by (2.11) _i eff o i min

r

=

≅

eff o eff

L

L

L

L

This method is questionable for highly scaled MOSFET devices, especially in the low-Vgs regime because the series resistance becomes a strong function of

Vgs. Moreover, the assumption such as the invariance of the effective mobility

with the channel length of the MOSFET devices tends to yield unreasonable high values of Leff for highly scaled MOSFET devices [15]. In the citation [16],

it is also pointed out that this method fails for MOSFET devices with halo/pocket implants.

2.3 Capacitive Method

This method introduced in [11] has two ways to extract Leff：constant ΔL

method and individual ΔL method. They all measure the gate-to-channel capacitance Cgc(Vgs) which is proportional to the effective channel area. The

authors in [11] indicate that this Cgc(Vgs) measurement has no requirements for

any de-embedding structure to get rid of parastic capacitance during Cgb(Vgs)

measurements. We can only set the maximum gate-to-channel capacitance, max(Cgc), as a reference point of each curve and start Leff extraction with the

2.3.1 Constant ΔL Method

This method assumes that the channel length reduction ΔL is independent of channel length L, which can be extracted by a linear regression on the max(Cgc) - channel length L plot. Then the value of ΔL can be created at the

intercept between the regression linear and the L-axis. The ΔL is determined through the following expression

(2.12)

C

gc

=

W

×

C

ox

×

(L

−

ΔL)

It is easy to extract the ΔL with this method, but there would be an error on Leff which is strongly linked to the relevance of the ΔL linearity assumption.

Even though this issue exists in this method, however, it is just the choice when we do not have a long enough MOSFET device as reference.

2.3.2 Individual ΔL Method

This ΔL extraction using the longest MOSFET device as reference and extracting an individual ΔL for each MOSFET device from a proportionality relationship which can be written in the form

(2.13)

)

max(C

)

max(C

L

L

−

×

=

ΔL

_ref gc * gc ref eff * *

The authors in [11] assert this method has high accuracy with long-enough MOSFET devicess as reference (error due to this assumption Lref @ Leffref being

about 2 % for a 1µm long reference MOSFET device, and 0.2 % for a 10µm long one).

While the capacitive methods in [11] provide high accuracy and simple process with no assumption regarding the mobility, it might encounter difficulties to extract effective channel length with these methods on highly scaled MOSFET devices with ultra-thin oxide due to the huge gate leakage and the equipment detection limit (usually the limited minimum device area @ 0.2 µm2).

2.4 Edge Direct Tunneling and Modeling Description

The EDT (edge direct tunneling) method in this thesis is based on the triangular potential approximation. The detailed triangular potential profile for nMOSFET devices is schematically shown in Fig. 5. When MOSFET devices are operated under accumulation or inversion conditions, corresponding band bending at n+ poly-gate surface or silicon-substrate surface can be characterized by a triangle-like electrostatic potential well. Replacing the electrostatic potential in Shrödinger wave equation with the triangular potential leads to the Airy equation with solutions, which is called the triangular potential approximation method. We can derive the quantized energy of the first subband directly with this approximation [9], [17]

(2.14) 2/3 Si ox 1/3 z 2 1

8

9π

2m

E

=

_⎜⎜

=

_⎟⎟

_⎜⎜

F

_⎟⎟

⎠

⎞

⎝

⎛

⎠

⎞

⎝

⎛

ox

ε

qε

The voltage balance relationship for an nMOSFET device operated under accumulation conditions as illustrated in Fig. 6, can be expressed as

where VFB is the flat-band voltage, Vox ＝ toxFox is the potential drop across the

oxide, Vpoly is polysilicon depletion potential drop, and VDE is the band bending

in the drain extention region. The accumulated charge Q available for the tunnel process mainly populates in the first subband E1 due to the lowest quantized

energy dominating. This sheet charge density Q here is modeled as field induced and related to the number of occupied subband states, which can build up the charge conservation relationship [9]

(2.16) _ox

(

_fn

)

₂d

π

m

E

E

Q

=

ε

=

q

=

η

F

_ox

−

₁

where Efn is the quasi-Fermi level in the n+-poly gate and η is the degeneracy

factor. By applying the lowest subband approximation to the accumulated n+-poly gate and the depletion approximation to the drain diffusion extention, we get [9] (2.17)

q

η

q

F

ε

V

≅

=

+

q

ox 1

E

m

π

E

d 2 2 ox fn poly

=

(2.18) DE Si 2 2 DE

N

2

V

=

ox

ε

q

F

ε

_ox

where NDE is the dopant concentration of the drain diffusion extention. For

<100> oriented n+-polysilicon grains, mz=0.98mo, md=0.19mo, and η=2 were

adopted to approximate the band structure [2]. The edge tunneling current here is modeled by incorporating the accumulation layer quantization effect with a finite potential barrier height as the boundary condition and choosing a modified Wentzel-Kramers-Brillouin (WKB) method [2] to calculate the electron tunneling probability. Then within the effective mass approximation, the

tunneling probability can be expressed as

(2.19)

T

=

T

_WKB

×

T

_R

where TWKB is the usual WKB approximation of the tunneling probability for

slowly varying potentials, and TR is the correction factor taking into account the

reflections from potential discontinuities. The SiO2 band-gap dispersion relation

is modeled as the Franz-type E-k dispersion relation [18]

(2.20)

_2m

=

γ

=

E

⎜ −

_E

⎟

⎟

⎠

⎞

⎜

⎝

⎛

g ox ox ox 2 ox 2

_E

1

κ

=

(2.21) ox ox

m

2γ

γ'

1

ν

=

Here kox and vox are the purely imaginary wave vector and group velocity of

electrons within the oxide gap energy, respectively. Eox is the magnitude of the

electron energy with respect to the oxide conduction band edge, mox = 0.61mo is

the effective mass in the oxide based on the Franz-type dispersion relationship, and Eg @ 9 eV is the band gap for SiO2. With these conditions shown in Fig. 7,

TWKB is given by [2]

⎟

⎠

⎞

⎜

⎝

⎛−

=

∫

tox 0 ox WKB

exp

2

T

k

dx

(2.22)

where qψcat and qψan are the net barrier heights for the electrons at the cathode

(

)

_⎥

⎥

⎦

⎤

⎢

⎣

⎡

+

= = cat ox an ox E E ' -1 g ' ox g

γ

sin

E

γ

2γ

2m

E

φ φ q q ox

qF

=

⎢

=

4

exp

and anode interfaces, respectively. They are expressed as

(2.23)

q

φ

cat

= q

χ

c

−

(

E

1

+

E

2

)

(2.24)

_q

_q

(

)

where qχc @ 3.15eV is the discontinuity between the silicon and the SiO2

conduction bands [2],[3]. The correction factor TR is obtained by considering

reflections from the material interfaces as

(2.25)

where vSi,^(E1) and vSi,^(E1+qVox) are the interface-normal component group

velocities of the electrons incident onto and leaving from the oxide, respectively. With the oxide potential drop Vox, vox(ψcat) and vox (ψan) are the imaginary

group velocities of the electrons at the cathode and anode side within the oxide, respectively. The tunneling lifetime of the electrons from the lowest subband can be connected with the tunneling probability, as defined below [3]

(2.26)

With the established relation between the accumulated charge and the tunneling lifetime to oxide field, the edge direct tunneling current can be calculated analytically with the estimated effective edge-tunneling area ( LTN ×

W )： 1 1 1

E

T

τ

×

=

π=

ox

F

q

χ

_{c 1 2 ox} an

=

−

E

E

t

φ

+

−

(

) (

)

(

)

( ) (

)

( )

(

)

(

)

2 _an ox ox 1 2 Si, an ox ox 1 Si, cat 2 ox 1 2 Si, ox 1 Si, R

t

E

t

E

4

E

E

4

φ

cat

T

φ

φ

φ

υ

qF

q

q

qF

υ

q

q

υ

ox ox

ν

ν

ν

ν

+

+

υ

+

×

+

_⊥ ⊥ ⊥ ⊥

=

(2.27)

I

_EDT

=

×

(

)

where LTN is the estimated value of the drain diffusion extension length and W

is the channel width of the MOSFET device. In conclusion, the process flow for this EDT model operation is drawn in Fig. 8. With IEDT fitting to the

experimental data, LTN can be evaluated, leading to quantified ΔL：

(2.28)

W

L

τ

Q

TN 1

×

L 2L

Δ

=

_TN

Like the capacitive method, this EDT method also has no assumption regarding the mobility. It might be feasible to extract Leff for highly scaled

MOSFET devices with the EDT method becauce the EDT method has no apparent equipment detection limit which is the major problem for the capacitive method. In addition, the EDT method was involved with the huge leakage current which is the universal phenomenon for highly scaled MOSFET devices with ultra-thin oxide.

It must be noted that the above-mentioned EDT model is for nMOSFETs because the major objects examined in this thesis are nMOSFETs. However, the framework of the EDT model for pMOSFETs is similar to that for nMOSFETs except for the complicated effective mass of hole which is the major carrier of pMOSFETs and the energy band structure [24].

Chapter 3

Key Parameters Extraction

3.1 Threshold Voltage Extraction

Before extracting the series resistance and effective mobility, the first job is to extract the threshold voltage (Vth). For MOSFET devices, the Vth is a

fundamental parameter which represents the onset of the noticeable drain current flow, and is also recognized as the critical gate voltage at which the transition between weak and strong inversion arises in the MOSFET channel [19]. In correct extraction of Vth leads to significant errors in extracted effective mobility

as mentioned in [20], and therefore, accurate Vth extraction is necessary.

Many Vth extraction methods have been developed as introduced in [19].

Those extraction methods are mostly done with a low drain voltage so that the devices operate in the linear region. The extrapolation line in the linear region (ELR) method is the most popular Vth method. It is the common practice to find

the Vth as the gate voltage axis intercept (i.e., Id = 0) of the linear extrapolation

of the Id-Vgs characteristics at the maximum transconductance. One of the Vth

extraction methods developed to avoid the dependence on the series resistances is second-derivative (SD) method. It determines the Vth from the peak of

dgm/dVgs = d2Id/dVgs2 (the derivative of the transconductances).

3.2 Series Resistance Extraction

When the Vth of the MOSFET device is extraced, the next task is to extract

the series resistance Rsd. The Rsd extraction method used here is based on the

constant-mobility bias conditions as recently introduced in [10]. Regarding the mobility, it is convenient to express the effective mobility

µ

eff in terms of either

surface studies [20]. The typical relationship between the measured

µ

eff and Eeff

at the Si/SiO2 interface under different body-voltage (Vbs) conditions is

schematically shown in Fig. 9. The behavior of

µ

eff can be elucidated with the

Eeff expression given by [10]

(3.1)

E

=

_⎜⎜

Q

+

Q

_⎟⎟

⎠

⎞

⎝

⎛

inv dep si eff

1

1

η

ε

where εSi is the silicon permittivity, η is an empirical factor with the value @ 2

generally used for electron carriers at room temperature, Qinv is the

inversion-layer charge, and Qdep is the depletion-layer charge. The different Vbs

conditions resulting in Qdep variance can be interpreted with the following

formula (3.2)

_Q

=

₂

_N

_[

φ

_(V

₎

−

_V

_]

bs g S sub si dep

qε

where Nsub is the doping concentration of silicon substrate estimated by C-V

curves fitting along with Poisson-Schrödinger self-consistent simulations, and ψs is the substrate band bending. In low Eeff (low-Vg) regime, the quantity of the

Qdep is compared with the Qinv, leading to the obvious fluctuations of Eeff under

different Vbs conditions. On the contrary, the variances of the Qdep under

different Vbs conditions cannot be compared with the Qinv component in high Eeff

region because the Qinv is much larger than the Qdep in amount. Hence, the

µ

eff

under different Vbs conditions has the behaviour that disperses in low Eeff region

and converges toward one universal curve when Eeff is sufficiently high. The

(3.3)

where VFB is the flatband voltage, ψB is the potential difference between the

Fermi level and the intrinsic Fermi level, and V

B

th is the threshold extracted with

Id- Vgs data via gm-method. For a single device, both VFB and ψBB essentially

remain intact under different bias conditions. Thus, the formula (3.3) implies that a constant Eeff can be preserved from Vgs(1) and Vth(1) to other biases Vgs(2)

and Vth(2) under different Vbs conditions. In other words, we can keep the fixed

Eeff by adjusting the Vgs and Vth simultaneously which satisfy the following

expression [10]

(3.4)

Eventually, the constant-mobility bias conditions are established on the basis of the above-mentioned theory.

By integrating the constant-mobility criterion into the Id equation of

MOSFET devices operating in the linear region, the results for the two specific bias conditions (individually labeled with the superscript 1 and 2) are

(3.5)

(3.6)

The Rsd expression can be derived by dividing (3.5) by (3.6) under the

constant-mobility conditions, i.e.

µ

(1) =

µ

(2) under a high Eeff：

ox B

E

_eff gs th FB

t

3

2

V

1)V

(

V

η

η

η

η

−

−

φ

+

)(V

=

−

)

V

(1

V

V

=

+

−

η

−

(2) th (1) th (1) gs (2) gs

(

(1)

)

d sd ds ds (1) th (1) gs eff ox eff (1) (1) d

V

V

V

V

R

I

I

=

⎜

−

−

⎟

2

1

L

C

W

−

⎠

⎞

⎝

⎛

μ

(

(2)

)

d sd ds ds (2) th (2) gs eff ox eff (2) (2) d

V

V

V

V

R

I

I

=

⎜

−

−

⎟

2

1

L

C

W

₋

⎠

⎞

⎝

⎛

μ

(3.7)

)

V

)

I

I

(

R

_sd

−

−

=

η

(3.8) (3.9)

(V

V

A

B

(2) th (1) th ds (1) d (2) d th (1) gs

η

V

ds (1) th (1) gs

V

0.5V

V

A

=

−

−

ds (2) th (1)

_0.5V

1)V

(

V

B

=

+

−

−

η

−

After the treatment the effective channel length Leff, the effective channel

width Weff, and the inversion gate-oxide capacitance Cox are canceled out

because they are identical for a single device. This distinctive property makes this Rsd extraction method immune to the process variation for highly scaled

MOSFET devices where the explicit definitions of Leff, Weff, and Cox are difficult

to procure.

3.3 Effective Mobility Extraction

The effective mobility in MOSFET devices is a key parameter to describe the carrier transport and a also probe to study the electric properties of a two-dimensional carrier system. In order to extract the

µ

eff, one of the most

powerful methods is the combination of split capacitance-voltage (C-V) measurments, which are to deal with the used inversion and depletion charges, and linear Id-Vgs measurements [6]. Fig. 10 schematically shows the equivalent

circuit of a MOSFET device. If we take the Rsd into account in (2.1), the drain

and source voltages are rewritten [21]

(3.11)

I

R

sd

V

'

2

V

I

V

_gs

−

_d

R

_s

≅

_gs

−

1

_d

=

_gs

where Rs @ 0.5Rsd because the depletion due to Vds can be negligible when the

device is operated in the linear region (Vgs-Vth >> Vds). The series resistances

can be considered nearly the same between the drain and source. With the formulas (3.10) and (3.11), the Cox(Vgs-Vth-0.5Vds) factor in (2.1) is kept

constant [21]： (3.12)

V

_gs

'

_th

−

V

_ds

'

=

V

_gs

−

V

_th

−

V

_ds

2

1

2

1

V

−

The inversion charge Qinv under strong inversion condition, which is used in

evaluating

µ

eff and Eeff, can be approximately expressed [22]：

⎟

⎠

⎞

⎜

⎝

⎛

₋

₋

×

_{gs th ds} ox

V

2

1

V

V

C

(3.13)

≅

C

_ox

×

(

V

_gs

−

V

_th

)

≅

Q

_inv

(V

_gs

)

The approximation made in (3.13) is frequently employed to extract the mobility, but it leads to large errors in extracting mobility around the Vth. There are two

essential approahes to improve the accuracy of (3.13) in extracting

µ

eff [20]. One

is to measure the gate-to-channel capacitance Cgc and obtain the Qinv from the

voltage integral of the Cgc [4], [6], [23]. The second approach is to perform a

split C-V measurement to get C-V characteristics, then comparing the experimental and the simulated C-V characteristics (via Poisson-Schrödinger

self-consistent simulations) to obtain the Qinv.

Futhermore, it must be noted that the Vth through calculated Qinv may not

be exactly equal with that of Id(Vgs), especially for different devices. For this

reason, we can extract the

µ

eff more accurately by shifting Qinv characteristics

such as to compensate for the Vth discrepancy [4], [20]. Finally, the expression

of

µ

eff can be deduced from (2.1), (3.10), and the obtained Qinv：

(3.14)

_⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

⎟⎟

⎠

⎞

⎝

⎛

)

(V

Q

1

V

)

(V

I

W

L

g inv ds gs d eff eff

'

⎜⎜

=

μ

Chapter 4

Experimental Data and Interpretations

The halo-implanted bulk n-channel MOSFET devices with the gate width of 10µm, 1µm, 0.6µm, and 0.24µm under investigation were fabricated in a state-of-the-art manufacturing process. The major parameter extractions are focused on the nMOSFET devices with the channel length from 0.05µm to 0.1µm. Fig. 11 schematically shows the flowchart summarizing the procedures of

µ

eff extraction. In the flowchart diagram, the bold, solid line, and dashed dots

blocks indicate the expreimental data, extracted parameters, and simulated results during the measurements, respectively.

The objective for the C-V measurement is extracting the oxide thickness tox,

the dopant concentration of poly gate Npoly and substrate Nsub, and the effective

channel length Leff of the devices. The C-V characteristics of an nMOSFET

device are measured by means of the HP4284A LCR meter, followed by parameter extraction by comparing the measured and simulated C-V characteristics of an nMOSFET device. With the extraction results shown in Fig. 12, we get tox = 1.215 nm, Npoly = 4×1019 cm-3, and Nsub = 4×1017 cm-3.

I-V measurement includes Id-Vgs and Ig-Vgs characterizations for an

nMOSFET device. The Id-Vgs and Ig-Vgs experimental data are obtained by

HP4156B semiconductor parameter analyzer, which are adopted for the extractions of series resistance Rsd, threshold voltage Vth, oxide thickness tox,

effective channel length Leff, and the dopant concentration of the drain extension

NDE.

After performing the I-V measurement, the first task is to extract the Vth for

nMOSFET devices. The comparision between the Vth extracted by extrapolation

method is shown in Fig. 13, which indicates more obvious difference of Vth

values with shorter channel devices. Because the Rsd extraction via the Vth

values in ELR method shows more consistent results than that with the Vth

values extracted by SD method generally, the subsequently extraction procedures of Rsd and

µ

eff would use the Vth values extracted by ELR method.

Fig. 14 and 15 present the Leff extraction results for the W/L = 1μm/0.1 μm

nMOSFET device by both the channel-resistance method and the shift-and-ratio (S&R) method. The channel-resistance method fails because there is no explicit intersect point of the Rtot-L characteristics for different gate voltages, and the Leff

extraction results from the S&R method appear to be overestimated. Thus, we continue to try Leff extraction with the capacitive method. The experimental

Cgc(Vgs) curves for several nMOSFET devices with a largest width plotted in a

logarithm scale are plotted in Fig. 16. The Leff extracted by the constant ΔL

method and the individual ΔL method are displayed in Fig. 17 and 18, respectively. The corresponding Leff values for L = 1um are 61.57nm and

75.45nm. Furthermore, the EDT method is adopted for narrower and shorter devices under which the capacitive method can not work well. Fig. 19 demonstrates the example of EDT method for the W/L = 1μm/0.1 μm nMOSFET device, which leads to Leff = 72nm by comparing the measured

(triangular symbol) Ig-Vgs characteristics with the simulated (solid curve) under

accumulation conditions. Subsequently, the statistical analysis of the relations between ΔL and gate length and width is shown in Fig. 20 and 21, respectively. The figures reveal that the EDT method can preserve considerable accuracy for the narrower and shorter devices. Fig. 22 exhibits the Leff behavior with different

gate lengths. It must be noted that the difference between Leff and L becomes

larger with shorter channel length.

After finishing the Leff extraction, we proceed with the Rsd extraction by the

= 1μm/0.1 μm nMOSFET device is extracted by estimating the value with the universal curve at high Eeff. Fig. 24, 25, and 26 show that the Rsd values

apparently reduce with shorter devices, and have no visible dependence on the width and overlap length.

When the Leff and Rsd are extracted further, we can accurately carry out the

µ

eff extraction for highly scaled nMOSFET devices accordingly. Fig. 27 displays

the resulting

µ

eff curves of the W/L = 1μm/0.1μm nMOSFET device with raw

data also shown are corrected Leff , Rsd, and both Leff & Rsd corrected. The

variations of the peak mobility induced by overlap length for nMOSFET devices with different length and width are shown in Fig. 28 and 29, respectively. They illustrate that the mobility variations caused by overlap length are bigger with short devices but seem to be a weak function of the width. The variations of the mobility induced by Rsd at Vgs = 1.5V (higher Eeff) for nMOSFET devices with

different length and width are also illustrated in Fig. 30 and 31. As can be clearly seen, the variations of the mobility result from the Rsd seemingly

decrease with shorter length because the Rsd values reduce slightly with

decreasing gate length. In addition, the Rsd induced mobility variations are

connected with ΔL factor, rather than the width. At the end, the comparision between the raw and the corrected µeff values at Vgs = 1.5V are exhibited in Fig.

32 and 33 for different lengths and widths. The corrected µeff value for L = 0.1

µm nMOSFET device arises because the deviation caused by Rsd is worse than

that of ΔL. However, with device length scaling, the deviation caused by ΔL is larger than that by Rsd for highly scaled devices. From Fig. 32 and 33, the µeff

deviations tend to increase with reduced device length; nevertheless, it appears that the deviations are independent of the device width.

Chapter 5

Conclusion

The novel key parameter extractions for highly scaled MOSFET devices have been systematically executed. First, the Rsd extraction with

constant-mobility method neither considers the mobility dependence on channel length nor requires the precise values of mobility and channel length. Moreover, it provides immunity against process variation. Second, the problems of the Leff

extraction with capacitive method such as the gate leakage issue and the equipment detection limit, have been solved with the EDT method. Furthermore, for more accurate extraction of process parameters such as Nsub, Npoly, NDE, Qinv,

and tox, the EDT method and split C-V measurement can complement each other.

Because of the above-mentioned reasons, the

µ

eff eventually can be extracted

accurately. Moreover, the extraction methods also furnish the convenient and fast approaches that do not need to perform measurements in a large device sample size.

References

[1] S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFET's,”

IEEE Electron Device Letters, vol. 18, no. 5, pp. 209-211, May 1997.

[2] L. F. Register, E. Rosenbaum, and K. Yang, “Analytic model for direct tunneling current in polycrystalline silicon-gate metal–oxide–semiconductor devices,” Applied Physics

Letters, vol. 74, no. 3, pp. 457-459, January 1999.

[3] N.Yang,W.K. Henson, J.R.Hauser, and J.J.Wortman, “Modeling Study of Ultrathin Gate Oxides Direct Tunneling Current and Capacitance Measurements in MOS Devices,”

IEEE Transactions on Electron Devices, vol. 46, no. 7, pp. 1464-1471, July 1999.

[4] F. Lime, C. Guiducci, R. Clerc, G. Ghibaudo, C. Leroux, and T. Ernst, “Characterization of effective mobility by split C(V) technique in N-MOSFETs with ultra-thin gate oxides,” Solid State Electronics, vol. 41, pp. 1147-1153 (2003).

[5] Y. T. Hou, M. F. Li, Y. Jin, and W. H. Lai, “Direct tunneling hole currents through ultrathin gate oxides in metal-oxide-semiconductor devices,” Journal of Applied Physics, vol. 91, no. 11, pp. 258-264,January 2002.

[6] S. Severi, L. Pantisano, E. Augendre, E. S. Andrés, P. Eyben, and K. D. Meyer, “A Reliable Metric for Mobility Extraction of Short-Channel MOSFETs,” IEEE

Transactions on Electron Devices, vol. 54, no. 10, pp. 2690-2698, October 2007.

[7] X. Liu, J. Kang, and R. Han, “Direct tunneling current model for MOS devices with ultra-thin gate oxide including quantization effect and polysilicon depletion effect,” Solid

State Communications, vol. 125, pp. 219-223 (2003)

[8] J. Suiik, P. Olivo, and B. Riccb, “Quantum-Mechanical Modeling of Accumulation Layers in MOS Structure,” IEEE Transactions on Electron Devices, vol. 39, no. 7, pp.

[9] K. N. Yang, H. T. Huang, M. J. Chen, Y. M. Lin, M. C. Yu, S. M. Jang, Douglas C. H. Yu, and M. S. Liang, “Characterization and Modeling of Edge Direct tunneling (EDT) Leakage in Ultrathin Gate Oxide MOSFETs,” IEEE Transactions on Electron Devices, vol. 48, no. 6, pp. 1159-1164,June 2001.

[10] D. W. Lin, M. L. Cheng, S. W. Wang, C. C. Wu, and M. J. Chen, “A Constant-Mobility Method to Enable MOSFET Series-Resistance Extraction,” IEEE Electron Device

Letters, vol. 28, no. 12, pp. 1132-1134, December 2007.

[11] D. Fleury, A. Cros, K. Romanjekl, D. Roy, F. Perriert, B. Dumontt, and H. Brut, “Automatic extraction methodology for accurate measurement of effective channel length on 65nm MOSFET technology and below,” IEEE International Conference on

Microelectronic Test Structures, Tokyo, Japan, pp. 89-92, March 2007.

[12] J. G. J. Chern, P. Chang, R. F. Motta, and N. Godinho, “A New Method To Determine MOSFET Channel Length,” IEEE Electron Device Letters, vol. EDL-1, no. 9, pp. 170-173, September 1980.

[13] G. Niu, J. D. Cressler, S. J. Mathew, and S. Subbanna, “A Channel Resistance Derivative Method for Effective Channel Length Extraction in LDD MOSFET’s,” IEEE

Transactions on Electron Devices, vol. 47, no. 3, pp. 648-650,March 2000.

[14] Yuan Taur, “MOSFET Channel Length ： Extraction and Interpretation,” IEEE

Transactions on Electron Devices, vol. 47, no. 1, pp. 160-170, March 2000.

[15] M. Fathipour, E. Fathi, B. Afzal, and A. Khakifirooz, “An improved shift-and-ratio Leff

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[16] C. W. Eng, W. S. Lau, Y. Y. Jiang, D. Vigar, K. C. Tee, L. Chan, V. S. W. Lim, and A. Trigg, “Improving the Accuracy of Modified Shift-and-Ratio Channel Length Extraction Method Using Scanning Capacitance Microscopy,” Japanese Journal of Applied Physics,

vol. 43, no. 4B, pp. 1869-1872, 2004.

[17] Frank Stern, “Self-Consistent Results for n-Type Si Inversion Layers” Physical Review B, vol. 5, no. 12, pp. 4891-4899, June 1972.

[18] J. Maserjian and G. P. Petersson, “Tunneling through thin MOS structure：Depedence on energy (E-k),” Applied Physics Letters, vol. 25, no. 1, pp. 50-52, July 1974.

[19] A. O. Conde, F. J. G. Sanchez, J. J. Liou, A. Cerdeira, M. Estrada, and Y. Yue, "A review of recent MOSFET threshold voltage extraction methods," Microelectronics

Reliability 42 (2002) pp.583–596.

[20] J. R. Hauser, "Extraction of Experimental Mobility Data for MOS Llevices," IEEE

Transactions on Electron Devices, vol. 43, no. 11, pp. 1981-1988, November 1996.

[21] J.C. Guo, S. S. Chung, and C. C. Hsu, "A New Approach to Determine the Effective Channel Length and the Drain-and-Source Series Resistance of Miniaturized MOSFET's," IEEE Transactions on Electron Devices, vol. 41, no. 10, pp. 1811-1818,October 1994.

[22] K. Chen, H. C. Warm, J. Dunster, P. K. Ko, C. Hu, and M. Yoshida, "MOSFET Carrier Mobility Model Based on Gate Oxide Thickness, Threshold and Gate Voltages,"

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[23] K. Romanjek, F. Andrieu, T. Ernst, and G. Ghibaudo, "Improved Split C–V Method for Effective Mobility Extraction in sub - 0.1µm Si MOSFETs," IEEE Electron Device

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[24] K. N. Yang, H. T. Huang, M. J. Chen, Y. M. Lin, M. C. Yu, S. S. M. Jang, D. C. H. Yu, and M. S. Liang,"Edge Hole Direct Tunneling Leakage in Ultrathin," IEEE Transactions

W

L

_eff

L

_TN

L

_TN

L

_Gate

n

+

p-well

Oxide

V

_g

= -V

_DD

n

+

W

L

_eff

L

_TN

L

_TN

L

_Gate

n

+

p-well

Oxide

V

_g

= -V

_DD

n

+

W

L

_eff

L

_TN

L

_TN

L

_Gate

n

+

p-well

Oxide

V

_g

= -V

_DD

n

+

Fig. 1

R

_d

R

_s

R

ch

L

_Gate

L

_eff

scaling

R

_d

R

_s

R

ch

L

_Gate

L

_eff tot sd

R

R

R

_d

R

_s

R

ch

L

_Gate

L

_eff

scaling

R

_d

R

_s

R

ch

L

_Gate

L

_eff tot sd

R

R

Fig. 2

L

_eff

L

_Gate

n

+

p-well

Oxide

n

+

Source/Drain diffusion extensions

L

_eff

L

_Gate

n

+

p-well

Oxide

n

+

Source/Drain diffusion extensions

Gate Length L (µm)

Measured T

o

tal

Resistance

R

to t

(Ω

)

ΔL

R

_ext Vg=6 V Vg=8 V Vg=1 2V

Extracting L

_eff

with

Channel - Resistance Method

Gate Length L (µm)

Measured T

o

tal

Resistance

R

to t

(Ω

)

ΔL

R

_ext Vg=6 V Vg=8 V Vg=1 2V

Extracting L

_eff

with

Channel - Resistance Method

Energy reference point

SiO₂

n+_{-poly gate at accumulation condition}

Triangular Potential ~ ~ ~ ~ ~ ~ ~ ~ E_c @ E_fn E_v E1(The 1 st_subband)

E_F (The Fermi level)

E₂(The 2nd _subband) Si c

E

qF

dx

d

−

=

Energy reference point

SiO₂

n+_{-poly gate at accumulation condition}

~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ E_c @ E_fn E_v Triangular Potential Si c

E

qF

dx

d

−

=

E₁(The 1st_subband)

E_F (The Fermi level)

E₂(The 2nd _subband)

2DEG

~

~

~

~

n+_{-Poly Gate SiO}

2 Source/ Drain Diffusion Extension

qV

_GD

qV

_DE

qV

_ox

= qt

_ox

F

_ox

qV

_poly

E

_c

@ E

_fn

E

_v E_c E_v E₁ E_fn I_EDT Q 2DEG

~

~

~

~

~

~

~

~

n+_{-Poly Gate SiO}

2 Source/ Drain Diffusion Extension

qV

_GD

qV

_DE

qV

_ox

= qt

_ox

F

_ox

qV

_poly

E

_c

@ E

_fn

E

_v E_c E_v E₁ E_fn I_EDT Q

Fig. 6

~

~ ~~

Accumulated charge (Q) tunneling Model potential well

1 E E2 x E_o ox oxt qF c qχ ox

t

n+_{-Poly Gate SiO}

2 S/D Diffusion Extension F E ) F(anode E ⊕ -e

Energy reference point

ox Si ox Ec F ε ε q dx d − = Potential discontinuities (Boundary condition) ( )1 Si,⊥ E υ ( 1 ox) Si, E qV υ ⊥ + ( an) oxqφ ν ( cat) ox qφ ν Q ~ ~ ~ ~ ~~~~ Accumulated charge (Q) tunneling Model potential well

1 E E2 x E_o ox oxt qF c qχ ox

t

n+_{-Poly Gate SiO}

2 S/D Diffusion Extension F E ) F(anode E ⊕ -e

Energy reference point

ox Si ox Ec F ε ε q dx d − = Potential discontinuities (Boundary condition) ( )1 Si,⊥ E υ ( 1 ox) Si, E qV υ ⊥ + ( an) oxqφ ν ( cat) ox qφ ν Q

Fig. 7

F

_ox

, t

_ox

, N

_DE

Input

variable parameters

V

_ox

, Q, V

_DE

, F

_Si

E

₁

T

_WKB

, T

_R

, N

_DE

V

_poly

V

_g

Output

J

_EDT simulated results

F

_ox

, t

_ox

, N

_DE

Input

variable parameters

V

_ox

, Q, V

_DE

, F

_Si

E

₁

T

_WKB

, T

_R

, N

_DE

V

_poly

V

_g

Output

J

_EDT simulated results

Fig. 8

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0 25 50 75 100 125 150 175 at V_bs= 0V at V_bs= -0.5V at V_bs= -1V at V_bs= -1.5V

Raw Data

nMOSFET W/L=1μm/0.1μm, V_ds=0.025V

E

_eff

(MV/cm)

μ

eff

(c

m

2

/V

s)

Fig. 9

V

_ds

V

_gs

R

_D

R

_S

I

_d

V

_gs

’

V

_ds

’

V

_ds

V

_gs

R

_D

R

_S

I

_d

V

_gs

’

V

_ds

’

Fig. 10

I_g- V_gsData N_DE, t_ox, L_eff I_d- V_gsData C - V Data N_poly, N_sub, t_ox R_sd MOSFET Devices

C-V Measurement I-V Measurement

L_eff L_eff

EDT

Sim. & Fitting

Const. µ

Method V_th

g

_d Method

C

_gc Method

R

_ch

, S&R

Method

Shred

Sim. & Fitting

µ_eff, E_eff I_g- V_gsData N_DE, t_ox, L_eff I_d- V_gsData C - V Data N_poly, N_sub, t_ox R_sd MOSFET Devices C-V Measurement

C-V Measurement I-V MeasurementI-V Measurement

L_eff L_eff

EDT

Sim. & Fitting

Const. µ

Method V_th

g

_d Method

C

_gc Method

R

_ch

, S&R

Method

Shred

Sim. & Fitting

µ_eff, E_eff