Effects of PDA on the ZrO 2 /GeO 2 /Si MOS Capacitor

and by current fitting to comprehend the mechanism of Ge-related defects enhancing the leakage. The experiment flows of ZrO2/GeO2 capacitor with various treatments are exhibited in Fig. 3-1.

Second part, we want to see the effects of independent SCCO2 and H2O treatment on ZrO2 thin films, to confirm the validity after SCF treated on the ZrO2

films. A 0.5 ohm-cm p-type (100) Si wafer was cleaned with standard RCA clean process. 10nm ZrO2 deposited on Si immediately by E-gun evaporator, and then there are high pressure treating after dielectric depositing. Finally, 500nm aluminum electrodes were thermally evaporated on the top surface of ZrO2 film with an electrode area of 7.07×10^-4 cm² and the back side of silicon wafer to fabricate MOS capacitors. The IV and CV curve to see the MOS-capacitor properties. The experiment flows with various SCF-liked treatments are exhibited in Fig. 3-2. The results will show in section 3.4.

3.2 Effects of PDA on the ZrO

/GeO

/Si MOS Capacitor

3.2.1 Parameter Description

There are three parameters represent the characteristics of MOS capacitors.

¾ Effective Oxide Thickness (EOT)

(3-1)

Eq. (3-2) represents the effective oxide thickness (EOT) related to the dielectric constant of ZrO2. For the Eq. (3-2), the less EOT represents the value of k is higher.

Where εSiO2 is dielectric constant of SiO2, εZrO2 is dielectric constant of ZrO2, dthick is the Vfb near the zero bias, the less oxide charges existing inside the dielectric. Where φms is the work function difference between gate and substrate, Q0 is the number of oxide charges in the dielectric.

¾ Hysteresis (△Vfb)

Hysteresis represents the quality of interface between the dielectric and substrate, smaller △Vfb indicate better interface quality.

3.2.2 Characteristics of CV and IV Curves

Fig. 3-3 indicate the EOT verses various temperatures annealing. The dark square is pure ZrO2 stack on Si. The red square is ZrO2/GeO2 stacks on Si. As annealing temperature increasing, the EOT is shrinking; represent the higher k values of ZrO2 along with temperature increasing. At 500~600°C we can find the good annealing temperature. But at higher temperature annealing (> 600°C), the EOT uplift due to the low k interfacial layer have been formed.

Fig. 3-4 is shown the Vfb verse various temperature annealing. For pure ZrO2

stack, the Vfb reduced along with annealing temperature increased, the PDA treatment can effective remove the oxide charges in the high-k films. For ZrO2/GeO2 stacks, the

22 

Vfb generally reduced with temperature increased, expect the 400°C condition, the Vfb

shift to the negative is due to the Ge²⁺ typed defects creation [24]. Fig. 3-5 shows the impacts with band edge photo-absorption of GeO2 films of thermal treatments on GeO2 film properties evaluated by the spectroscopic ellipsometry. From the literature, it indicates the tailing states formation at the GeO2 band edge after annealing. Because of Ge decomposition or GeO desorption enhanced the oxygen-deficiency in GeO2

films to induce the defects like neutral oxygen vacancy or Ge²⁺, cause the Vfb shift to the negative bias [24,25].

Fig. 3-6 shows the delta Vfb verse the various annealing temperature. No matter the pure ZrO2 or ZrO2/GeO2 stacks, the hysteresis can effectively be reduced via PDA, showing the appropriate annealing can improve the interface quality.

Fig. 3-7 (a) and (b) show the leakage current density at the electric filed is 4×10⁶ (V/cm). We separate tow parts to discuss, the positive and negative bias. For the positive bias, the electron-hole pairs are generated by thermal excitation in deep depletion region to as leakage source. The current is limited by generation rate of minority carriers. Also, the traps near the interface contribute to the saturation current.

So the interface quality will affect the leakage current of positive bias, the current increases with the number of density of interface traps in the interface [26]. Fig. 3-7 (a) for pure ZrO2, the leakage of positive bias is reducing with annealing temperature increasing; show the density of interface traps can be improved by proper PDA. The results also correlated the characteristic of hysteresis. However, for ZrO2/GeO2 stacks, the different trend was observed relative to the pure ZrO2. Which along with temperature increasing the current density also increasing are due to Ge decomposition causing interface deterioration. The Ge decomposition makes interface consumption and creates interface traps to provide a path for minority carrier generation.

Fig. 3-7 (b) shows the leakage at negative bias. The leakage can be reduced through the modified temperature annealing. Above 600°C, the leakage is increased due to the complete poly-crystallization; the grain boundary supply a path of the leakage, on the other hand, the carrier will follow grain boundaries to form the leakage paths. The characteristics of XRD were show the crystal pattern in Fig. 3-8 (a) and (b). From the XRD, we can see as deposited the ZrO2 film is amorphous, along with annealing temperature increased; the peak of XRD is more significant, which shows the more complete crystallizing after 600°C annealing. But for the ZrO2/GeO2

stacks, after 600°C annealing, the leakage current increase dramatically, it would not only due to ZrO2 crystallization but also the Ge decomposition makes the GeO diffusion into the dielectric to enhanced the leakage uplift.