Electron Spectroscopy for Chemical analysis

There is no doubt that the spin-on dielectrics only contains cobalt, titanium and oxygen elements, which is confirmed by EDS analysis in section 3.1 and Auger depth profile in section 3.1. However, we still don’t know the chemical properties and atomic concentration ratio of this dielectric prepared by sol-gel spin coating. In the section we use electron spectroscopy for chemical analysis (ESCA) to obtain further information.

Figure 3.7 shows ESCA results of the dielectric formed by sol-gel spin coating method and the dielectric under analysis is 1-coated and annealed at 600^oC. From figure 3.7(a) to 3.7(d) are the spectrums of silicon 2p orbital, oxygen 1s orbital, cobalt 2p orbital and titanium 2p orbital, respectively. As shown in figure 3.7(a), two main peaks identify single crystalline silicon (99.3 eV) and silicon dioxide (103.3 eV) in the silicon 2p orbital spectrum. We also observe that the shift and the growth of the silicon-dioxide-peak increases, as the annealing temperature is increased, which means that more complete structure and thicker silicon oxide are formed after higher temperature annealing. The spectrum of oxygen 1s orbital shown in figure 3.7(b) reveals that there may be two kinds of metal-oxygen bonds with lower binding energy near 531 eV , e.g. Co-O and Ti-O for all samples. However, the broader binding energy distribution for the sample annealed at 200^oC may be resulting from hydroxides in the dielectric [27]. Furthermore, the samples with 800^oC and 900^oC

annealing have silicon oxide bond with binding energy near 533 eV, which is consistent with the results in figure 3.7(a). We also notice that two shake-up peaks with higher binding energy than two main peaks (2p3/2 and 2p1/2) appear in the Co spectrum, as shown in figure 3.7(c).

In order to confirm the atomic concentration ratio of the dielectric prepared by sol-gel spin coating method, more detailed ESCA analysis for the spin-on dielectric annealed at 600 ^oC is executed. After background removal by Shirley method and curve fitting for oxygen-metal bonds (oblique line area) in oxygen spectra, we integrate the intensity from 775 to 810 eV for cobalt spectra, from 453 to 468 eV for titanium spectra and from 527 to 535 eV for oxygen spectra, as shown in figure 3.8.

The relative sensitivity factors for cobalt, titanium and oxygen are 3.529, 2.077 and 0.733, respectively. And the atomic concentration ratio is obtained as,

93175.67 53580.63 53828.65

Therefore, the atomic concentration ratio is almost close to 1:1:3.

5nm

Fig. 3.1 TEM image of Al-electrode/1-coated CoTiO3

thin film/bare Si structure.

Fig. 3.2 Electron dispersive spectra (EDS), associated with the TEM image showed in Fig. 3.1, of the CoTiO3dielectric annealed at 400^oC.

1.88 nm 5.27 nm 2.23 nm

(a)

(b) Al

CoTiO

₃

Si-sub

Fig. 3.3 XRD spectra of spin-on CoTiO3 films. The marked peaks correspond to crystallized CoTiO3 phases.

(012) (104) (110) (113) (024) (116)

(a)

(b)

(c)

(d)

(e)

(f)

Fig. 3.4 SPM images of spin-on CoTiO3 films with various thermal treatments at (a) 200^oC, (b) 400^oC, (c) 600^oC, (d) 700^oC, (e) 800^oC and (f) 900^oC. The image size is 1 μm by 1 μm.

200 400 600 800 1000

Fig. 3.5 Surface roughness of spin-on dielectrics as functions of annealing temperature.

Fig. 3.6 Auger depth profile of the CoTiO3 dielectric annealed at 600^oC.

543 540 537 534 531 528 525 (b)

810 800 790 780 770

(c)

470 465 460 455 450

(d)

810 800 790 780

468 465 462 459 456 453

0 1s(c) for the spin-on dielectric annealed at 600^oC.

Chapter 4

Physical Property

In this chapter, we will report the physical properties of spin-on CoTiO3 thin films, such as dielectric permittivity, C-V and I-V characteristics, current transport mechanism, band energy gap and band alignment.

4.1 Dielectric Permittivity

According to section 3.1.1, it is easy to form an interfacial layer between Si-sub and a CoTiO3 film. However, it is imprecise and difficult to extract the κ value of CoTiO3 film from measuring capacitance. In order to estimate the dielectric constant of CoTiO3 thin films, a thermal oxidation is used to grow a high quality SiO2 thin layer before the CoTiO3 spin-coating. The C-V characteristics of both TaN/CoTiO3/SiO2/Si and TaN/SiO2/Si capacitors are demonstrated in Fig. 4.1. The well C-V characteristics can be observed for both two capacitors without flat-band voltage shift, as shown in Fig. 4.1. The capacitance effective thickness (CET) is extracted from C-V curves at 100 kHz without considering quantum effect. The CET of CoTiO3/SiO2 and SiO2 are 4.66nm and 4.27nm, respectively. However figure 4.2 shows HR-TEM image of the Si/SiO2/CoTiO3/TaN structure. Thicknesses of 1-coated high-k dielectric and thermal oxide are 4.02 and 4.27 nm, respectively, as shown in this TEM image. As a result, the exact dielectric constant of CoTiO3 thin film is found to be 40.2, which is matched the value of CoTiO3 films fabricated by direct oxidation of sputtered Co/Ti layers [28][29], indicating that the high permittivity CoTiO3 films can also been deposited by simple sol-gel spin coating method.

4.2 C-V and I-V Characteristics

Figure 4.3 shows the C-V characteristics of CoTiO3 gate dielectric with different

thermal treatments. The sample with 600^oC RTA shows a steeper C-V slope in the depletion region, suggesting a better CoTiO3/Si interface. RTA temperatures beyond 600^oC result into flatter C-V curves which may be due to the sub-stoichiometric interfacial-oxide growth and thermal stress.

Figure 4.4 shows the I-V characteristics of CoTiO3 gate dielectrics. The leakage current density increases with increasing RTA temperature (600~900^oC), even though the C-V curves suggest a larger effective oxide thickness (EOT) for samples annealed at higher temperatures. This can be explained by the cracks and crystallization of CoTiO3 thin films, as discussed before. Finally we sum up the fundamental electrical behavior of spin-on CoTiO3 dielectric in figure 4.5, and the dielectric annealed at 600^oC has the smallest EOT.

4.3 Current Transport Mechanism

Figure 4.6 shows the I-V curves measured at elevated temperatures. The CoTiO3

film under test was annealed at 600^oC. The I-V curves were fitted by the Schottky emission model (inset), and the barrier heights of 0.74, 0.72, 0.70, and 0.69eV were extracted at room temperature, 40^oC, 50^oC, and 60^oC, respectively. Fittings with the Frenkel-Poole (FP) conduction model were also carried out. Figure 4.7 demonstrates that the current conduction is not dominated by the FP conduction but by the Schottky emission, which shows a smaller Si/CoTiO3 barrier height.

4.4 Band Energy gap and Band Alignment

As mentioned in Section 1.5, XPS technique can be utilized to determine the band gap energy. In this section we characterize the band gaps of SiO2 and the spin-on CoTiO3 dielectric annealed at 600^oC. In order to align the band diagram, we also use high resolution XPS analyzer to detect the maximum valence energy band level of

thermally grown SiO2 and the spin-on CoTiO3 dielectric [30].

As mentioned in Section 1.5, the background rise below XPS core level peaks is due to inelastic scattering effects of the photon-electrons. More importantly, the excitation of the electrons from valence band to conduction band can also be detected at the onset of plasma energy loss. As a result, the onset of the background increase relative to the peak position corresponds with the band gap of the material. Figure 4.8 shows the spectrum of oxygen 1s orbital for SiO2, which is illustrating that the energy band gap of thermal SiO2 is about 9.0 eV. This value is almost close to the common results [6][7]. Furthermore, the high resolution core level and band gap spectra of spin-on CoTiO3 film is shown in Fig. 4.9. The energy band gap of spin-on CoTiO3 is about 2.2 eV, which is close to the value of CoTiO3 powders fabricated by a modified Pechini method [31].

On the other hand, the measurements are performed on thermal SiO2 (~15nm) and the 5-coated dielectric CoTiO3 (~20nm)/SiO2 (~15nm) stacks. The valance band spectrum for these layers contains the information about the density of states of both the CoTiO3 and SiO2 films. The maximum valence energy band and the valence band offset (ΔEv) between CoTiO3 and SiO2 films can thus be determined as about 4.0 eV, as indicated in Fig. 4.10.

As mention in figure 4.7, the energy barrier height between silicon substrate and spin-on CoTiO3 dielectric is about 0.74 eV at room temperature. Because the energy band alignment between Si and SiO2 is a well-known result, we can deduce the band alignment between Si, SiO2 and spin-on CoTiO3 dielectric, as shown in figure 4.11.

Figure 4.11 shows the energy band alignment between Si, SiO2 and high-k dielectric CoTiO3, which serves to summarize the key results we have obtained from the analysis of HR-XPS and Schottky emission characteristics. And this deduction is consistent with the result in figure 4.9.

Fig. 4.1 TEM micrograph of an ultrathin CoTiO3 film spin-coated on a high quality thermal SiO2 layer and annealed at 600^oC.

Fig. 4.2 C-V curves of capacitors with TaN/CoTiO3/SiO2/Si and TaN/SiO2/Si stack structures.

Fig. 4.4 I-V curves of spin-on CoTiO3 films with different thermal treatments.

Fig. 4.3 C-V curves of spin-on CoTiO3 films with different thermal treatments.

200 400 600 800 1000 10

100 EOT

J^g@Vg=2V

Temperature ^(oC⁾

E.O.T.(nm)

1E-6 1E-5 1E-4 1E-3 0.01 0.1

J (A/cm 2

)

Fig. 4.5 Effective oxide thickness and current density of spin-on dielectrics as functions of annealing temperature.

Fig. 4.7 Effective barrier heights extracted from I-V curves by using Schottky-emission and Frenkel-Poole models.

Fig. 4.6 I-V curves measured at RT and elevated temperatures.

(Inset) Extracted Schottky-emission barrier heights.

550 545 540 535 530 525

SiO2

9.0 eV O 1s

Intensity (a.u.)

Binding Energy (eV)

550 545 540 535 530 525

9 12 15 18 21 24 27

Counts (x104 /s)

Binding Energy (eV)

2.2 eV CoTiO₃

O 1s

Fig. 4.8 ESCA spectra of O 1s for thermally grown 15 nm-SiO2.

Fig. 4.9 ESCA spectra of O 1s for the spin-on 15 nm-CoTiO3

dielectric annealed at 600^oC.

14 12 10 8 6 4 2 0 -2 -4 SiO₂ CoTiO₃

CoTiO₃ SiO₂

ΔVB_max=4.0 eV

Intensity (a.u.)

Binding Energy (eV)

SiO2 Si-sub CoTiO3

4. 0 eV 4. 4 eV

Eg=2.2 eV Eg=1.1 eV

E^c=0.7 eV

Fig. 4.11 Band alignment between Si, SiO2 and spin-on CoTiO3 dielectric with 600^oC annealing.

Fig. 4.10 Maximum valence energy band spectra of thermally grown 15 nm-SiO2 and spin-on 20 nm CoTiO3 dielectric annealed at 600^oC measured by high resolution ESCA.

Chapter 5 Conclusions

In this chapter we will summarize the important results of spin-on CoTiO3 as mentioned in previous chapters and make conclusions for this these.

5.1 Conclusions

In this thesis we form the dielectric CoTiO3 by sol-gel spin coating method followed by different annealing temperature 600~900^oC. The image of transmission electron microscopy (TEM), as shown in Fig. 3.1, reveals that 2.2 nm interfacial layer is between Si-sub and CoTiO3 with 400^oC annealing. According to X-ray diffraction (XRD) pattern in Fig. 3.3, crystallization temperature of the spin-on dielectric is between 600 and 700^oC. As shown in Fig. 3.4 and Fig. 3.5, scanning probe microscope (SPM) describes surface morphology of the spin-on dielectrics with different annealing temperature and the surface roughness abruptly increases as annealing temperature higher than 600 ^oC. Electron spectroscopy for chemical analysis (ESCA) in Fig. 3.7 shows that higher temperature annealing results in thicker interfacial layer and pure chemical bonding. Furthermore ESCA in Fig. 3.8 also confirms that the spin-on dielectric with 600^oC annealing has atomic concentration ratio [Co]:[Ti]:[O]~1:1:3. The spin-on film CoTiO3 with 600^oC annealing has Schottky emission conduction mechanism for the TaN/ CoTiO3/ Si-sub structure and the evidences are presented in Fig. 4.6 and Fig.4.7. And the trapping characteristics of spin-on film CoTiO3 with 600^oC annealing is affected by temperature, applied stress voltage and stress time.

High electrical permittivity (k~40.2) of CoTiO3 dielectric is extracted via the high resolution transmission electron microscopy (HR-TEM) image and C-V curves, as shown in Fig 4.1 and Fig. 4.2. In addition, the band energy gaps of thermally

grown SiO2 and spin-on CoTiO3 are 9.0 and 2.2 eV, respectively, as shown in Fig. 4.8 and Fig. 4.9. The valence energy band offset between thermally grown SiO2 and spin-on CoTiO3 is about 4.0eV, which is detected by high resolution X-ray photoelectron spectroscopy (HR-XPS) in Fig. 4.10. The energy band alignment of spin-on CoTiO3 directly with SiO2 and indirectly with Si is successfully determined in this thesis, as shown in Fig. 4.11.

Reference

[1] B. G. Streetman and S. Banergee, Solid State Electronic Device, 5th ed.:

Prentice Hall Inc., 2000.

[2] S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, "Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFET's," Electron Device Letters, IEEE, vol. 18, pp.

209-211, 1997.

[3] S. O. Kasap, Principles of Electrical Engineering Materials and Devices:

McGraw-Hill, 2002.

[4] K. Eisenbeiser, J. M. Finder, Z. Yu, J. Ramdani, J. A. Curless, J. A. Hallmark, R. Droopad, W. J. Ooms, L. Salem, S. Bradshaw, and C. D. Overgaard, "Field effect transistors with SrTiO3 gate dielectric on Si," Applied Physics Letters, vol. 76, pp. 1324-1326, 2000.

[5] G. Lucovsky and B. Rayner, "Microscopic Model for Enhanced Dielectric Constants in Low Concentration SiO2-Rich Noncrystalline Zr and Hf Silicate Alloys," Appl. Phys. Lett., vol. 77, pp. 2912, 2000.

[6] S. M. Sze, Physics of Semiconductor Devices, 1985.

[7] G. D. Wilk, R. M. Wallace, and J. M. Anthony, "High-k Gate Dielectrics:

Current Status and Materials Properties Considerations," J. Appl. Phys., vol.

89, pp. 5243, 2001.

[11] R. Chandrasekharan, Inkyu Park, R. I. Masel, and M. A. Shannon, "Thermal Oxidation of Tantalum Films at Various Oxidation States from 300 to 700 ﾟ C," J. Appl. Phys., vol. 98, pp. 114908, 2005.

[12] I. C. Kizilyalli, R. Y. S. Huang, P. K. Roy, "MOS Transistors with Stacked SiO2 –Ta2O5 –SiO2 Gate Dielectrics for Giga-Scale Integration of CMOS Technologies," Electron Device Letters, IEEE, vol. 19, pp. 423-425, 1998.

[13] D. G. Park, H. J. Cho, et al. (2000). Tech. Dig. VLSI Symp.

[14] J. H. Lee, K. Koh, et al. (2000). Tech. Dig. Int. Electron Devices Meet.

[15] The International Technology Roadmap for Semiconductors, Semiconductor Industry Association.

[16] J. C. Wang, D. C. Shie, et al. (2004). Appl. Phys. Lett. 84: 1531.

[17] Kuo-Hsing Kao, Jian-Hao Chen, et al. (2007). Characterization of CoTiO3 Thin Films Formed by Sol-Gel Spin Coating with High Temperature Annealing. SNDT, Taiwan.

[18] Hsin-Chiang You, Tze-Hsiang Hsu, et al. (2006). "Hafnium Silicate Nanocrystal Memory Using Sol–Gel-Spin-Coating Method." Electron Device Letters, IEEE 27: 644.

[19] Ko, F.-H., Hsin-Chiang You, et al. (2007). "Fabrication of SONOS-Type Flash Memory with the Binary High-k Dielectrics by the Sol-Gel Spin Coating Method." Jouranl fo The Electrochemial Society 154.

[20] J. Tang, J. Fbbri, et al. (2004). Chem. Mater 16: 1336.

[21] L.C. Feldman and J.W. Mayer, Fundamentals of Surface and Thin Film Analysis, Elsevier Science Publishing Co., Inc., 1986.

[22] D.A. Shirley, Photoemission in Solids І, Vol. 26 of Topics in Applied Physics, edited by M. Cardona and L.Ley (Springer-Verlag, Berlin, 1978), p.165.

[23] S. Miyazaki, H. Nishimura, M.Fukuda, L. Ley, and J. Ristein, Appl. Sur. Sci.

113/114, 585-589 (1997).

[24] J.L. Alay and M. Hirose, J. Appl. Phys., 81, 1606, (1997).

[25] H. Itokawa, T. Maruyama, S. Miyazaki, and M. Hirose, Extended abstracts of the 1999 Int. Conf. Solid State Devices and Materials, Tokyo, 1999, p. 158.

[26] Hyeong Joon Kim, Qingyi Shao, Yoon-Hae Kim. Surface and Coatings Technology, 171 (2003), 39–45.

[27] John F. Moulder, William F. Stickle, Peter E. Sobol, Kenneth D. Bomben, Handbook of X-ray Photoelectron Spectroscopy, Perkin-Elmer Corporation, 1992

[28] T. M. Pan, et al Appl. Phys. Lett. 78, (2001) 1439 [29] J. H. Chen, et al J. Electrochem. Soc., 154, (2007) [30] F.G. Bell and L. Ley, Phys. Rev. B, 37, p.8383, (1988).

[31] Yi-Jing Lin, Yen-Hwei-Chang, et al. (2005). "Synthesis and Characterization of Ilmenite NiTiO3 and CoTiO3 Prepared by a Modified Pechini Method."

Jouranl of Non-Crystalline Solid, 352 789-794.

[32] K. Kukli, et al J. Appl. Phys. 92, 5698 (2002).

[33] C. M. perkins, et al Appl. Phys. Lett. 78, 2357 (2001).

Publication List

A. International Journal Paper：

[A-1] Ming-Wen Ma, Tien-Sheng Chao, Kuo-Hsing Kao, Jyun-Siang Huang, and Tan-Fu Lei, “Fringing electric field effect on 65-nm-node fully depleted silicon-on-insulator devices,” Japanese Journal of Applied Physics, vol. 45, no.

9A, pp.6854-6859, 2006.

[A-2] Ming-Wen Ma, Chin-Yang Chen, Chun-Jung Su, Woei-Cherng Wu, Kuo-Hsing Kao, Tien-Sheng Chao, and Tan-Fu Lei, “Reliability mechanisms of LTPS-TFT with HfO2 gate dielectric: PBTI, NBTI and hot carrier stress,”

IEEE Trans. Electron Devices, have been accepted for publication.

[A-3] Ming-Wen Ma, Chin-Yang Chen, Chun-Jung Su, Woei-Cherng Wu, Tsung-Yu Yang, Kuo-Hsing Kao, Tien-Sheng Chao, and Tan-Fu Lei, “Improvement on performance and reliability of TaN/HfO2 LTPS-TFTs with fluorine implantation,” Solid State Electronics, vol. 52, no. 3, pp.342-247, 2008.

B. International Letter Paper：

[B-1] Kuo-Hsing Kao, Shiow-Huey Chuang, Jian-Hao Chen, Ming-Wen Ma, and Tien-Sheng Chao, “High resolution XPS energy band alignment of CoTiO3

high-k dielectric prepared by sol-gel spin coating method,” Appiled Physics Lett., in revision.

[B-2] Ming-Wen Ma, Yi-Hong Wu, Kuo-Hsing Kao, Woei-Cherng Wu, Tien-Sheng Chao, and Tan-Fu Lei, “Impacts of N2 and NH3 plasma surface-treatment on high performance LTPS-TFT with high-κ gate dielectric,” IEEE Electron Device Lett., in version.

[B-3] Ming-Wen Ma, Tien-Sheng Chao, Kuo-Hsing Kao, Jyun-Siang Huang, and Tan-Fu Lei, “High-κ material sidewall with source/drain-to-gate non-overlapped structure for low standby power applications,” Japanese Journal of Applied Physics, vol. 45, no. 11, pp.8656-8658, 2006.

[B-4] Ming-Wen Ma, Chien-Hung Wu, Tsung-Yu Yang, Kuo-Hsing Kao, Woei-Cherng Wu, Tien-Sheng Chao, and Tan-Fu Lei, “Impact of high-κ offset spacer in 65-nm node SOI devicesn,” IEEE Electron Device Lett., vol. 28, no.

3, pp.238-241, March, 2007.

[B-5] Ming-Wen Ma, Tien-Sheng Chao, Chun-Jung Su, Woei-Cherng Wu, Kuo-Hsing Kao, and Tan-Fu Lei, “High performance metal-induced lateral crystallized polycrystalline silicon p-channel thin film transistor with TaN/HfO2 gate stack structure,” IEEE Electron Device Lett., have been accepted for publication.

[B-6] Ming-Wen Ma, Chin-Yang Chen, Chun-Jung Su, Woei-Cherng Wu, Yi-Hong Wu, Kuo-Hsing Kao, Tien-Sheng Chao, and Tan-Fu Lei, “Characteristics of PBTI and hot carrier stress for LTPS-TFT with high-κ gate dielectric,” IEEE Electron Device Lett., vol. 29, no. 2, pp.171-173, Feb., 2008.

[B-7] Ming-Wen Ma, Chin-Yang Chen, Chun-Jung Su, Woei-Cherng Wu, Yi-Hong Wu, Tsung-Yu Yang, Kuo-Hsing Kao, Tien-Sheng Chao, and Tan-Fu Lei,

“Impacts of fluorine ion implantation with low temperature solid-phase crystallized activation on high-κ LTPS-TFT,” IEEE Electron Device Lett., vol.

29, no. 2, pp.168-170, Feb., 2008.

C. International Conference Paper：

[C-1] Ming-Wen Ma, Kuo Hsing Kao, Tien-Sheng Chao and Tan-Fu lei, “Ultra-low temperature of aluminum silicate dielectric formed by nitric acid” 2006 International Workshop on Dielectric Thin Films for Future ULSI Devices Technical Program, November, Kawasaki, Japan, pp. 81-82, Nov. 2006.

[C-2] Ming-Wen Ma, Tsung-Yu Yang, Kuo-Hsing Kao, Chun-Jung Su, Tien-Sheng Chao, and Tan-Fu Lei, “Mobility improvement of HfO2 LTPS-TFTs with nitrogen implantation,” Asia Display 2007 International Conference, Shanghai, China, pp. 674-677, March, 2007.

[C-3] Ming-Wen Ma, Tsung-Yu Yang, Kuo-Hsing Kao, Tien-Sheng Chao, and Tan-Fu Lei, “Improvement on performance and reliability of TaN/HfO2

LTPS-TFTs with fluorine implantation,” 2007 International Thin Film Transistors Conference, January, Rome, Italy, pp.352-355, Jan. 2007.

[C-4] Ming-Wen Ma, Tsung-Yu Yang, Kuo-Hsing Kao, Chun-Jung Su, Tien-ShengChao, and Tan-Fu Lei, “High performance LTPS TFTs with HfO2 gate dielectric and nitric acid pre-treatment,” 2006 International Workshop on Dielectric Thin Films for Future ULSI Devices Technical Program, November, Kawasaki, Japan, pp. 33-34, Nov. 2006.

[C-5] Ming-Wen Ma, Tien-Sheng Chao, Kuo-Hsing Kao, Jyun-Siang Huang and Tan-Fu Lei,” Impacts of high-κ offset spacer on 65-nm node SOI devices”,Ninth International Conference on Modeling and Simulation of Microsystems, Boston, Massachusetts, pp.697-700, May 2006.

[C-6] Ming-Wen Ma, Tien-Sheng Chao, Kuo-Hsing Kao, Jyun-Siang Huang and Tan-Fu Lei,” Novel FD SOI devices structure for low standby power applications“, Ninth International Conference on Modeling and Simulation of Microsystems, Boston, Massachusetts, pp.59-62, May 2006.

[C-7] Tsung-Yu Yang, Ming-Wen Ma, Kuo-Hsing Kao, Chun-Jung Su, Tien-Sheng Chao, and Tan-Fu Lei, “Impacts of nitric acid oxidation on low-temperature polycrystalline silicon TFTs with high-κ gate dielectric,” Asia Display 2007 International Conference, Shanghai, China, pp. 519-522, March 2007.

D. Local Conference Paper：

[D-1] Kuo-Hsing Kao, Jian-Hao Chen, Ming-Wen Ma, Tien-Sheng Chao, Reui-Hung Gau, Michael Y. Chiang, Shiow-Huey Chuang, Tan-Fu Leiand Guang-Li Luo “Characterization of CoTiO3 Thin Films Formed by Sol-Gel Spin Coating with High Temperature Annealing”, SNDT 2007 Symposium on Nano Device Technology, Hsin Chu, R.O.C.

[D-2] Ming-Wen Ma, Tien-Sheng Chao, Kuo Hsing Kao, Jyun-Siang Huang, and Tan-Fu lei, “Novel FD SOI devices structure for ultra low leakage applications,” SNDT 2006 Symposium on Nano on Nan Device Technology, Hsin Chu, R.O.C., pp. T05-07, April, 2006.

簡 歷 (Vita) 姓名: 高國興

性別: 男

出生日: 1982 年 11 月 10 日 籍貫: 山東省 青島市

出身地: 台灣 台北市

學歷: 國立中興大學物理學系 學士班 2001 年 9 月-2005 年 6 月

國立交通大學電子物理研究所 碩士班 2005 年 9 月-2008 年 6 月

碩士論文題目:

利用溶膠旋轉塗佈法備製鈦酸鈷高介電層

利用溶膠旋轉塗佈法備製鈦酸鈷高介電層

在文檔中 利用溶膠旋轉塗佈法備製鈦酸鈷高介電層 (頁 33-0)