The speedy progress of complementary metal-oxide-semiconductor（CMOS）
integrated circuit technology has made our chips more powerful, even cheaper and met several requirements. The requirements include higher speed, lower consumption, and so on. And these have been accomplished by scaling down the transistor feature size, such as channel length and gate silicon-oxide （SiO2） thickness. According to Moore’s law, an exponential growth in the number of transistors per chip was predicted and had been proven true as shown in figure 1.1 [1].
One reason that Si-based devices have played the main roles in microelectronic fabrication is that Si has a high quality and easily-formed SiO2. And it exhibits low trap density, large band gap, low interface state density, high carrier mobility and good thermal stability with Si. Unfortunately, significant gate leakage current increases and boron penetration occurs when SiO2 is scaled less than 30Å as shown in figure 1.2 [2]. However, a temporary solution, silicon nitride or oxynitride（SiOxNy）, relaxes the problems. SiOxNy owns slightly higher dielectrics constant（κ~7.5）and which reduces the gate leakage current due to thicker physical film. The particular Si-O-N network bonding in SiOxNy greatly suppresses boron penetration through the dielectrics. But, a further problem is that the dielectrics constant value of SiOxNy is
not high enough. And it is necessary to find a candidate material which has higher dielectric constant for replacing conditional gate dielectrics.
1.2 Metal Oxide Material for High- κ Gate Dielectrics
As the description in the classical electrostatics, the internal polarization P of a substance is induced when an external electric field E is applied on it. And which can be formulated simply as below equation,
(1-1)
where D is the electric displacement and εo is the permittivity of free space. However, we can rewrite Eq. (1-1) and replace the internal polarization P by a coefficient κ called dielectric constant,
(1-2)
Comparing Eq. (1-1) with Eq. (1-2), therefore, we know that dielectric constant κ is used to tell the degree of the polarization of certain material while the external electrical field is applied.
Figure 1.3 illustrates the relation between the real (εr’) and imaginary (εr”) parts of the dielectric permittivity and the frequency, and also marks the current frequency range for CMOS operation (100MHz~10GHz) [3]. There are two main contributions to the dielectric constant which give rise to the polarization: electronic and ionic dipoles. In general, atoms with higher atomic number demonstrate more electron dipole response to an external electrical field, because there are more electrons to respond to the field. And this electronic contribution tends to increase the permittivity
D=εoE+P,
D=εoκE.
at ultrahigh frequency (~1016 Hz) as a result of the light electrons.
The ionic contribution to the permittivity could be much larger than the electronic portion such as (Ba, Sr)TiO3 which exhibits ferroelectric behavior (perovskite crystal structure) below Curie Temperature. As shown in figure 1.4, Ti ions in the unit cells are displaced in response to an applied electric field. This displacement of Ti ions results in a huge polarization in the material, and thus can give rise to large dielectric constants (SrTiO3 ~175 [4]). Since ions respond more slowly than electrons to an applied field, the ionic contribution begins to decrease at very high frequency (~1012 Hz), as shown in Figure 1.3.
Furthermore, we can modify the polarization behavior of an insulator by low level incorporation. This low level incorporation actually changes the localized bonding order and the vibration mode of the network ions in that insulator. G..
Lucovsky and B. Rayner demonstrated this phenomenon by low level doping Zr (or Hf) atoms in the SiO2 film; and the dielectric constant of the insulator increased due to the discernable change in bonding order and in vibration modes [5].
In summary, we can briefly tell the main contributions to the polarization of insulators for gate dielectrics: electronic, ionic and low level incorporation. However, the above contributions will be distinguished when the atoms own more electrons and higher atomic number. And that’s why metal oxide exhibits higher permittivity than the SiO2.
1.3 Requirements for High- κ Gate Dielectrics
In order to successfully replace gate SiO2, the alternative high-κ material should possesses some required properties for next generation devices. In this section, we are going to talk about this issue.
1.3.1 Permittivity and Barrier Height
As previous discussion, an insulator with higher permittivity reduces the gate leakage current due to thicker physical thickness. However, leakage mechanism actually is dominated by intrinsic properties and is affected by extrinsic properties.
The intrinsic properties of the insulator include band gap (Eg), the dielectric constant (κ) and the conduction band offset (ΔEC). The extrinsic properties of the insulator include physical thickness, film morphology, the method of deposition, temperature and applied electrical field to the insulator. And several basic conduction processes in insulators are listed in table 1.1 [6].
Therefore, as described in table 1.1, the direct tunneling current will be obviously suppressed by increasing the physical thickness and the conduction band offset.
1.3.2 Thermodynamic Stability on Silicon
So far, most of the studied high-κ metal oxide systems have unstable interfaces with Si; they react with Si to form an undesirable interfacial layer. However, that will reduce the effective oxide thickness (E.O.T.) and degrade the carrier mobility under the interfacial layer [7]. So it is important to understand the thermodynamics of these systems and thereby attempt to control the interface with Si.
Because Si devices will undergo several high temperature processes after high-κ deposition on Si-sub, possible interfacial reaction are given as follows:
(1-3)
Although the interfacial metal-silicon products are usually detrimental to the gate oxide performance, the metal silicate which is shown in Eq. (1-5) is even helpful in some aspects. Taking HfO2 and HfSiO4 for example, the interface and crystallization temperature of HfSiO4 are sharper and higher than those of HfO2, respectively [7][8].
And we will discuss high-κ material crystallization temperature more detail later.
In addition to the issue of thermodynamics stability between high-κ material and bare Si-sub, the Eq. (1-6) describes that the excess oxygen atoms diffuse through the high-κ metal oxide and react with Si at high temperature. Especially in the ultra-thin film regime, this reaction will cause undesirable interfacial layer more easily.
Therefore, in order to precisely control the EOT of high-κ gate oxide and obtain better interface between gate oxide and Si-sub, we need to find certain high-κ metal oxide which has good thermodynamics stability with Si-sub at high temperature.
1.3.3 Interface Quality
A definite goal of any potential high-κ gate dielectric is to have a sufficiently high-quality interface with Si channel, as close as possible to that of SiO2. And the SiO2 gate dielectric has a midgap interface state density Dit ~2×1010 states/cm2 [6].
However, most of the investigated high-κ materials represent Dit ~1011-1012states/cm2, and exhibit a flatband voltage shift ΔVFB > 300mV [7]. Therefore, in order to obtain an optimal high-κ-Si interface quality, it is critical to understand the origin of the interface properties of any high-κ gate dielectric.
Because of the lattice structure mismatch, there certainly exists some interface defect states between high-κ gate oxide and Si-sub. It is empirically shown that if the average number of bonds per atom Nav>3 at the interface, the interface defect density will increase proportionally, and the device performance will be degraded also. Metal oxides which contain elements with a high coordination, such as Ta and Ti, will have a high Nav, and form an overconstrained interface with Si. And degradation in leakage
current and electron channel mobility is also observed [9]. Furthermore, the silicide bonding which forms near the Si channel interface will tend to give rise to detrimental bonding conditions, leading to significant leakage current and poor carrier channel mobility.
As mentioned earlier in Eq. (1-6), oxygen atoms may diffuse through the high-κ dielectric and react with Si. And ZrO2 and HfO2 have been studied as having high oxygen diffusivities [10]. Although we know that there exists better interface between SiO2 and Si-sub ( Dit ~2×1010 states/cm2), an uncontrolled interfacial SiO2 will severely compromise the capacitance gain from any high-κ material in that gate stack structure. Therefore, the character of resisting to oxygen diffusion in the annealing ambient should be considered when we are assessing the interface stability of high-κ dielectric.
Furthermore, the ideal gate dielectric stack may well turn out to have an interfacial layer composed of several monolayers of Si-O and a high-κ dielectric is used on the top of the interfacial layer. And this stack structure could possess better quality interface like that of SiO2 and higher capacitance because of the high-κ material.
1.3.4 Film Morphology
The work by R. Chandrasekharan et al. investigated the film morphology of high-κ dielectric Ta2O5 and recognized the relation between oxidation time and crystallization temperature [11]. Figure 1.5 shows that no peak of crystalline Ta2O5 is observed until after 1.5min of oxidation. Between 1.5 and 2 min of oxidation, crystalline phases of Ta2O5 begin to appear. Furthermore, as the oxidation time increases, the intensity of crystal formation also increases. And figure 1.6 shows that the surface morphology of Ta2O5 film with different oxidation time. For the 1-min-oxidated sample, no change of surface morphology is observed; for the
3-min-oxided sample, the surface becomes rough and small cracks start to appear while the oxide grains are formed; and the 4-min-oxided one, the surface becomes rougher and more cracks are observed while larger grains are formed.
Because grain boundaries serve as highly leaky paths, it is expected to find a material which remains in an amorphous phase even if the film undergoes high temperature processes.
1.3.5 Gate Compatibility
As mentioned in 1.3.2, when high-κ materials directly contact with Si-sub, they will react with Si and form unfavorable interfacial layers. The similar reactions will also occur when high-κ materials meet poly-Si gate electrodes [12]. Furthermore, the dopant diffusion through high-κ gate dielectric will cause an unfavorable Vth shift [13][14]. And metal gate is one of possible solutions to suppressing dopant diffusion, poly depletion and sheet resistance constraint. In addition, the use of metal gates in gate processes can lower the thermal budge by eliminating the need for the dopant activation of poly-Si electrode [7].
Since doped poly-Si is the incumbent gate electrode material, it should be carried out to investigate how dopants in poly-Si diffuse through high-κ materials. However, current roadmap predicts that the metal gate technology will replace the doped poly-Si gates [15]. It is therefore necessary to focus efforts on dielectric materials systems which are compatible with potential metal gate materials.
1.3.6 Process Compatibility
There are several studying methods to deposit a high-κ dielectric: physical vapor deposition (PVD) [16], chemical vapor deposition (CVD) [12], molecular beam epitoxy (MBE) [4] and sol-gel spin coating method [17][18][19].
PVD principally includes evaporation and sputtering. Though these two PVD methods could be carried out at normal temperature for unlimited substrate materials,
the poor step coverage is the most challenge to deposit an uniform gate dielectric. In a sputtering process, however, the inevitable plasma damage results in surface damage and thereby creates unwanted interfacial states [7].
CVD mainly involves metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). Though most of CVD methods have proven to give more uniform step coverage, the ALD method seems to provide much promise to deposit better-quality high-κ gate dielectrics than that of MOCVD. Furthermore, as far as the throughput and the requirements for instrument are concerned, it is obviously that ALD method is better than MOCVD and MBE methods [7].
This study mainly uses the sol-gel spin coating method to form the high-κ gate dielectrics. However, the more detail introduction about this method will be provided in the next section.
1.4 Sol-Gel Spin Coating Method
Recently, many technologies have been used to prepare various high-κ dielectrics, such as atomic layer deposition (ALD), chemical vapor deposition (CVD) and physical vapor deposition (PVD). Nevertheless, the sol-gel spin coating method also catches much attention; it is utilized to form the high-κ dielectric films [17] and memory charge trapping layers [18][19].
In the sol-gel processes, hydrolysis, condensation, and polymerization, the step-by-step formation leads to a metal-oxide network. And there is an arresting character of sol-gel spin coating method and which is an ability to synthesize new types of high-κ materials, called “inorganic-organic hybrid” [20].
The sol-gel spin coating method could be executed in the normal pressure environment rather than high vacuum system. And thin film formation with spin coating is simpler than ALD, PVD, or MBE to deposit an insulator because of its
cheaper precursors and tools.
1.5 Electron Spectroscopy for Chemical Analysis (ESCA)
In this section it is worth introducing the fundamental principle of ESCA because the most following analysis for material and physical properties are performed by ESCA technique.
ESCA, also known as XPS, is used to characterize the chemical bonding and film composition. Since the photon energy range of interest for material analysis corresponds to the x-ray energy (1-10 keV), photoelectron spectra with specific binding energies produced by x-ray radiation of a sample present chemical bonding information about given elements. Figure 1.7 shows relevant energy levels for ESCA measurements [21]. Binding energies of photoelectrons can be obtained from Eq.
(1-7), based on Figure 1.7.
Ekin =hν −Eb−φspec, (1-7) where Ekin is kinetic energy of the photoelectron, h is Plank’s constant, ν is the frequency of he photon, Eb is the binding energy, and Øspec is the work-function of the spectrometer.
However the ejected photoelectrons from ESCA analysis undergo inelastic energy losses due to collective oscillations (plasmon) and single particle excitation (electron-hole band to band transitions). More importantly, the excitation of a single electron from the valence band to the conduction band can also be detected at the onset of plasma energy loss, as illustrated in Figure 1.8 [22]. This onset point of plasma energy loss can be utilized to determine the band gap energy [23-25].
Photo-excited electrons lose their kinetic energies due to collective oscillations of outer shells, resulting in a plasmon spectrum. Single electron excitation from valence
band edge to conduction band edge also takes place at the onset of a plasmon spectrum. Ec, Ev, Eg, and hν denote conduction band minimum, valence band maximum, band gap energy, and photon energy of X-ray irradiation, respectively.
Figure 1.2 Calculated（lines）and measured（dots）results for tunneling currents from inversion layers through oxides [2].
Figure 1.1 Moore’s law for microelectronic industry. The exponential increase of transistors count as a function of time for distinct generations of microelectronics has been realized [1].
Ba
Fig. 1.4 The symmetric perovskite crystal structure (a) is not polarized when there is no applied electric field. And the applied field polarizes the structure (b).
Figure 1.3 The frequency dependence of the real (εr’) and imaginary (εr”) parts of the dielectric permittivity. In CMOS devices, ionic and electronic contributions are present.
(a) (b)
Fig. 1.5 XRD pattern of Ta thin film oxided at 700 ﾟ C for 1, 1.5, 2,3 and 4 min [11].
Fig. 1.6 The evolution of surface morphology resulted from thermal oxidation at 700 ﾟ C for 1(a), 3(b) and 4(c) min [11].
Fig. 1.8 Illustration of band gap energy by O 1s or N 1s photoelectron energy loss spectrum.
Fig. 1.7 Schematic of the relevant energy levels for XPS binding energy measurements. Note that a conducting specimen and spectrometer are in electrical contact and thus have common Fermi levels.
Schottky
Table 1.1 Basic conduction processes in insulators [6].
⎟⎟⎠
Chapter 2
Experimental Procedures
In this chapter we will illustrate the device fabrication process with figures and list the instruments for material and physical properties measurements.
2.1 Device Fabrication
In this investigation, CoTiO3 films were prepared by sol-gel spin coating method in a controlled environment, where was maintained at 22oC and 43 % RH. The process flow was illustrated in figure 1. First, n-type single crystal Si wafers with resistivity 4-7 Ωcm underwent standard RCA cleaning followed by a dilute-HF dip to remove the native SiO2. Then, the sol-like precursor for CoTiO3 was directly spun on the Si substrates at about 3000 revolutions per minute, and the spin speed was maintained for 30 seconds. However the precursor for cobalt and titanium elements were cobalt acetate tetrahydrate Co(OOCCH3)2．4H2O and titanium isopropoxide Ti(OCHC2H6)4, respectively. These two precursors were dissolved in 2-methoxyethanol for spin coating method. After the spin-coating of the precursor, in order to remove the solvent, the samples were baked at 90oC for 1.5 min on a hotplate.
And the procedure (coating-and-baking) was repeated for 5 times. Afterward the films were oxidized at 400oC in an N2/O2 ambient for 10 min, in which both N2 and O2 flow were 50 sccm. In order to study the properties of CoTiO3 high-k dielectrics after high temperature treatment, rapid thermal annealing (RTA) was performed. The samples were annealed at 600oC, 700oC, 800oC or 900oC for 30s in N2 ambient.
Photolithography was used to define gate areas and then TaN metal was deposited on the top of samples by reactive DC-sputtering. Lift-off was performed to form the MIS capacitors. Thereafter, ohmic contacts were formed by thermal evaporation of 300-nm-thick aluminum (Al) electrode on the backside of the samples.
2.2 Material and Physical Properties Measurements
The microstructure of spin-on CoTiO3 film and Si substrate were studied by JEOL JEM-2100F field emission transmission electron microscopy (TEM) equipped with Link ISIS-300 energy dispersive X-ray analyzer (EDS). And the TEM EDS with a 5-nm electron beam probe was used to perform chemical analysis qualitatively.
The characteristic of crystallization of spin-on CoTiO3 films with different annealing temperature were identified by PANalytical X’Pert Pro X-ray diffraction system under normal atmosphere. Optical module with X-ray mirrors and a parallel plate collimator was used to perform gracing incident X-ray diffraction (angle of incidence θi ~1˚). The beam source originated from Cu Kα radiation with a 0.154-nm wavelength and this beam source was operating at 1.8 kW.
Surface morphology of spin-on CoTiO3 films with different annealing temperature was obtained by Veeco dimension 5000 scanning probe microscope (SPM) under normal atmosphere. The highest resolution in X-Y plane and Z direction were about 1.5 nm and few angstroms, respectively. And the tip curvature radius was about 2 nm.
A ULVAC-PHI Quantera high resolution X-ray photoelectron spectrometer (HR-XPS) with 180˚ spherical capacitor analyzer was used to analyze quantitatively the chemical composition of the dielectrics CoTiO3 prepared by sol-gel coating method.
The capacitance-voltage (C-V) curves and current-voltage (I-V) curves were measured in the same probe station by HP 4284 and Keithly 4200, respectively.
●
Spin coating (CoTiO3)
200oC baking Repeat 5 times 400oC annealing in N2 and O2
RTA (600oC / 700oC / 800oC / 900oC) in N2
Define patterns with photoresist
Lift-off and electrodes formation TaN/Al deposition
Chapter 3 Material Properties
In this chapter, we will report the material properties of spin-on CoTiO3 thin films analyzed by Transmission Electron Microscope (TEM), Energy Dispersive Spectrometer (EDS), Grazing Incident X-Ray Diffraction (GI-XRD), Scanning Probe Microscope (AFM), Auger Electron Microprobe (AEM) and Electron Spectroscopy for Chemical Analysis (ESCA).
3.1 Si-sub/CoTiO
3Interface Quality
In figure 3.1, the graph is the cross-section of Al-electrode/1-coated CoTiO3 thin film/bare Si substrate structure and the CoTiO3 thin film is annealed at 400oC. There are two interfacial layers astride the CoTiO3 thin film. The interfacial layer between Si-sub and CoTiO3 thin film is about 2.23 nm and the interfacial layer between Al-electrode and CoTiO3 thin film is about 1.88 nm. Furthermore, the thickness of the 1-coated CoTiO3 thin film on Si-sub is about 5.27 nm.
In order to qualitatively recognize the composition of the spin-on dielectric, EDS analysis is performed. As shown in figure 3.2 (a), the three principal elements, Cobalt, Titanium and oxygen, are detected. However, as shown in figure 3.2 (b), Al peak and Si peak maybe come from the interfaces beside the dielectric, and the Cu peak should
In order to qualitatively recognize the composition of the spin-on dielectric, EDS analysis is performed. As shown in figure 3.2 (a), the three principal elements, Cobalt, Titanium and oxygen, are detected. However, as shown in figure 3.2 (b), Al peak and Si peak maybe come from the interfaces beside the dielectric, and the Cu peak should