Chapter 3 RF ESD Protection Basics
3.4 I NDUCTIVE ESD D EVICES
3.4.1 ESD Power Spectrum
Typical ESD energy spectrums are illustrated in Fig. 3.3 (c), Fig. 3.4 (c), and Fig.
3.5 (c). It can be concluded that the ESD energy occupy the lower part (at most several hundreds of MHz) of the frequency spectrum as compared to the RF operation frequency (over GHz), as shown in Fig. 3.19 (a). Therefore, a straightforward inference is that it is possible to use a shunted passive device which exhibits low impedance at ESD low frequency but high impedance (or a particular value) at RF high frequency, as shown in Fig. 3.19 (b) [4]. It comes to an inductor. An inductor with inductance L at frequency f exhibits impedance (Z) characterized in equation (3.2)
L f j
Z = ⋅2π ⋅ (3.2)
Therefore, a shunted inductor provides an almost shorted path at low frequency but an almost open circuit condition (or a particular value) at high frequency. Further, in chapter 2 it is showed that in RF circuitry inductors are frequently used in the matching networks. Therefore, an inductor is in potential to be incorporated and co-designed for both RF functionality and ESD protection capability.
Therefore, it has no influence on RF circuit operation but has the capability to provide an almost shorted path to effectively discharge the ESD current. Similar ideas can be extended to the inductor co-design methodology. The ultimate goal is to use a single inductor which can serve both for RF functionality and ESD protection capability. Fig.
3.20 and Fig. 3.21 illustrate some potentially applicable RF circuits using this co-design methodology.
Fig. 3.20 (a) uses a RF choke, as in [4]. Further, this inductance can also be part of the matching network, as shown in Fig. 3.20 (b). For narrowband application, an inductor and a capacitor form a resonant tank, exhibiting an open condition at the resonance frequency. Further, the inductor can also serve as the ESD clamp, and the capacitor can be made by a diode or a SCR to serve an additional ESD clamp, as shown in Fig. 3.21 (a) and (b). In Fig. 3.21 (a) the shunted inductor serves as one part of the I/O ESD clamp and also resonates out all the parasitic capacitance at the I/O terminal. In Fig. 3.21 (b) the SCR is triggered on by the detection and trigger circuit activated by the ESD current flowing through the upward diode string to the power rail, as described in section 3.3.3. Proper design of this RC time constant and the trigger circuit may result in excellent capability to discharge the ESD current. The shunted inductor resonates out the SCR parasitic capacitance at the RF operation frequency, and the detection and trigger circuits are both on the power rail, contributing no parasitic capacitance to the I/O terminal. Therefore, impact on the normal RF performance can be minimized. For ultra-wideband application, the distributed ESD protection structure acts as an artificial transmission line and provide constant characteristic impedance over a considerable wide bandwidth, as shown in Fig. 3.21 (c) [18].
Fig. 3.1 Typical pad layout allocation of a RF system IC.
(a) (b)
(c) (d)
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Fig. 3.3 Pin assignments of ESD test zapping for VDD pads of (a) positive VDD-to-VSS mode and (b) negative VDD-to-VSS mode.
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Fig. 3.4 (a) Equivalent testing circuit models, (b) typical current waveform, and (c) corresponding power spectrum, of human-body-model (HBM) ESD testing.
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Fig. 3.5 (a) Equivalent testing circuit models, (b) typical current waveform, and (c) corresponding power spectrum, of machine-model (MM) ESD testing.
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(b) (c)
Fig. 3.6 (a) Equivalent testing circuit models, (b) typical current waveform, and (c) corresponding power spectrum, of charged-device-model (CDM) ESD testing.
Fig. 3.7 Traditional mixed-voltage I/O interface circuit.
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(b)
(c)
Fig. 3.8 General I/O interface circuit specifically designed for RF application: (a) low-noise amplifier (LNA) as the RF input interface, (b) power amplifier (PA) as the RF output interface, and (c) RF switch as an integrated RF I/O interface.
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(b)
Fig. 3.9 Whole-chip ESD protection of (a) conventional architecture and (b) architecture with signal line blocker.
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(b)
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Fig. 3.10 Power rail ESD clamp with (a) typical architecture, (b) a big NMOS as the main clamp device, and (c) a parasitic bipolar transistor as the main clamp device.
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Fig. 3.11 I/O ESD clamp using (a) a pair of GGNMOS and PGPMOS, and (b) a pair of diodes within the whole-chip ESD protection architecture.
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Fig. 3.12 ESD current under (a) positive, and (b) negative, VDD-to-VSS modes for the I/O ESD clamp using a pair of diodes within the whole-chip ESD protection architecture.
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(c) (d)
Fig. 3.13 ESD current under (a) PS-mode, (b) NS-mode, (c) PD-mode, and (d) ND-mode, for the I/O ESD clamp using a pair of diodes within the whole-chip ESD protection architecture.
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(b)
(c) (d)
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Fig. 3.15 (a) Device cross-sectional view, (b) simplified structural illustration, and (c) equivalent circuit, of another SCR device.
Fig. 3.16 Power rail ESD clamp using SCR device.
Fig. 3.17 Whole-chip ESD protection circuit with the I/O ESD clamp using SCR device.
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(b)
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Fig. 3.18 ESD current under (a) PS-mode, (b) NS-mode, (c) PD-mode, and (d) ND-mode, for the whole-chip ESD protection circuit with the I/O ESD clamp using SCR device.
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Fig. 3.19 (a) Spectral locations of ESD and RF power. (b) Clamp device characteristic in frequency viewpoint.
(a) (b)
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Fig. 3.21 (a) Parallel resonant tank composed of an inductor and a diodes, (b) parallel resonant tank composed of an inductor and a SCR, and (c) distributed ESD protection in potentially applicable RF circuits using inductor co-design methodology.
Chapter 4
Experimental Results
4.1NARROWBAND CLASS-ABPA WITH AN INDUCTIVE ESDDEVICE
In this section the inductor co-design strategy and the signal line blocker concept are demonstrated. An on-chip planar inductor is designed to serve for both the PA output matching network and the output port ESD clamp. A metal-insulator-metal capacitor (MIMCAP) is designed to serve for both the PA output matching network and the signal line blocker. The protected PA is a narrowband class-AB PA designed to operate at 3-GHz and transmit a 0-dBm linear output power for demonstration. The measurement results reveal the truth that this inductor co-design strategy and the signal line blocker concept indeed provide excellent ESD robustness for the PA circuit and cause no degradation on the RF performance.
4.1.1 Design of the PA Circuit and the ESD Protection circuit
The PA circuit is illustrated in Fig. 4.1. The corresponding device parameters are organized in Table 4.1.
The active device core (M1 and M2) is in cascode topology. The cascode topology provides good voltage gain and good isolation. It also prevents drain overstressing since the voltage swing may approach 2 times the VDD. The size and
The input matching network is a simple L-section. The resistor (RIN) provides the real part of the input impedance. The reactive components (CIN and LIN) provide suitable impedance transformation and match the PA input to 50-ohm.
The output matching network (LD, COUT, and LOUT) is a π-section. It transforms the 50-ohm external output loading to the optimal load-line resistance for the cascode pair output.
The inductor, LOUT, in the output matching network also provides ESD protection capability. It serves as a low impedance discharging path for ESD power occupying the lower frequency spectrum. To achieve good ESD protection capability, the metal trace of LOUT is purposefully designed to be as wide as possible. In such manner, the parasitic resistance is minimized and the discharging efficiency of this inductor can be maximized. With this series resistance concern, the inductor parameters are co-designed with the circuits to achieve its normal RF function, the output matching.
The capacitance, COUT, in the output matching network provides an additional ESD protection capability. It serves as a signal line blocker to block out the ESD current from directly penetrating into the active device core. It also acts as a capacitive voltage divider, with respect to the active device core. With COUT the active device core is not directly zapped by the ESD overstress; part of the overstress voltage potential is taken by COUT. Thus, M2 and M1 are protected. Certainly, COUT is also co-designed within the output matching network and serves for normal circuit operation.
The pre-layout simulation results are shown in Fig. 4.2, Fig, 4.3, and Fig. 4.4.
Fig. 4.2 is the matching situations of the PA. Fig. 4.3 is the forward and reverse power transmission of the PA. Fig. 4.4 is the large signal PTC of the PA operating at its maximum output power frequency, 5.2-GHz. The results are organized in Table 4.2.
4.1.2 Chip Implementation
The layout of this narrowband Class-AB PA is shown in Fig. 4.5. The left-handed corner is the input GSG pads. The right-handed corner is the output GSG pads. The up-most pads are for DC bias (VG and VDD).
The post-layout simulation is illustrated in Fig. 4.6, Fig. 4.7, and Fig. 4.8. Fig.
4.6 is the matching situations of the PA. Fig. 4.7 is the forward and reverse power transmission of the PA. Fig. 4.8 is the large signal operation of the PA operating at its maximum output power frequency, 3.64-GHz. The results are organized in Table 4.2.
4.1.3 Measurement Results
The narrowband Class-AB PA is fabricated in a 130-nm mixed-signal/RF CMOS process. The fabricated chip photograph is shown in Fig. 4.9.
The setup for RF functionality measurement is as follow. An Agilent E8364B PNA is the instrument for S-parameters measurement. An Agilent E4448A spectrum analyzer and an Agilent E8257D signal generator are used to extract the power transfer characteristics of the PA. The measurement results of the PA are illustrated in Fig. 4.10, Fig. 4.11, and Fig. 4.12. Fig. 4.10 is the matching situations of the PA. Fig.
4.11 is the forward and reverse power transmission of the PA. Fig. 4.12 is the large signal PTC of the PA operating at its maximum output power frequency, 3.2-GHz.
The results are organized in Table 4.2.
To compare the ESD protection capability, the PA was tested under HBM ESD zapping and MM ESD zapping. The ESD testing set-up is illustrated in Fig. 4.13. The ESD testing parameter arrangement is organized in Table 4.3. Each PA is zapped by a
The S-parameters and the large signal operation data are extracted. The measurement results are organized in Fig. 4.15 to Fig.4.18.
Fig. 4.15 illustrates the S21 and S22 parameters of a set of tested PA zapped by a series of different HBM ESD level. Fig. 4.16 illustrated the large signal PTC of this set of PA (zapped by HBM ESD) operating at its maximum output power frequency, 3.2-GHz.
Fig. 4.17 illustrates the S21 and S22 parameters of a set of tested PA zapped by a series of different MM ESD level. Fig. 4.18 illustrated the large signal PTC of this set of PA (zapped by MM ESD) operating at its maximum output power frequency, 3.2-GHz.
After ESD zapping, it can be seen from the chip photographs that the chip is obviously damaged only after 800V MM test and 1kV MM test. LOUT and COUT are clearly damaged. The RF functionality test also shows that the PA survives all the HBM ESD tests (up to 8kV HBM level). The PA survives up to 400V MM test, and its output terminal exhibits an open circuit after 800V MM test and 1kV MM test. In short, the output terminal which contains LOUT and COUT is not severely damaged until 800V MM test. The inductor co-design strategy and the signal line blocker concept can effectively protect the PA core circuit.
LOUT is damaged at the M8-M7-M6 via, as shown in Fig. 4.14. Via is one of the most fragile points in the metal interconnect. It has a relative small cross-section area and thus the resistance is large. Heat is generated when the ESD current flows through the tiny via cross-section, and finally the via is burned out and melt down. In short, the inductor is burned down and becomes an open circuit.
It is not clear, though, how the ESD current damage the MIMCAP. From the experimental data it can be seen that the output terminal appears as an open circuit after 400 MM test. The PA cannot survive an 800V MM test but does survive an 8kV
HBM test. Therefore, it is not likely that the ESD overstress exceeds the dielectric strength of the MIMCAP insulator and punch through this dielectric. A reasonable guess is that the destructive ESD current rushes toward the MIMCAP and peel off the metal layer of the MIMCAP. From Fig. 4.14 it can also be seen that the MIMCAP metal layer is indeed somehow peeled.
4.1.4 Conclusion
The experimental results of the 3-GHz 0-dBm Narrowband Class-AB PA are organized in Table 4.3 and Fig. 4.19. The ESD protection strategy using an output inductor and a MIMCAP co-designed with the output matching network provides excellent ESD protection capability but cause no degradation on the RF performance.
Since the inductor and the capacitor are designed with RF performance concern from the very beginning of the circuit design, it has no negative impact on the RF circuit performance. The inductor can provide ESD robustness over 8-kV HBM ESD level and 400-V MM ESD level. Both levels far exceed the standard ESD robustness requirement.
4.2UWBCLASS-ABDISTRIBUTED AMPLIFIER WITH LOW-CESDDEVICES
This section demonstrates the truth that a RF PA is in urgent need of ESD protection. An ultra-wideband (UWB) class-AB distributed amplifier (DA) is designed to operate as a 3 to 10-GHz 0-dBm power amplifier and serve as the
ESD protection circuit utilizes an upward diode string and a SCR clamp with detection and trigger circuits. RF and ESD performance is compared between a pure PA without ESD protection circuit and a protected PA under a series of ESD testing to qualify the impact of ESD protection circuits on the RF PA performance. The RF performance of the unprotected distributed amplifier is measured to qualify the influence of ESD zapping on the circuit RF operation. The RF performance of the protected distributed amplifier is measured to qualify the ESD protection strategy in use. The layout of the SCR clamp and the upward diodes are in waffle-structured style which maximizes the peripheral within a given square area. Therefore the ESD capability is further increased; effective capacitance is reduced for a given ESD robustness. It is proved with experimental evidence that a RF PA is in urgent need of ESD protection. The ESD protection circuit certainly provides parasitic capacitance and degrades the RF PA performance; RF PA and ESD protection circuit co-design is of great importance to minimize this negative impact.
4.2.1 Design of the DA Circuit and the ESD Protection circuit
The PA circuit is illustrated in Fig. 4.20. The corresponding device parameters are organized in Table 4.4.
The active device core (M1 and M2) of each stage is in cascode topology. The cascode topology provides good voltage gain and good isolation. It also prevents drain overstressing since the voltage swing may approach 2 times the VDD. The size and bias of the coscode pair is designed to output a particular current that gives the active device core a 50-ohm for its optimal load-line resistance within its operational dynamic range. In such manner the distributed amplifier can simultaneously satisfies a 50-ohm conjugate match and optimal load-line match. The number of stages is decided according to the output power specification.
The input and output artificial line is in band-pass type. The design equation is illustrated in chapter 2. Characteristic impedance of both lines is designed to be 50-ohm. The upper and lower cut-off frequencies are set to be 10-GHz and 3-GHz, respectively.
The ESD protection circuit is shown in Fig. 4.21. The corresponding device parameters are organized in Table 4.5. It contains an upward diode string and a SCR.
For PD-mode, the ESD current is discharge through the upward diode string. For the NS-mode, the ESD current is discharged through the SCR PW-NW diode. For ND-mode, the ESD current first shunted from VDD rail to GND rail through power-rail ESD clamp; then it goes through the SCR PW-NW diodes and discharged.
For PS-mode, there exist two paths. One path is that partial ESD current first go through the upward diode string to the VDD rail and then activates the detection and trigger circuits. The detection and trigger circuits are then turn on the I/O SCR and discharge all the ESD current to GND. The other path is that the ESD current go through the upward diodes and then directly discharged to GND by the power-rail ESD clamp. Since the voltage swing at the PA output port can be as large as about 1 volt while outputting the required output power level, the upward diode string need two diodes for safe operation.
The diodes and SCR in the I/O ESD clamp are both in waffle-structured style.
The layout sketches are illustrated in Fig. 4.22. It has been truth that the discharging capability of an ESD clamp is proportional to its peripheral (to be precise, its cross-sectional area), not to its area. Therefore, the waffle-structured layout can maximize the peripheral within a given square area. In such manner the discharging
Parasitic capacitance added to the output port of a RF amplifier by the ESD protection circuits certainly does degrade the circuit performance. The artificial line gives the circuit design an edge to minimize this effect. The parasitic capacitance at output port can be somehow absorbed into the artificial line and co-designed to minimize its impact on gain and bandwidth.
The pre-layout simulation results of an unprotected DA are shown in Fig. 4.23, Fig, 4.24, and Fig. 4.25. Fig. 4.23 is the matching situations of the unprotected DA.
Fig. 4.24 is the forward and reverse power transmission of the unprotected DA. Fig.
4.25 is the gain and OP1dB versus frequency of the unprotected DA. The results are organized in Table 4.6.
4.2.2 Chip Implementation
The layout of this ultra-wideband Class-AB distributed amplifier is shown in Fig.
4.26. The left-handed corner is the input GSG pads. The right-handed corner is the output GSG pads. The up-most pads are for VDD bias. The up-most pads are for VDD bias. The bottom-most pads are for VG bias.
The parasitic capacitances (mainly by the SCR and diodes) contributed by the ESD protection circuit are extracted by a Layout Parasitic Extraction (LPE) CAD tool.
Then the extracted capacitances can be incorporated to do the post-layout simulation, and the effect of the ESD protection circuit on the DA can be obtained.
The post-layout simulation of the unprotected DA is illustrated in Fig. 4.27, Fig.
4.28, and Fig. 4.29. Fig. 4.27 is the matching situations of the DA. Fig. 4.28 is the forward and reverse power transmission of the DA. Fig. 4.29 is the gain and OP1dB versus frequency of the DA. The post-layout simulation of the protected DA is illustrated in Fig. 4.30, Fig. 4.31, and Fig. 4.32. Fig. 4.31 is the matching situations of the DA. Fig. 4.32 is the forward and reverse power transmission of the DA. Fig. 4.33
is the gain and OP1dB versus frequency of the DA. The results are organized in Table 4.6.
4.2.3 Measurement Results
The ultra-wideband Class-AB distributed amplifier is fabricated in a 130-nm mixed-signal/RF CMOS process. The fabricated chip photograph is shown in Fig.
4.33. The DA at the left hand side is the protected DA; the DA at the right hand side is the unprotected DA.
The setup for RF functionality measurement is as follow. An Agilent E8364B PNA is the instrument for S-parameters measurement. An Agilent E4448A spectrum analyzer and an Agilent E8257D signal generator are used to extract the power transfer characteristics of the PA. The measurement results of the unprotected DA are illustrated in Fig. 4.34, Fig. 4.35, and Fig. 4.36. Fig. 4.34 is the matching situations of the DA. Fig. 4.35 is the forward and reverse power transmission of the DA. Fig. 4.36 is the gain and OP1dB versus frequency of the DA. The measurement results of the protected DA are illustrated in Fig. 4.37, Fig. 4.38, and Fig. 4.39. Fig. 4.37 is the matching situations of the DA. Fig. 4.38 is the forward and reverse power transmission of the DA. Fig. 4.39 is the gain and OP1dB versus frequency of the DA.
The setup for RF functionality measurement is as follow. An Agilent E8364B PNA is the instrument for S-parameters measurement. An Agilent E4448A spectrum analyzer and an Agilent E8257D signal generator are used to extract the power transfer characteristics of the PA. The measurement results of the unprotected DA are illustrated in Fig. 4.34, Fig. 4.35, and Fig. 4.36. Fig. 4.34 is the matching situations of the DA. Fig. 4.35 is the forward and reverse power transmission of the DA. Fig. 4.36 is the gain and OP1dB versus frequency of the DA. The measurement results of the protected DA are illustrated in Fig. 4.37, Fig. 4.38, and Fig. 4.39. Fig. 4.37 is the matching situations of the DA. Fig. 4.38 is the forward and reverse power transmission of the DA. Fig. 4.39 is the gain and OP1dB versus frequency of the DA.