Chapter 5 Failure Analysis
5.2.3 Operation of the Low-C ESD Clamps during ESD
From the I-V curves, it can be concluded that the SCR devices exhibit no obvious snapback in both the I/O ESD clamp and the power-rail ESD clamp. The SCR devices were turned on. Therefore, when PS-mode ESD zapping, ESD current cannot be discharged by the I/O SCR but by the upward diodes to the VDD rail.
Certainly the power-rail SCR cannot discharge the ESD current since both the I/O SCR and the power-rail SCR are in the same structure. The only reasonable guess is that the ESD charges on the VDD rail can be discharged by the RC-inverter, which acts as the ESD detection and trigger circuit. This hypothesis is illustrated in Fig. 5.6 and the details are addressed as follow.
When VDD-to-VSS-mode ESD zapping, since the SCR is inactive, the ESD current is detected by the RC time constant and discharged directly by the activated PMOS of the inverter. The ESD current flows from the source to the drain of the PMOS. Finally it is discharged to the GND through the P-well resistor in the SCR structure.
When PS-mode ESD zapping, the ESD current first goes to the VDD rail through the up-ward diodes. Then the ESD charges on the VDD rail is discharged by the same mechanism as described in the case of VDD-to-VSS-mode ESD zapping. The upward diodes consist of two diodes, and thus they contribute an additional voltage drop of about 1.6-volt (0.8-volt diode turn-on voltage drop for a single diode) for the PS-mode ESD zapping I-V curve, as compared to the VDD-to-VSS-mode ESD zapping I-V curve. The measured I-V curves confirm this hypothesis.
Two of the most fragile locations of this RC-PMOS discharging path are expected to be the gate oxide of the PMOS and NMOS of the inverter and drain-to-source discharging path of the PMOS. The gate oxide dielectric can be punched through by the strong electrical filed caused by the high voltage potential of the accumulated ESD charges. This overstressing voltage potential is about 5-V for devices of a 130-nm CMOS process. On the other hand, the ESD current flows through the PMOS channel which is basically a resistive current path. Heat is generated and finally burns through the PMOS drain-to-source channel. On both cases, the leakage current shall rise. The measured I-V curves and the SEM photos also confirm this hypothesis.
One last question remains. Why is the SCR not activated? Although there is indeed current flowing through the P-well resistor, the RPWELL in Fig. 5.6 (b), the P-well resistor is too small to generate the cut-in voltage enough to activate the lateral NPN bipolar transistor. It is because the p-plus trigger nodes inserted between the P-well and N-well are so numerous that they act as numerous resistors in parallel. The effective resistance is the resistance of the P-well resistance with a single p-plus trigger nodes divided by the number of the trigger nodes. In such sense, the effective RPWELL resistance is quite small. The base terminal of the lateral NPN bipolar transistor is effectively shorted to the emitter terminal, and the NPN bipolar transistor is difficult to be activated.
Therefore, it can be conclude that the trigger nodes of a SCR device cannot be placed much. Otherwise the SCR cannot be triggered on easily for that the RPWELL
resistance is too small to generate the required cut-in voltage to activate the NPN
devices to guarantee fast and effective turning, and the whole-chip ESD protection architecture with the proposed waffle-structured SCR can bring the protected circuit maximal ESD robustness.
MIMCAP current and (b) the reflected current.
1 2 3 4
Fig. 5.2 The DC I-V curves of (a) output pad to GND pad after PS-mode zapping and (b) VDD pad to GND pad after VDD-to-VSS-mode zapping.
(a) (b)
Fig. 5.3 The pulse I-V curves of (a) output pad to GND pad after PS-mode zapping and (b) VDD pad to GND pad after VDD-to-VSS-mode zapping.
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
Fig. 5.4 The TLP I-V curves of (a) output pad to GND pad after PS-mode zapping, (b) VDD pad to GND pad after VDD-to-VSS-mode zapping, and (c) the TLP testing instrument set-up schematic.
(a)
(b)
Fig. 5.5 The SEM photos of (a) the PMOS of the RC-inverter and (b) the observably damaged location of the PMOS.
(a)
(b)
Fig. 5.6 Circuit schematics of (a) the whole-chip ESD protection circuit with low-C SCR clamp for the DA and (b) the SCR device.
Chapter 6
the ESD protection circuit, and novel ESD protection strategy specifically designed for a RF PA must be incorporated.RF PA circuitry has a distinctive structure that is far different from the traditional mixed-signal I/O circuitry. The RF PA circuitry incorporates numerous passive devices in between the active device core and the output terminal pad. Therefore, traditional dc leakage current test is not enough for ESD testing failure criterion;
complete RF functionality test must be utilized for the ESD testing failure criterion of a RF PA. It is proved with experimental evidence that an ESD event can damage the passive device network of the RF PA output terminal and causes degradation on the RF PA performance. In such cases only RF functionality test can reveal this kind of negative effect.
Two ESD protection strategies are proposed to provide the urgent need of ESD protection for RF PA circuitry. One is to use an inductive ESD device to distinguish an ESD event from normal RF signals. The other is to use capacitive ESD clamps but with low parasitic capacitance.
The inductive ESD device can be co-designed with the RF PA output matching
network. It can be simply an inductor shunted to ground at the RF PA output terminal.
This inductor can be the low impedance discharging path for an ESD event whose power spectrum occupies the lower frequency range. It can also be co-designed to become a part of the output matching network and thus causes no negative impact on the RF PA performance. Further, a MIMCAP in series can act as a signal line blocker which blocks out the ESD current from directly penetrating into the RF PA core. measurement results verify this ESD protection strategy and reveal the truth that ESD protection technique in use indeed provide excellent ESD robustness up to 8kV HBM ESD level and 400V MM ESD level.
The low-C ESD device is a SCR with detection and trigger circuit incorporated in the whole-chip ESD protection architecture which utilizes an upward diode string to divert part of the ESD current to the power-rail and activate the detection circuit, trigger circuit, and the power-rail ESD clamp. The SCR and the diodes are in waffle-structured layout style which can maximize the discharging peripheral within a given layout area. Therefore, the waffle-structured layout style can provide maximum ESD protection capability but contributing minimum parasitic capacitance. This ESD protection strategy is designed and fabricated in a standard 0.13-µm CMOS process. A
measured, and compared to understand the influence of ESD zapping. The measurement results prove that an unprotected DA cannot survive any ESD zapping.
The gain and output power capability of an unprotected DA are largely degraded ever since a 1kV HBM test and a 100V MM test. It can be concluded that an unprotected RF PA may not survive any single ESD zapping; RF PA circuitry is in urgent need of ESD protection.
On the other hand, the measurement results verify the low-C ESD protection strategy and reveal the truth that this ESD protection technique in use indeed provide excellent ESD robustness up to 8kV HBM ESD level and 800V MM ESD level. The RF PA performance will certainly be degraded by the parasitic capacitance contributed by the ESD protection circuit. The ESD protection circuit needs to be co-designed with the protected RF PA, and novel ESD device with low parasitic capacitance is still being sought.
6.2 F
UTUREW
ORKSTo further understand the effect of ESD zapping on the fabricated RF PAs and the proposed ESD protection strategies, more ESD testing needs to be carried out for further analysis.
The fabricated chips needs to be further verified under the four modes of ESD testing, namely, the PS, NS, PD, and ND modes for completion. Further, TLP testing needs to be carried out to understand the exact ESD behaviors of the ESD clamp devices. After all the ESD testing is completed, failure analysis is to be done for those chips whose RF functionality is damaged by ESD zapping; fully understanding of the ESD protection strategies can be obtained.
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簡歷 簡歷 簡歷 簡歷
姓名：蒙國軒 學歷：
台北市立建國高級中學 (89 年 9 月 ~ 91 年 6 月)
國立交通大學電子工程學系 (91 年 9 月 ~ 95 年 1 月)
國立交通大學電子研究所碩士班 (95 年 2 月 ~ 96 年 10 月)