Test and Experimental Results
5.4 Experimental Results
The die photomicrograph of the experimental open-loop ADC is shown in Fig. 5.4.
The whole chip is filled with dummy metal cells because of design rule of metal density. The prototype is fabricated in a TSMC CMOS 0.13-μm 1P8M process. The measured results are presented in the following.
Figure 5.4. Die photomicrograph of the prototype chip.
In Fig. 5.5 (a) and Fig. 5.5 (b), the transient results of the ADC are shown. Fig.
5.5 (a) shows the output clock signal, phid. The frequency of the phid signal, 43.75 MHz, is one over sixteen of the frequency of the cksource signal, 700 MHz, as we
expected. The digital output streams of the DUT are estimated by the logic analyzer.
After an ideal DAC the plot chart is shown in Fig. 5.5 (b).
(a)
(b)
Figure 5.5. Measured results of (a) output clock and (b) plot chart.
Integral nonlinearity (INL) and differential nonlinearity (DNL) are calculated based on code-density measurement of the digital output codes in Fig. 5.6. With a 43-MHz sinusoidal signal at 700-Msample/s conversion rate, peak INL is 0.75 LSB and peak DNL is 0.61 LSB.
0 10 20 30 40 50 60
0.5 0 0.5
DNL(LSB)
0 10 20 30 40 50 60
DIGITAL OUTPUT CODE
INL(LSB)
1 0.5 0 0.5 1
Figure 5.6. Measured INL and DNL.
Fig. 5.7 shows the output spectrum of the converted data at 700 Msample/s. The spectrum of the sampled signal is folded between 0 to 21.875 MHz because of decimation by 16. With a 256-kHz input, SNDR and SFDR of the ADC are 30.99 dB
and 41.34 dB, respectively. Near Nyquist sampling, SNDR and SFDR of the ADC are 30.39 dB and 39.58 dB, respectively.
Magnitude (dB)
Index of 8192pt FFT
0 1000 2000 3000 4000
Index of 8192pt FFT
0 1000 2000 3000 4000
Figure 5.7. (a) FFT of 256-kHz input at 700 Msample/s. (b) FFT of 349.9-MHz input at 700 Msample/s.
dB
Figure 5.8. (a) SNDR and SFDR versus conversion rate with 80-MHz input. (b) SNDR and SFDR versus input frequency at 700 Msample/s.
Shown in Fig. 5.8 (a) and 5.8 (b), with the input signal of 80 MHz, the frequency operating range is from 500 Msample/s to 700 Msample/s. For clock rate beyond 700 Msample/s, the sampling circuit and comparators are not fast enough. When the sampling frequency is lower than 500 Msample/s, just as described before, the Vout
decays with time constant equals toRoutCH /
(
1−A)
. When sampling rate is fixed at 700 Msample/s with different input frequencies, SNDR is almost constant over Nyquist frequency.Discussions To compare with simulation results, the SNDR is about 3 dB decayed. The reasons are discussed below:
1. Just as described in Section 3.5.1, differential circuits exhibit an odd-symmetric
input/output characteristic, and the even-order terms must be zero. In Fig. 5.7 (a), the second tone is -50.1 dB, and in Fig. 5.7 (b), the second tone is -39.58 dB, even higher than the third tone, -41.75 dB. So the mismatch must affect the performance a lot. Figure 5.9 shows the Monte Carlo simulation (100 samples) of track-and-hold circuit. The resistance coefficient of variation is 0.74 % and the second tone is about in the range of -50 dB to -45 dB, much higher than the ideal case.
Figure 5.9. The Monte Carlo simulation of track-and-hold circuit.
2. To count the noise and distortion separately, the signal-to-noise ratio is 33.04 dB and the signal-to-distortion ratio is 35.23 dB in Fig. 5.7 (a). And in Fig. 5.7 (b), the signal-to-noise and the signal-to-distortion ratio are 31.85 dB and 35.08 dB, respectively. It is obviously that noises limit the performance and may be caused by
0 5 10 15 20 25 30 35
-90~ -70 -70~ -65 -65~ -60 -60~ -55 -55~ -50 -50~ -45 -45~ -40 -40~ -35 dB
%
2nd tone
analog circuit and digital circuit. But the turn-on clock, 0.85 V, and the common-mode voltage used in the analog part are not separated. The other reason is that the reference voltage is provided off chip. If the reference buffers are used, the ADC noise will not be affected by the bond wire and the line on the PCB.
5.5 Summary
The experimental results of the prototype ADC was presented in this chapter. Because of the open-loop architecture, the power consumption of the ADC is low. The summary of experimental results of the prototype ADC is shown in Table 5.1.
Table 5.1. Summary of measured results of the pipelined ADC.
Technology
Chapter 6
Conclusions
With the trend of fast technology scaling down, low supply voltage exhibits low cost for digital circuit but stringent constraints for analog circuit design.
Analog-to-digital converters, providing the link between the analog world and the digital system, suffer the analog design constraints but is usually demanded to operate as fast as the digital circuits, result to be a bottleneck in data processing applications.
In this research, a 700-MHz 6-bit pipelined ADC was implemented by using current-switching open-loop residue amplification and global-gain control techniques. The open-loop residue amplification provides efficient power strategy in conversion stage design. For the measurement results of the prototype fabricated in a TSMC CMOS 0.13-μm 1P8M technology, the power dissipation is 16.44 mW for analog circuits and 7.66 mW for the rest of digital circuits at 700 MHz.
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