The Design of Pipelined Analog-to-Digital Converter
3.4 Low-Power High-Speed Conversion Stage Design
3.4.2 Multiplexed-Input Architecture
(a) (b) Figure 3.14. Source degeneration applied to a differential pair.
A differential pair can be degenerated as shown in Figs. 3.14(a) and 3.14(b).
In Fig. 3.14(a), ISS flows through the degeneration resistors, thereby consuming a voltage headroom of ISSRS 2, an important issue if a high level of degeneration is required. The circuit of Fig. 3.14(b), on the other hand, does not involve this issue but it suffers from a slightly higher noise (and offset voltage) because the two tail current sources introduce some differential error.
3.4.2 Multiplexed-Input Architecture
Fig. 3.15(a) shows the single-ended version of a multiplexed-input SHA originally proposed by Ryan [19] and later modified by Petschacher et al. [20]. It
consists of transconductance amplifiers Gm1, Gm2 and transresistance amplifier R.
Nominally, Gm1R = Gm2R = 1. Amplifiers Gm1 and Gm2 are controlled (i.e.,
multiplexed) by CK andCK. During sampling, Gm1 is enabled, Gm2 is disabled, and Gm1 and R operate as a unity-gain amplifier, allowing Vout to track Vin. Note that the acquisition time constant is given primarily by the output resistance of R and the value of CH. In the transition to the hold mode, Gm1 is disabled, Gm2 is enabled, and Gm2 and R are configured as a unity-gain amplifier, thereby retaining the sampled value of Vin across CH.
Gm1 R
Gm2
CH
Vin Vout
CK CK
(a)
Rout A
CH VX
Vout
(b)
Figure 3.15. Multiplexed-input architecture. (a) Basic (single-ended) circuit; (b)
In order to illustrate the hold-mode operation, a simplified version of the circuit is shown in Fig. 3.15(b), where A = Gm2R (≈ 1) and Rout represents the open-loop output resistance of the amplifier. Assuming CH is charged to a voltage Vo at the end of the acquisition mode and neglecting the input bias current of A, the following equation can be arrived:
dt C dV R
V
V out
H out
X
out − =−
, (3.20)
and
out
X AV
V = , (3.21)
Thus,
τ V t
Vout = oexp− , (3.22)
where τ =RoutCH/
(
1−A)
and the origin of time is the beginning of the hold mode. Equation (3.22) shows that if A = 1, then τ =∞; i.e., the droop rate is zero and Vout will remain at Vo definitely. If A= 1−ε, then Vout decays with a time constant equals to RoutCH /ε; i.e.; the droop time constant is 1/ε times the acquisition time constant. While achieving high speed, the architecture of Fig.3.15 entails several challenges if employed for high-resolution applications. The acquisition time constant and the droop rate trade off according to the deviation of A from unity.
M1 M2 Vin
ISS R
VDD R
M3 M4
Vout
Rs1 Rs1 Rs2 Rs2
CK CK
CH
CK M7CK M8
M5 M6
Figure 3.16. Schematic of multiplexed-input architecture.
The circuit detail is shown in Fig. 3.16. To allow proper operation, the equivalent gain of track and hold mode, corresponding to gm1,2R/(1+gm1,2Rs1) and )gm3,4R/(1+gm3,4Rs2 , must be equal to unity. During sampling, CK = high, M1,2 turn on and M3,4 turn off, so Vout tracks the value of Vin. In the transition to the hold mode, CK = low, M3,4 turn on and M1,2 turn off, so Vout holds the value stored in CH, which equals to Vin. Just as described before, transmission-gate switches need rail-to-rail clock swing and large W/L ratios, the speed will be limited by turn-on resistance. And the rise/fall time of full swing non-overlap
clock is about 0.2 ns for a 0.13-μm CMOS technology, the ADC barely operates over 500 MHz. Additionally, a frequency-dependent nonlinearity error in MOS sampling circuits arises from the variation of the switch on-resistance with the input voltage. For high-frequency inputs, this variation introduces input-dependent phase shift and hence harmonic distortion. On the contrary, current-steering method can replace conventional transmission-gate switches with the turn-on voltage 0.85 V and the turn-off voltage 0.35 V. Therefore, it consumes less power consumption. And there is no voltage drop and nonlinearity proportional to input frequency, so the ADC can operate with wide bandwidth input signal.
Likely, the MDAC with the multiplexed-input architecture by current-steering method is shown in Fig. 3.17. During sampling, Gm1,3 are enabled, Gm2,4 are disabled, and Gm1 and R1 operate as a unity-gain amplifier, allowing Vout1 to track Vin. In the hold mode, Gm1,3 are disabled, Gm2,4 are enabled, and Gm2R1 = Gm4R2 = 1, thereby
2
ref i in o
D V V
V = + × , (3.23)
and hence
where Di is the converted Residue-Signed-Digit (RSD) code of coarse ADC and can be +1,0, or -1, Vout is the stage output, Vin is the stage input, Vin+1 is the input of the next stage, and Vref is the reference voltage. However, the parasitic capacitance CP at the input node of an open-loop amplifier attenuates the input voltage by a factor of CH/(CH+CP). Therefore, the gain of the open-loop amplifier must be compensated in addition to the nominal amplification gain of 2. So the proposed global-gain control techniques [8] are used to compensate it.
Gm1
Figure 3.17. MDAC of multiplexed-input architecture.
M 1 M 2
Figure 3.18. Schematic of MDAC with multiplexed-input architecture.
The proposed current-steering MDAC circuit is shown in Fig. 3.18. During sampling, CK = high, M1,2,5,6 turn on and M3,4,7,8 turn off, so Vin is stored on the top plate of CH by setting gm1,2R1/(1+gm1,2Rs1) to be unity. On the bottom plate of CH, the node voltage is Vcm no matter how much the gain is. MP also turns on to reduce the equivalent resistance even if R2 is large, so the acquisition speed (proportional to R and C time constant) can be fast. In the hold mode, MP turns off to increase equivalent resistance to R2 and reduce the droop rate. Let the gain equal to unit, Vo will be Vin +Di×(Vref /2). With the open-loop residue
amplifier, Vout will become 2×(Vin +Di×Vref /2). The programmable load resistance, R2 in parallel Mp, allows the MDAC to diminish droop rate in hold mode while achieving fast sampling speed.And for the same common-mode bias, current can be small to make the same IR drop, so the power consumption can be reduced.
Fig. 3.19 shows the open-loop residue amplifier. The gain is adjusted by varying the gate voltage (Vctrl) of source degeneration NMOS to avoid the variation of DC operation point. The control voltage is generated by global-gain control described later.
M 1 M 2 V in
R
V DD R
I SS
ctrl
V
I SS
M 3 M 4 R
V DD R
I SS
ctrl
V
I SS V out
0.7mA
Figure 3.19. Open-loop residue amplifier.