EXPERIMENTAL RESULTS 117

Figure 7.19: Measured SNDR and SFDR versus finat normal calibration.

is a differential 1.4Vpp 9.99MHz sinusoidal signal. Without calibration, the offset error is the dominant distortion term. The signal-to-distortion-plus-noise (SNDR) is 54.4 dB and the spurious-free dynamic range (SFDR) is 55.6 dB. After the calibration is activated, the SNDR is improved by 15.5 dB to 69.9 dB and the SFDR is improved by 36.3 dB to 91.9 dB. Fig. 7.19 shows the ADC’s measured SNDR and SFDR versus input frequencies at 125 MS/s sampling rate. The calibration can improve the SNDR by more than 10 dB and the SFDR about 30 dB when the input frequencies up to the Nyquist frequency.

Fig. 7.20 shows the ADC’s measured SNR and SFDR versus input signal levels with the calibration on and off respectively by applying a sinusoid at the frequency of 1.99MHz.

This results reveal that the noise power excluding the distortion is not affected by the input levels, and the injected random term, q × Vr. The measured dynamic range is approxi-mately 73 dB at the supply voltage of 1.8 V.

Fig. 7.21 shows the ADC’s measured signal-to-noise ratio (SNR) versus input fre-quencies at 125 MS/s sampling rate. The input is a differential 1.4 Vpp9.99MHz sinusoidal signal. The SNR is calculated from the ADC’s output FFT spectrum while ignoring the

Figure 7.20: Measured SNR and SFDR versus input levels.

Figure 7.21: Measured SNR versus input frequencies.

7.7. SUMMARY 119

harmonic tones caused by A/D nonlinearity and the spurious tones caused by inter-channel offset and gain mismatches. Also shown in Fig. 7.21 is the calculated SNR of an ADC model which includes the effect of sampling clock jitter ∆t. Its input is A sin(2πfint)+nex

where nexis an external noise source. Its SNR can be expressed as [55]:

SNRn+j = A²/2 2π²f_in²A²∆t²+ n²ex

(7.1) By curve-fitting (7.1) against measured data, the root-mean-square (rms) value of nex is estimated to be nex,rms = 137 µV, and the rms value of ∆t is estimated to be ∆trms = 0.82 psec.

7.7 Summary

The comparisons of this prototyping ADC with other works are described in the follow-ing. Table 7.4 shows the measured specifications of this ADC chip and compare it with published works that claim to have a maximum sample rate of more than 100 MS/s and a resolution of more than 14 bits.

Fig. 7.22 shows the performance of pipelined and time-interleaved pipelined ADCs of more than 12-bit resolution reported in the Custom Integrated Circuits Conference (CICC), International Solid-State Circuits Conference (ISSCC), Journal of Solid-State Circuits (JSSC), and commercial product’s data sheets of Analog Device and Texas In-struments Incorporated. The corresponding references are listed in Table 7.5. The 12-bit, 13-bit, 14-bit, 16-bit designs implemented using different technologies are labeled, as well as this work. The ADCs with outstanding performance are highlighted using the corre-sponding item in Table 7.5. The results indicate that BiCMOS implementations can have better effective number of bits (ENOB) and faster sampling rate than CMOS implemen-tations. This is true because BiCMOS is the best technology for the design of an opamp in all aspects except for money cost when it combines the benefits of Bipolar and those of CMOS [58]. The qualitative comparison for an opamp implemented using CMOS, Bipolar and BiCMOS technology is shown in Table 7.6 [59].

For a high resolution ADCs, two dominant noise sources are the thermal noise and the aperture noise. If the thermal noise is considered as the only noise source, the reachable

Table 7.4: Performance Comparison

This Work [3] [56] [57]

Technology 0.18 µm CMOS 0.13 µm CMOS 0.35 µm BiCMOS 0.35 µm BiCMOS

Architecture TI Pipelined Pipelined Pipelined TI Pipelined

Calibration Digital Background Digital Background None Digital Foreground

Supplies 1.8 V 1.5 V 3.3 V/5 V 3.0 V

Input Range (Vpp) 1.4 V 1.5 V 2 V 4 V

Power Consumption 0.909 W 0.224 W 1.95 W 1.4 W

Resolution 15 Bits 14 Bits 14 Bits 14 Bits

Max. Sampling Rate 125 MS/s 100MS/s 125 MS/s 100 MS/s

DNL (LSB) −0.27/+0.25 −1.1/+1.1 −0.2/+0.2 0.97

INL (LSB) −5.7/+5.5 −2.0/+2.0 −0.5/+0.5 6.9

SNR (@fin= 5 MHz) 70.4 dB 70 dB 75 dB

SNR (@fin= 49 MHz) 67.3 dB 65 dB 75 dB

THD (@fin= 5 MHz) −81.7 dB −71.1 dB THD (@fin= 49 MHz) −76.9 dB −68 dB

THD (@fin= 210 MHz) −76.3 dB

SFDR (@fin = 5 MHz) 91.6 dB 100 dB

SFDR (@fin = 70 MHz) 82.9 dB 95 dB

SFDR (@fin = 210 MHz) 79.9 dB

Active Area 18.5 mm² 1.02 mm² 70 mm² 10.2 mm²

7.7. SUMMARY 121

Table 7.5: Nyquist-rate ADC Survey

Item Publication/ Sampling ENOB

Author Title

Year Rate (MS/s) (bits)

CMOS

1 ISSCC / 2006 100 10.5 P. Bogner, etc. A 14b 100MS/s Digitally Self-Calibrated Pipelined ADC in 0.13µm CMOS

2 ADI / 2006 125 11.8 Analog Device AD9246 Data Sheet 3 ADI / 2006 150 11.9 Analog Device AD9254 Data Sheet

4 JSSC / 2005 110 10.7 T. N. Andersen, etc. A Cost-Efficient High-Speed 12-bit Pipeline ADC in 0.18-µm Digital CMOS

5 CICC / 2005 180 10.6 k. Gulati, etc. A Highly-Integrated CMOS Analog Baseband Transceiver with 180MSPS 13b Pipelined CMOS ADC and Dual 12b DACs 6 Texas In. / 2005 125 11.3 Texas Instrument ADS5500 Data Sheet

7 JSSC / 2005 80 11.8 C. R. Grace, etc. A 12b 80MS/s Pipelined ADC with Bootstrapped Digital Calibration

8 ISSCC / 2004 50 12.5 K. Nair, etc. A 96 dB SFDR 50MS/s Digitally Enhanced CMOS Pipeline A/D Converter

9 JSSC / 2003 75 11 B. Murmann, etc. A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification

10 JSSC / 2001 54 10.5 H. v. d. Ploeg, etc. A 2.5-V 12-b 54-MSample/s 0.25-µm CMOS ADC in 1-mm² with Mixed-Signal Chopping and Calibration

11 JSSC / 2001 75 12 W. Yang, etc. A 3-V 340-mW 14-b 75-MSample/s CMOS ADC with 85-dB SFDR at Nyquist Input

12 ISSCC / 2000 65 11.6 L. Singer, etc. A 12b 65MSample/s CMOS ADC with 82dB SFDR at 120MHz 13 JSSC / 2000 50 10.5 H. Pan, etc. A 3.3-V 12-b 50-MS/s A/D Converter in 0.6-µm CMOS with

over 80-dB SFDR

14 ISSCC / 1997 128 10.1 R. Jewett, etc. A 12b 128MSample/s ADC with 0.5LSB DNL BiCMOS

15 JSSC / 2006 125 12.5 A. M. Ali, etc. A 14-bit 125-MS/s IF/RF Sampling Pipelined ADC with 100dB SFDR and 50fs Jitter

16 Texas In. / 2006 170 11.4 Texas Instrument ADS5545 Data Sheet 17 Texas In. / 2006 210 12.1 Texas Instrument ADS5547 Data Sheet

18 JSSC / 2005 65 12.9 A. Zanchi, etc. A 16-bit 65-MS/s 3.3-V Pipeline ADC Core in SiGe BiCMOS with 78-dB SNR and 180-fs Jitter

19 ADI / 2005 100 13.1 Analog Device AD9446 Data Sheet

20 Norchip / 2004 100 12.1 V. Hakkarainen, etc. A 14b 200MHz IF-Sampling A/D Converter with 79.9dB SFDR Bipolar

21 JSSC / 2000 100 12.5 A 14-bit 100-MSample/s Subranging ADC

Figure 7.22: High-resolution (≥ 12 bits) high-speed (≥ 50 MS/s) pipeline and time-interleaved ADCs.

Table 7.6: Qualitative Comparison for An Opamp Implemented Using Bipolar, CMOS and BiCMOS Technologies

Qualitative Comparison CMOS Bipolar BiCMOS

High Gain √ √

High Gain-Bandwidth Product √ √

Ease of Compensation √ √

Low Voltage Noise √ √

Low Current Noise √ √

Low Power Supply Limit √ √

Common Rejection √ √ √

Low Voltage Offset √ √

High Input Impedance √ √

7.7. SUMMARY 123

Figure 7.23: Figure of merit.

resolution is given by

N_thm = 1

2log₂ V_{F S}² 6kT Ref ff_s

!

−1 (7.2)

where k is the Boltzmann’s constant, T is the absolute temperature, fs is the sampling rate, and Ref f is an effective thermal resistance, which includes the effects of all noise sources [60]. If the aperture noise is only considered, the attainable resolution is limited as

N_apt = log₂

 2

√3πf_sσ_a



−1 (7.3)

where σ_a is the rms aperture jitter [60]. Both N_thm and N_apt boundaries are plotted in Fig. 7.22 with Ref f = 300 Ω and σ^a = 0.1 psec. The thermal noise truly limits the resolution above 14 bits. The aperture jitter degrades the available resolution more as the sampling rate increases. However, the designs labeled in Fig. 7.22 do not close to the limitation due to physical uncertainty, so does this work.

The figure of merit, the energy per conversion step, defined as Econv = Pd

2^ENOB× f_s (7.4)

is widely used to evaluate the efficiency of ADCs, where Pd is ADC’s power dissipation, and fs is ADC’s sampling rate. Fig. 7.23 shows the efficiency comparison of the ADCs surveyed in Table 7.5 which have the resolution more than 14 bits and the sampling rate more than 100 MS/s. The three boundaries of Econv = 1 pJ, Econv = 2 pJ and Econv = 3 pJ are also plotted in Fig. 7.23 to clearly exhibit this comparison. Most designs locate between Econv = 1 pJ and Econv = 2 pJ. The CMOS design of reference 3 has the best conversion efficiency among these references. BiCMOS designs reveal better 2^ENOB× f_s, but larger power consumption. The design of reference 17 has outstanding efficiency among the BiCMOS designs. Although it has little worse conversion efficiency than that of CMOS designs of reference2 and 3, it has much better 2^ENOB× f_s.

Chapter 8