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### Design of High-Performance Time-Interleaved

### Pipelined Analog-to-Digital Converters

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### Design of High-Performance Time-Interleaved

### Pipelined Analog-to-Digital Converters

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### Student : Zwei-Mei Lee

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### Advisor : Jieh-Tsorng Wu

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### A Dissertation

### Submitted to Department of Electronics Engineering

### and Institute of Electronics

### College of Electrical Engineering

### National Chiao-Tung University

### in partial Fulfillment of the Requirements

### for the Degree of

### Doctor of Philosophy

### in

### Electronics Engineering

### June 2007

### Hsin-Chu, Taiwan, Republic of China

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### Design of High-Performance Time-Interleaved

### Pipelined Analog-to-Digital Converters

### Student : Zwei-Mei Lee

### Advisor : Jieh-Tsorng Wu

### Department of Electronics Engineering

### and Institute of Electronics

### National Chiao-Tung University

### Abstract

High-speed high-resolution Nyquist-rate analog-to-digital converters (ADCs) have been predominantly realized using the pipeline architecture. High-gain opamps with lin-ear feedback are often used to ensure the linlin-earity of sample-and-hold amplifiers (SHAs) and pipeline stages. To achieve more than 14-bit resolution, the opamps are required to have a voltage gain of more than 90 dB, which results in reduced speed.

Time-interleaving slow high-resolution pipelined A/D channels is therefore used to increase the effective sampling speed. However, gain, offset and sampling phase mismatch errors among the A/D channels degrade the overall A/D linearity. Thus, calibration is necessary for reducing the mismatch errors to maintain the A/D conversion linearity.

This thesis presents a time-interleaved pipelined ADC design. Methodologies for re-ducing the mismatch errors and improving the A/D linearity of a single channel are in-vestigated and discussed. The proposed buffered-precharged SHA used to reduce the sampling time skew errors among A/D channels is also discussed.

91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. The ADC uses a single bu
ffered-precharged sample-and-hold amplifier to avoid sampling phase error. Digital background
calibration is employed to maintain the conversion linearity of each A/D channel and also
correct both gain and offset mismatches between the two channels. Excluding I/O buffers,
*the chip occupies an area of 4.3 × 4.3 mm*2and dissipates 909 mW from a 1.8 V supply.

## Acknowledgements

First of all, I would like to express my appreciation to Prof. Jieh-Tsorng Wu for his support and patient guidance in my research. I was truely very fortunate to have the opportunity to work under him as a student. Whenever I encounter the difficulties or problems, he is always patient to give me the direction and encouragement.

I would also like to express my appreciation to the other students in Prof. Jieh-Tsorng Wu’s group, to the students in Prof. Jing-Yang Jou’s group, and to the other members in ED307 lab at NCTU. They provided a comfortable environment to work in, and peopele were very accepting. Without their help, my Ph. D work never be done well.

I especially appreciate Mr. Hung-Chih Liu for his guidence during my time here at National Chaio-Tong University. I worked with him on his pipelined ADC and through working with him learned a great deal about circuit design.

I would like express my greatest appreciation to Mr. Cheng-Yeh Wang, for his patient encouragement. In addition to being a valuable resource, he provided a great deal support to me through all the phases of my research work. He also took care of me when I was sick and damp.

Finally, I would like to express my appreciation to my mother, and other members of my family for their unconditional support and encouragement.

### Z

WEI### -M

EI### L

EE## Contents

Z` i

English Abstract iii

Acknowledgements v

List of Tables xi

List of Figures xiii

1 Introduction 1

1.1 Motivation . . . 1

1.2 Organization of Thesis . . . 3

2 Pipelined ADCs 5 2.1 Introduction . . . 5

2.2 Nonidealities in Pipelined ADCs . . . 9

2.2.1 Offset Errors . . . 10

2.2.2 Sub-DAC and Interstage Gain Error . . . 14

2.3 Switched-Capacitor Implementations . . . 16

2.4 Summary . . . 25

3 Techniques for Linearity Enhancement 27 3.1 Introduction . . . 27

3.2 Capacitor Error Averaging . . . 28

3.5 Proposed Background Digital Calibration . . . 38

3.6 Summary . . . 44

4 Time-Interleaved ADCs 47 4.1 Introduction . . . 47

4.2 Overview of Time-Interleaved ADCs . . . 48

4.3 Nonidealities in Time-Interleaved ADCs . . . 50

4.3.1 Timing Mismatch . . . 50

4.3.2 Gain Mismatch . . . 54

4.3.3 Offset Mismatch . . . 57

4.4 Summary . . . 60

5 Techniques for Reducing TI Mismatch Errors 61 5.1 Introduction . . . 61

5.2 Foreground Calibration . . . 61

5.3 Equalization-Based Calibration . . . 63

5.4 Randomly Time-Interleaving Method . . . 68

5.5 Proposed Mismatch Correction Technique . . . 72

5.6 Summary . . . 77

6 Sample-and-Hold Amplifiers for TI-ADCs 79 6.1 Introduction . . . 79

6.2 Flip-Around SHA . . . 80

6.3 Charge-Transfered SHA . . . 82

6.4 Charge-Redistribution SHA . . . 85

6.5 Precharged SHA (PC-SHA) . . . 87

6.6 Proposed Buffered-Precharged SHA (BP-SHA) . . . 90

6.7 The PC-SHA and BP-SHA in a TI-ADC . . . 93

6.8 Summary . . . 99

7 A 15-bit 125 MS/s Time-Interleaved Pipelined ADC 101

7.1 Introduction . . . 101

7.2 ADC’s Architecture . . . 101

7.3 Front-end SHA . . . 102

7.4 Pipelined A/D Channel . . . 106

7.5 Digital Circuits . . . 109

7.6 Experimental Results . . . 113

7.7 Summary . . . 119

8 Conclusions and Future Works 125 8.1 Conclusions . . . 125

8.2 Future Works . . . 126

Bibliography 127

Vita 135

## List of Tables

2.1 *Parameters of a Bj*-bit pipeline stage. . . 8

2.2 Parameters of a 2-bit pipeline stage. . . 9

2.3 Parameters of a 2-bit pipeline stage with reduced gain. . . 12

2.4 Parameters of an alternative of 2-bit pipeline stage with reduced gain. . . 13

2.5 *Parameters of a Bj*-bit SC stage. . . 16

2.6 Parameters of a 3-bit SC stage. . . 18

3.1 Summary of methods for linearity enhancement . . . 44

5.1 Simulated Parameters . . . 69

6.1 Summary of SHAs . . . 99

7.1 Device Sizes of Buffer . . . 104

7.2 Device Sizes of Opamp . . . 108

7.3 Device Sizes of Comparator . . . 110

7.4 Performance Comparison . . . 120

7.5 Nyquist-rate ADC Survey . . . 121

7.6 Qualitative Comparison for An Opamp Implemented Using Bipolar, CMOS and BiCMOS Technologies . . . 122

## List of Figures

1.1 CMOS Nyquist ADC survey. . . 2

2.1 A pipelined ADC. . . 5

2.2 A pipeline stage. . . 6

2.3 Transfer characteristics of a stage. . . 7

2.4 Ideal transfer curve of a 2-bit stage. . . 8

2.5 Transfer curve of a 2-bit stage with sub-ADC offsets. . . 9

2.6 Transfer curve of a 2-bit stage with offsets in the subtractor and gain am-plifier. . . 10

2.7 *Transfer curve of a 2-bit j-th stage with the extended range of the (j*+1)-th
stage. . . 11

2.8 Transfer curve of a 2-bit stage with interstage gain=2. . . 12

2.9 Transfer curve of a 1.5-bit stage with interstage gain=2. . . 13

2.10 Transfer curve of a 2-bit stage with sub-DAC reference errors. . . 14

2.11 Transfer curve of a 2-bit stage with residue gain errors. . . 15

*2.12 A Bj*-bit SC pipeline stage with the reduced interstage gain. . . 17

*2.13 Two phase operations of a Bj*-bit SC stage. . . 19

2.14 Two phase operations of MDAC. . . 22

2.15 Relevant block diagram and circuit for feedback factor calculation. . . 23

3.1 A radix-2 1.5-b SC stage with PCEA [1]. . . 29

3.2 Operations of a radix-2 1.5-b SC stage with PCEA [1]. . . 30

3.3 Block diagram of foreground digital self-calibration. . . 31

3.4 Transfer curve of (j+z)-ADC. . . 32 xiii

3.7 Block diagram of calibration employing CB method. . . 37

3.8 Model for the stage under calibration using CB method. . . 37

3.9 *A Bj*-bit split-capacitor SC pipeline stage. . . 40

3.10 Correlation-based parameter extraction. . . 41

*3.11 (j+ z)-ADC output encoding. . . 42*

3.12 ADC’s output encoding. . . 43

4.1 A conventional time-interleaved ADC. . . 48

4.2 The behavioral model of S/H in a TI-ADC. . . 49

4.3 Conceptual spectra of a 4-channel TI-ADC. . . 51

4.4 Illustration of timing skew effect on the sampled signal. . . 52

4.5 Conceptual spectra of a 4-channel TI-ADC with sampling skew mismatch. 53 4.6 Model of A/D channel’s gain factor in a TI-ADC. . . 55

4.7 Illustration of gain error effect on the sampled data. . . 55

4.8 Conceptual spectra of a 4-channel TI-ADC with gain effect. . . 56

4.9 Model of offset in a TI-ADC. . . 58

4.10 Illustration of offset error effect on the sampled data. . . 58

4.11 Conceptual spectra of a 4-channel TI-ADC with offset. . . 59

5.1 Block diagram of a TI-ADC with foreground calibration. . . 62

5.2 Block diagram of a TI-ADC with equalization-based calibration. . . 64

5.3 Block diagram of the adaptive signal processing. . . 65

5.4 Block diagram of a 4-channel TI-ADC with equalization-based calibration. 66
5.5 *Simulated power spectrum at fin* *= 18.17 MHz and fs* = 100 MHz. . . . 67

5.6 Output SNDR versus calibration cycles. . . 67

5.7 A randomly time-interleaved ADC. . . 69

5.8 The model of single channel in a randomly TI-ADC. . . 69

5.9 A (4+ 1)-channel randomly TI-ADC. . . 70

5.10 A diagram of randomly controlling signals in a (4+1) TI-ADC. . . 71

5.11 Principles of randomization. . . 71

5.12 Simulated SNDR and SFDR versus input frequency of a (4+ 1) TI-ADC. 72

5.13 A TI-ADC with the proposed mismatch correction. . . 73

5.14 A mismatch correction processor. . . 74

*5.15 Vm* *to Dr*1transfer functions. . . 76

5.16 Offset extraction signal-flow diagram. . . 76

6.1 A fully-differential FA-SHA and its timing phase. . . 80

6.2 Single-ended operating model of an FA-SHA. . . 81

6.3 A CT-SHA with its timing diagram. . . 83

6.4 Single-ended operating model of a CT-SHA. . . 83

6.5 A CR-SHA with its timing diagram. . . 85

6.6 Single-ended operating model of a CR-SHA. . . 85

6.7 A precharged SHA. . . 87

6.8 Model of the precharged SHA’s operation. . . 88

6.9 A BP-SHA. . . 91

6.10 Single-ended configuration of the BP-SHA’s operations. . . 91

6.11 The PC-SHA with the input networks of a TI-ADC. . . 94

6.12 PC-SHA’s operation in a 2-channel TI-ADC. . . 95

6.13 The BP-SHA with CHP1 and CHP2 choppers. . . 96

6.14 BP-SHA’s operation in a 2-channel TI-ADC. . . 97

6.15 Simulation results for the PC-SHA and BP-SHA at various mismatches. . 98

7.1 Time-interleaved pipeline ADC with single SHA. . . 102

7.2 BP-SHA with CHP1 and CHP2 choppers. . . 103

7.3 Bootstrapped switch [2]. . . 104

7.4 Unity-gain buffer for BP-SHA. . . 105

7.5 Block diagram of the single A/D channel. . . 105

7.6 1.5-bit fully differential MDAC for calibration. . . 106

7.7 Conventional 1.5-bit fully differential MDAC. . . 107

7.8 A two-stage fully differential opamp with Ahuja style compensation. . . . 108

7.9 Comparator schematic. . . 109

7.10 Digital output encoding and correction. . . 111

7.13 ADC’s microphotograph. . . 113

7.14 Block diagram of instrumentation setup. . . 114

7.15 Evaluated PCB photo. . . 115

7.16 Measured DNL and INL of the TI-ADC before calibration. . . 115

7.17 Measured DNL and INL of the TI-ADC after calibration. . . 116

*7.18 Measured FFT spectrum (fs*@125MS/s). . . 116

*7.19 Measured SNDR and SFDR versus fin*at normal calibration. . . 117

7.20 Measured SNR and SFDR versus input levels. . . 118

7.21 Measured SNR versus input frequencies. . . 118

7.22 High-resolution (≥ 12 bits) high-speed (≥ 50 MS/s) pipeline and time-interleaved ADCs. . . 122

7.23 Figure of merit. . . 123

## Chapter 1

## Introduction

### 1.1

### Motivation

Nyquist-rate analog-to-digital converters (ADCs) of more than 12-bit resolution have been predominantly realized using the pipelined analog-to-digital conversion (A/D) ar-chitecture as shown in Fig. 1.1, which is a survey of CMOS Nyquist-rate ADCs published from 1997 to 2006. As a pipelined ADC is required high sample rate, time-interleaving technique is applied. Therefore, this work addresses on the design of time-interleaved pipelined ADCs.

In switched-capacitor pipelined ADCs, the linearities of sample-and-hold amplifiers and pipeline stages are ensured by using high-gain opamps with capacitor feedback. Pipelined ADCs of more than 14-bit resolution can be achieved by incorporating digi-tal calibration (either foreground or background) to mitigate the requirements for device matching and opamps’ dc gain [3] [4] [5]. The maximum sampling rate of a pipelined ADC is mainly determined by the achievable operating speed of its internal high-gain opamps.

The time-interleaved (TI) architecture which contains more than one A/D channels to share the conversion operations can overcome the speed limitation imposed by their inter-nal circuit blocks [6]. However, the overall accuracy of a TI-ADC can be degraded by the gain, offset, and sampling phase mismatches among its A/D channels. Many calibration techniques have been developed to correct the A/D errors caused by these mismatches.

Figure 1.1: CMOS Nyquist ADC survey.

To take advantage of low-cost digital circuits in scaled CMOS technologies, there are cal-ibration schemes that execute the calcal-ibration procedures continuously in the background, while requiring no external reference signals or extra A/D channels [7] [8]. These schemes are able to extract mismatch information directly from the ADC’s digital outputs. These techniques usually involve complicated signal processing in the digital domain. They also impose certain requirements on the ADC’s input signal, e.g., it must be bandlimited and asynchronous with the ADC’s sampling clock.

In this work, we designed a 15-bit 125-MS/s CMOS TI-ADC which consists of two pipelined A/D channels. This ADC incorporates a single sample-and-hold amplifier (SHA) to avoid sampling phase mismatch. The SHA uses a precharged circuit configuration to mitigate the performance requirements for its opamp which has to operate at a maximum clock rate of 125 MHz. Digital background calibration is employed to maintain the con-version linearity of each A/D channel and also correct both gain and offset mismatches between the two channels. The calibration is proceeded continuously in the background

1.2. ORGANIZATION OF THESIS 3

without interrupting the normal A/D operations. The calibration schemes incorporated
in this ADC are robust since they do not rely on input signal condition. The ADC chip
*was fabricated in a 0.18 µm 1P6M CMOS technology with MIM capacitors, and operates*
under a single 1.8 V supply.

### 1.2

### Organization of Thesis

This thesis is organized into eight chapters. Chapter 1 gives the introduction of the thesis from high resolution, high speed ADCs. Chapter 2 examines the switch-capacitor based pipelined ADC with its error sources, and the linearity enhancement techniques are pre-sented in chapter 3. Chapter 4 overviews the time-interleaved ADC, and the degradation of linearity caused by mismatches among A/D channels. Then, the mismatch error cor-rection methods are briefly reviewed in chapter 5. Chapter 6 discusses the topology of the sample-and-hold amplifiers with their essential parameters. Factors limiting the resolution and sampling rate of sample-and-hold amplifier are analyzed and summarized. In chapter 7, the prototyping ADC’s implementation is described, including the opamp, compara-tor, and digital function blocks for calibration, as well as the experimental measurements. Finally, conclusions and future works are drawn in chapter 8.

## Chapter 2

## Pipelined Analog-to-Digital Converters

### 2.1

### Introduction

Pipelined A/D architecture is widely used for implementing high performance ADCs due to its high throughput rate. In addition, it exhibits linear growth in hardware as resolu-tion increases. However, it can achieves only 8-10 bits of linearity in most IC processing technologies without the use of component trimming or calibration. In this chapter, an overview of pipeline ADCs is presented, and nonidealities in pipeline ADCs are exam-ined. Moreover, switched-capacitor (SC) implementations are discussed.

*Fig. 2.1 shows the block diagram of a pipelined ADC [9]. It consists of P identical*
pipeline stages. A pipeline stage comprises a sub-ADC, a sub-DAC, a subtractor, and a
*gain amplifier. Its block diagram is shown in Fig. 2.2. The input signal Vjto the j-th stage*

**V1**

**V2**

**V3**

**VP+1**

**D1**

**D2**

**DP**

**Do**

**VP**

**1**

**Stage**

**2**

**Stage**

**P**

**Stage**

**Digital Signal Processing**

Figure 2.1: A pipelined ADC.

**Vj**

**Bj**

**Dj**

**Dj**

**Vj**

**Dj**

**Vj**

**Vj+1**

**Gj**

**da**

**(**

**)**

**(**

**)**

**res**

**sub−**

**DAC**

**sub−**

**ADC**

Figure 2.2: A pipeline stage.

*is quantized by the sub-ADC to produce Bjbits digital code, Dj*. The sub-ADC typically
consists of a bank of 2*Bj* _{−}_{1 comparators, j ∈ {1, 2, · · · , P }. Then, the digital code, D}

*j*,
*drives the Bj-bit sub-DAC to produce Vj*da*(Dj*), which is a quantized analog estimate of
*the Vjinput signal. This sub-DAC output, Vj*da*(Dj*), is then subtracted from the stage input
*to give an analog residue, V _{j}*res

*(Dj). Finally, Vj*res

*(Dj) is amplified by an amount of Gj*and

*transferred to the next stage. In typically, Bj*

*is ranged from 2 to 5 bits, and Gj*usually equals to 2

*Bj*

_{.}

*The static transfer characteristics of a Bj-bit pipeline stage is shown in Fig. 2.3. Its Vj*
*input has a full-scale range from −Vr*to*+Vr*. That means the minimum range of resolution
*corresponding to the Bj* bits digital code equals to [(*+Vr) − (−Vr)]/2Bj, denoted as rj*.
*The plot of V _{j}*da

*versus Vjexhibits a staircase. Note that the threshold levels in the Vj*-axis

*ideally are uniformly spaced. The V*da

_{j}*represents the approximation of Vj*corresponding

*to Dj*. Thus, the di

*fference of Vjand Vj*da can be plotted as the middle curve of Fig. 2.3,

*named V*res

_{j}*versus Vj*. This di

*fference is gained up by Gj*, and then the stage analog

*output, Vj*+1

*, is obtained. The curve of Vj*+1

*versus Vj*is shown in the most underlying

*frame, where the slope of each sawtooth-like shape equals to Gj*= 2

*Bj*.

*The mathematical description for the ideal relationship of the stage input, Vj*, and the
*amplified residue, Vj*+1, is given by

*Vj*+1 *= Gj*×*Vj− Vj*da*(Dj*)

(2.1) where the parameters of a pipeline stage referred to (2.1) are listed in Table 2.1.

2.1. INTRODUCTION 7
**Vj**
**+Vr**
**−Vr**
**−Vr**
**−Vr**
**+Vr**
**+Vr**
**+Vr**
**−Vr**
**+Vr j−r**
**+Vr−3rj**
**j**
**+3r**
**−Vr**
**j**
**+r**
**−Vr**
**j**
**r**
**j**
**−Vr +2r** **+Vr−2rj**
**+Vr**
**−Vr**
**Vjda**
**Vj**
**−Vr** **+Vr**
**Vjres**
**+0.5rj**
**−0.5rj**
**0**
**Vj**
**−Vr** **+Vr**
**−Vr**
**Vj+1**
**0**
**+Vr**
**j**
**+1.5rj**
**+3.5rj**
**j**
**−1.5rj**
**−0.5rj**
**−2.5r**
**+2.5r**
**j**
**+0.5r**

*Table 2.1: Parameters of a Bj*-bit pipeline stage.
*Range of Vj* *{−Vr,+Vr*}
Thresholds of sub-ADC ±(V*r− rj), ±(Vr*−*2rj), · · · , ±2rj, ±rj*
*Digital codes (Dj*) *0, 1, 2, · · · , 2Bj* −1
*Reference levels (V _{j}*da) ±(V

*r*−

*0.5rj), ±(Vr*−

*1.5rj), · · · , ±1.5rj, ±0.5rj*

**Vj**

**−Vr**

**−0.5Vr**

**+Vr**

**−Vr**

**+Vr**

**Vj+1**

**+0.5Vr**

**−0.75Vr**

**0**

**0**

**00**

**01**

**10**

**11**

**−0.25Vr**

**+0.25Vr**

**+0.75Vr**

Figure 2.4: Ideal transfer curve of a 2-bit stage.
Furthermore, the overall ADC’s input can be iteratively derived according to (2.1)
*from the 1-st stage to the last P -th stage. It is obtained by:*

*V*_{1}*= V*_{1}da*(D*1)+
*V*_{2}da*(D*2)
*G*1
+ *V*
da
3 *(D*3)
*G*1*G*2
+ · · · + *V*
da
*P* *(DP*)
*G*1*G*2*· · · GP −*1
+ *VP*+1
*G*1*G*2*· · · GP*
(2.2)

*where the last term, VP*+1*/G*1*G*2*· · · GP*, is the typical quantization error.

So far, it has been assumed that each stage has ideal transfer characteristics as well as the whole pipelined ADC. However, there will be errors incurred due to the imperfections of circuit implementations.

2.2. NONIDEALITIES IN PIPELINED ADCS 9

Table 2.2: Parameters of a 2-bit pipeline stage.
*Range of Vj* *{−Vr,+Vr*}

Thresholds of sub-ADC −0.5V*r,0,+0.5Vr*
*Four digital codes (Dj*) *0, 1, 2, 3*

*Four reference levels (V _{j}*da) −0.75V

*r, −0.25Vr,+0.25Vr,+0.75Vr*

**Vj**

**−Vr**

**−0.5Vr**

**+Vr**

**−Vr**

**+Vr**

**Vj+1**

**Vth3 V**

_{th3}

_{th3}

**Vth1**

**Vth2**

**0**

**0**

**Ideal**

**00**

**01**

**10**

**11**

**Actual**

Figure 2.5: Transfer curve of a 2-bit stage with sub-ADC offsets.

### 2.2

### Nonidealities in Pipelined ADCs

In this section, the linear errors of a pipelined ADC are discussed by illustrating with a
*2-bit pipeline stage, i.e. Bj* = 2. Its ideal transfer curve is shown in Fig. 2.4 and the
*corresponding parameters are shown in Table 2.2, where rj* *= 0.5Vr*. Here, three major
error sources are examined. They are offset errors, sub-DAC reference errors and
inter-stage gain errors. As shown in Fig. 2.2, the sub-ADC, the subtractor and gain amplifier
can result in offset errors in a pipelined ADC.

**+Vr**
**Vj+1**
**Vj**
**−Vr** **−0.5Vr** **+Vr**
**−Vr**
**+0.5Vr**
**−0.75Vr**
**0**
**00** **01** **10** **11**
**Ideal**
**Actual**
**0**
**−0.25Vr** **+0.25Vr** **+0.75Vr**
**Missing Codes**

Figure 2.6: Transfer curve of a 2-bit stage with offsets in the subtractor and gain amplifier.

### 2.2.1

### O

**ffset Errors**

The behavior of the 2-bit stage with an offset in one of the thresholds is illustrated in
Fig. 2.5. Assume that only the nonideal threshold levels are discussed in this subsection
unless extra being stated. If there has an offset in the threshold level, the actual transfer
*curve is shown as the dash line in Fig. 2.5. The threshold level of Vth*3 is broken by an

o*ffset and becomes as ˆVth*3*. Due to the changed level, the stage output, Vj*+1, is more
*negative than −Vr*, and thus out of the input range of the next stage. Furthermore, errors
in the overall A/D transfer characteristics will be incurred, especially in missing digital
*codes. This means that if Vj*+1 *is less than −Vr, Dj* becomes too large, i.e. 10 → 11, and
*should be made more negative. On the other hand, if Vj*+1 is greater than*+Vr, Dj* is too
small, and should be made more positive.

The transfer characteristics due to the offsets in the subtractor and the gain amplifier are shown in Fig. 2.6. These offsets result in a repeated pattern, whereas those of sub-ADC cause errors only in the neighborhood of the thresholds. The transfer relations of the stage can be expressed in mathematical description as:

*Vj*+1 *= Gj*×*Vj− Vj*da*(Dj) − Vj*os

(2.3)

2.2. NONIDEALITIES IN PIPELINED ADCS 11
**Vth3**
**−Vr**
**+Vr**
**Vj+1**
**−Vr** **−0.5Vr** **+Vr**
**Vth3**
**Vj**
**−0.5Vr**
**+Vr**
**−Vr**
**0**
**+0.5Vr**
**−1.5Vr**
**−2Vr**
**+1.5Vr**
**+2Vr**
**Extended Range**
**of the (j+1)−th Stage**
**100**
**101**
**00**
**−10**
**01**
**10**
**11**
**−01**
**Vth1** **Vth2**
**0**
**Ideal**
**00** **01** **10** **11**
**0**
**Actual**

*Figure 2.7: Transfer curve of a 2-bit j-th stage with the extended range of the (j*+ 1)-th
stage.

means that a repeated pattern of missing codes appears at the whole A/D digital output.
Two techniques are used to alleviate the offset effects resulted from the sub-ADC, the
*subtractor, and the gain amplifier. One is to expand the range to be more than ±Vr* of the
following stage to allow the amplified residue output with some amount of being more
*than ±Vr*. The other is to reduce the interstage gain, and thus to use the less range than
*±Vr* to guarantee that the offsets do not result in overrange. Both the two schemes here
are discussed.

*Consider an example of 2-bit j-th stage following by the (j* + 1)-th stage with the
*extended range shown in Fig. 2.7. The threshold levels of the (j*+ 1)-th stage and its
corresponding codes are shown on the right-side of the figure. The extended range is 2
times of the normal range. If there have threshold o*ffsets in the j-th stage, the Vj*+1 will
*not be overrange while the (j+ 1)-th stage accommodates it to vary from −2Vr* to*+2Vr*.

Reducing gain scheme with shifting the sub-ADC thresholds and the sub-DAC levels
*is also helpful for avoiding the overrange of Vj*+1. In a 2-bit case shown in Fig. 2.8, its dc
parameters are listed in Table 2.3. Due to the reduced interstage gain, the redundancy is
introduced to alleviate the offset requirement. Then, this redundancy is removed after the
output digital coding. After digital correction [9] [10], the final effective number of bits
equals to 1 bit.

**Vj**
**−Vr** **−0.5Vr** **+Vr**
**−Vr**
**+Vr**
**Vj+1**
**+0.5Vr**
**−0.75Vr**
**−0.5Vr**
**+0.5Vr**
**0**
**0**
**−0.25Vr** **+0.25Vr** **+0.75Vr**
**01** **10**
**00** **11**

Figure 2.8: Transfer curve of a 2-bit stage with interstage gain=2.

Table 2.3: Parameters of a 2-bit pipeline stage with reduced gain.
*Range of Vj* *{−Vr,+Vr*}

Thresholds of sub-ADC −0.25V*r,+0.25Vr,+0.75Vr*
*Four digital codes (Dj*) *0, 1, 2, 3*

2.2. NONIDEALITIES IN PIPELINED ADCS 13
**Vj**
**−Vr** **−0.5Vr** **+Vr**
**−Vr**
**+Vr**
**Vj+1**
**+0.5Vr**
**−0.75Vr**
**−0.5Vr**
**+0.5Vr**
**0**
**0**
**−0.25Vr** **+0.25Vr** **+0.75Vr**
**01** **10**
**00**

Figure 2.9: Transfer curve of a 1.5-bit stage with interstage gain=2.

Table 2.4: Parameters of an alternative of 2-bit pipeline stage with reduced gain.
*Range of Vj* *{−Vr,+Vr*}

Thresholds of sub-ADC −0.25V*r,+0.25Vr*
*Four digital codes (Dj*) *0, 1, 2*

*Four reference levels (V _{j}*da) −0.5V

*r,0,+0.5Vr*

At this point, in a pipelined ADC, reduced interstage gain permits large allowable
offsets and thus leads to a robust implementation. The maximum allowable offsets are
*defined by the requirement that Vj*+1 *must be within the range of the following (j* +
1)-th stage. Therefore, 1)-the accuracy of 1)-the 1)-thresholds is independent of 1)-the overall A/D
accuracy.

An alternative with 1 effective bit which is most widely used in pipelined ADC’s implementations [2] [11] [3] [12] is 1.5 bits per stage. Its corresponding transfer charac-teristics are shown in Fig. 2.9, and its dc parameters are presented in Table 2.4. While the characteristics of this alternative is widely employed and is easily extend to implement multibit per stage, it is furthermore discussed in the following sections. In particular, it is used to investigated the switched-capacitor implementation of a pipelined ADC.

**Vj**
**−Vr** **−0.5Vr** **+Vr**
**−Vr**
**+Vr**
**+0.5Vr**
**−0.75Vr**
**00** **01** **10** **11**
**Vj+1** **G xj** ∆**Vj Dj( )**
**da**
**0**
**0**
**−0.25Vr** **+0.25Vr** **+0.75Vr**
**Ideal**
**Actual**

Figure 2.10: Transfer curve of a 2-bit stage with sub-DAC reference errors.

### 2.2.2

### Sub-DAC and Interstage Gain Error

The effect on transfer characteristics of an individual stage due to errors in a sub-DAC
reference level is examined here. Its corresponding transfer curve is depicted in Fig. 2.10.
*It can be observed that an error ∆Vj*da*(Dj*) in the sub-DAC reference level will result in
*an error in the final amplified residue output with a value of Gj× ∆Vj*da*(Dj*). Due to this
sub-DAC error, the stage transfer function is rewritten as:

*Vj*+1 *= Gj*×*Vj*− ˆ*Vj*da*(Dj*)

(2.4)
where ˆ*V _{j}*da

*(Dj*)

*= Vj*da

*(Dj) − ∆Vj*da

*(Dj*). In order to maintain the overall ADC’s accuracy,

*this error amount is required to be less than x LSB of the remaining stages and this is*expressed as

*Gj× ∆Vj*da

*< x ·*

*2Vr*2 P

*P*

*p=j+1Bp*(2.5)

which yields the relative sub-DAC accuracy as

*∆V _{j}*da

*(Dj*)

*2Vr*

*<*

*x*2 P

*P*

*p=j+1Bp*· 1

*Gj*=

*x*2 P

*P*

*p=jBp*(2.6)

*Typically, x is chosen as 1/2, and Gj* = 2*Bj*.

It is obvious that any errors in the sub-DAC will directly degrade the accuracy of the
*stage input since V _{j}*da is subtracted directly from the input. It is also clear to be examined

2.2. NONIDEALITIES IN PIPELINED ADCS 15

**Vj**

**−Vr**

**−0.5Vr**

**+Vr**

**−Vr**

**+Vr**

**Vj+1**

**+0.5Vr**

**−0.75Vr**

**0**

**0**

**00**

**01**

**10**

**11**

**−0.25Vr**

**+0.25Vr**

**+0.75Vr**

**Ideal**

**Actual**

Figure 2.11: Transfer curve of a 2-bit stage with residue gain errors.

from (2.2) that the kind of errors directly degrades the overall A/D accuracy of the whole
*ADC. Therefore, the sub-DAC relative accuracy, ∆V _{j}*da

*(Dj)/2Vr*should be considered to

*be consistent with the corresponding resolution of the pipeline stages from the j-th to the*last one.

The effects of nonideal interstage gain are now examined, as depicted in Fig. 2.11.
*For a 2-bit stage using simple coding with no redundancy, its nominal gain is Gj* = 4.
*However, if there appears gain error, denoted by εG*, the actual gain becomes as ˆ*Gj* =

*Gj(1 − εG*). Hence, the actual transfer curve shown as the dash line in Fig. 2.11 indicates
*to have the slope of 4(1 − εG*). This causes that the maximum residue output is reduced
*from Vr* *to Vr(1 − εG*), and the stage’s analog I/O transfer function is given by

*Vj*+1 *= ˆGj*×*Vj− Vj*da*(Dj*)

*= Gj(1 − εG*) ×*Vj− Vj*da*(Dj*)

(2.7)

*The error, Gj× εG*×*[Vj− Vj*da*(Dj*)], of the residue output due to the interstage gain error
will be passed down the pipeline. In order to maintain the ADC’s resolution, this error
*is therefore limited to be less than x LSB of the resolution in the remaining stages. This*

*Table 2.5: Parameters of a Bj*-bit SC stage.
*Range of Vj* *{−Vr,+Vr*}
(2*Bj* _{−}_{2) thresholds of sub-ADC} _{±(N}
*s*−*0.5)rj, ±(Ns*−*1.5)rj, · · · , ±0.5rj*
(2*Bj* _{−}_{1) digital codes (D}*j*) *0, ±1, ±2, · · · , ±(Ns*−*1), ±(Ns*)
(2*Bj* _{−}* _{1) reference levels (V}*da

*j*)

*±Nsrj, ±(Ns*−

*1)rj, · · · , ±rj,*0

*Ns* *intermediate codes Dj,y* −1, 0,+1
implies that
*Gj× εG*×*[Vj− Vj*da*(Dj)] < x ·*
*2Vr*
2
P*P*
*p=j+1Bp*
⇒ *εG* *<*
*x*
2
P*P*
*p=jBp*
×
*2Vr*
*Vj− Vj*da*(Dj*)
⇒ *εG* *<*
*x*
2
P*P*
*p=jBp*
−1
(2.8)

*Equation 2.8 holds if max{Vj− Vj*da*(Dj*)} *= Vr. To avoid missing codes, x corresponds*
*to 1 and thus εG* *<*
*1/2*
P*P*
*p=jBp*
−1
.

In the practical design, the error contributions of settling time errors and matching
*errors in the gain amplifier are also considered. Therefore, x in (2.8) is typically required*
*to be less than 1/4.*

### 2.3

### Switched-Capacitor Implementations

*A general Bj-bit SC stage in the single-ended configuration with reduced Gj* to alleviate
offset effects is illustrated here to examine its operating principles and nonidealities.

*A general switched-capacitor (SC) configuration for a Bj*-bit stage with the reduced

*Gj* is shown in Fig. 2.12. Since it is to emphasize the essence of what is happening with
respect to the pipelined A/D conversion function, the peripheral details such as output
*reset are therefore omitted. The sub-ADC consists of a bank of 2Ns* comparators. The

2.3. SWITCHED-CAPACITOR IMPLEMENTATIONS 17
**Cf**
**Vj+1**
φ**2**
φ**1**
φ**1**
φ**2**
φ**1**
**Cs,Ns**
**x Vr**
**Dj,Ns**
φ**2**
φ**1**
**Dj,2 x Vr**
**Cs,2**
φ**1** φ**2**
**Dj,1x Vr**
**Cs,1**
**j**
**B −bit MDAC**
**Dj,Ns**
**Dj,1** **Dj,2**
**Vj**
**j**
**B −bit sub−ADC**
**Dj**
**+1.5rj**
**−1.5rj**
**−0.5rj** **+0.5rj** **−(Ns−0.5)rj** **+(Ns−0.5)rj**
**Encoder**

Table 2.6: Parameters of a 3-bit SC stage.
*Range of Vj* *{−Vr,+Vr*}

6 thresholds of sub-ADC ±5V*r/8, ±3Vr/8, ±Vr/*8
*7 digital codes Dj* −3, −2, −1, 0,*+1, +2, +3*
*7 reference levels V _{j}*da ±6V

*r/8, ±4Vr/8, ±2Vr/8, 0*

multiplying digital-to-analog converter (MDAC) is used to implemented the sub-DAC, the
subtractor, and the gain amplifier shown in Fig. 2.2, and comprises a bank of
*switched-capacitors, and an opamp. Its corresponding parameters are listed in Table 2.5, where Ns*
is defined as the minimum number of required sampling capacitors while employing the
*reduced interstage gain technique with sharing the Cf* feedback capacitor, and its value
*related to Bj*is given by

*Ns* = 2*Bj*−1−1 (2.9)

*The intermediate code, Dj,y*, is produced by the two comparators which have thresholds
*with the same value but opposite sign, and its corresponding values are within {−1, 0,*+1}.
*The Djoutput code is obtained by adding the Dj,y*’s, and is expressed as

*Dj*=
*Ns*

X
*y*=1

*Dj,y* (2.10)

*For example, a 3-bit SC stage sharing the feedback capacitor has Ns* = 3 sampling
capac-itors and its has the dc parameters shown in Table 2.6.

The SC schematic shown in Fig. 2.12 has two operating phases which is shown in Fig. 2.13. It is assumed that the operational amplifier (opamp) is ideal as well as the switches and capacitors. The nonideal effects are considered later.

*During the sample phase (φ*1*= 1), as shown in Fig. 2.13(a), the Vj*input is acquired on
*sampling capacitors, Cs,y, for all y ∈ {1, 2, · · · , Ns*}, and the shared feedback capacitor,

*Cf*. The input is also acquired by the comparators in the sub-ADC for comparing to the
thresholds. At the end of the sampling phase which is defined as the sampling instant, the

2.3. SWITCHED-CAPACITOR IMPLEMENTATIONS 19
**Cf**
**Vj+1**
**j**
**B −bit sub−ADC**
**Cf**
**x Vr**
**Vj+1**
**j**
**B −bit sub−ADC**
**Cs,1** **Cs,2**
**Dj,1x Vr** **Dj,2 x Vr**
**j**
**B −bit MDAC**
**j**
**B −bit MDAC**
**Dj**
**j**
**−(N −0.5)r _{s}**

**+(N −0.5)r**

_{s}

_{j}**Vj**

**Dj,1**

**Dj,2**

**+1.5rj**

**−1.5rj**

**+0.5rj**

**−0.5rj**

**Dj**

**Dj,1**

**Dj,2**

**Dj,N**

_{s}**Vj**

**j**

**−(N −0.5)r**

_{s}**+(N −0.5)r**

_{s}

_{j}**+1.5rj**

**−1.5rj**

**+0.5rj**

**−0.5rj**

**Cs,Ns**

**X**

**Dj,N**

_{s}**Cs,N**

_{s}**X**

**Cs,1**

**Cs,2**

**Dj,N**

_{s}**Encoder**

**(a) Sample phase.**

**(b) Hold phase.**

**Encoder**

*sampling switches are opened, and the stored charge at the node X is given by*
*QX,s* = − *CfVj*+
*Ns*
X
*y*=1
*Cs,yVj*
!
(2.11)

*During the hold phase (φ*2 = 1), as shown in Fig. 2.13(b), the digital code produced

*by the sub-ADC determines which references are connected to the capacitors, Cs,y*, to
perform the sub-DAC function. At the same phase, the opamp goes into closed-loop
*con-figuration with the feedback capacitor, Cf, and the sampled charge, QX,s*, is redistributed
*over Cs,y* *and Cf, to generate the stage’s output, Vj*+1. Then, this output is acquired by the
*next pipeline stage. At the end of the hold phase, the charge at node X is given by*

*QX,h*= − *Cf* *× Vj*+1+
*Ns*
X
*y*=1
*Cs,y× Dj,yVr*
!
(2.12)

*According to the charge conservation theorem, QX,hequals to QX,s*. Therefore,
equat-ing (2.11) and (2.12) yields

− *CfVj*+
*Ns*
X
*y*=1
*Cs,yVj*
!
= − *Cf* *× Vj*+1+
*Ns*
X
*y*=1
*Cs,y× Dj,yVr*
!
(2.13)

*which can be solved to given Vj*+1,

*Vj*+1 = 1+
*Ns*
X
*y*=1
*Cs,y*
*Cf*
!
*× Vj*−
*Ns*
X
*y*=1
*Cs,y*
*Cf*
*× Dj,yVr* (2.14)
*Let the notation Ct*is denoted the total capacitance used for acquiring the input at phase
1, thus it is given by
*Ct* *= Cf* +
*Ns*
X
*y*=1
*Cs,y* (2.15)

Then, (2.14) can be rewritten as

*Vj*+1 =
*Ct*
*Cf*
*Vj*−
P*Ns*
*y*=1*Cs,y* *· Dj,y*
*Ct*
*× Vr*
!
(2.16)

Furthermore, we can compare (2.16) to (2.1) and obtain that

*Gj* =
*Ct*
*Cf*
= 1 +
P*Ns*
*y*=1*Cs,y*
*Cf*
(2.17)
*V _{j}*da

*(Dj*) = P

*Ns*

*y*=1

*Cs,y*

*· Dj,y*

*Ct*

*× Vr*(2.18)

2.3. SWITCHED-CAPACITOR IMPLEMENTATIONS 21

*From (2.2), it appears that Gjand Vj*da directly affect the accuracy of the whole pipelined
A/D conversion. Moreover, both (2.17) and (2.18) indicate that they are closely related
*to the ratio of the sampling capacitors, Cs,y, and the feedback capacitor, Cf*. This implies
that the capacitor ratio dominates the accuracy of the conversion in an SC pipelined ADC.
In the following, the major nonidealities presented in the SC implementation of a
pipelined ADC are discussed. Assume that the digital correction scheme has been
em-ployed in the pipelined ADC’s design. Therefore, the thresholds offsets of the sub-ADC
here are not further discussed. The investigation is focused on the imperfections of the
SC MDAC which is assumed to be implemented with sharing the feedback capacitor.

*Since the feedback capacitor, Cf*, is shared to be used for acquiring the input signal
during the sample phase, the closed-loop gain of the pipeline stage during the hold phase
is given by
*Gj* =
*Cs,*1*+ Cs,*2*+ · + Cs,Ns* *+ Cf*
*Cf*
= 1 +
*Ns*
X
*y*=1
*Cs,y*
*Cf*
(2.19)

*Assume that the Cs,y’s and Cf* capacitors are independent and identically distributed (i.i.d)
*random variables, the variance of Gj*therefore can be obtained by

*V ar(Gj*)*= V ar* 1+
*Ns*
X
*y*=1
*Cs,y*
*Cf*
!
= 0 +
*Ns*
X
*y*=1
*σ _{∆C}*2

*s,y/Cf*(2.20)

*where σ∆Cs,y/Cf* is the standard deviation of the capacitor relative mismatches, and they

have typical values from 0.1% to 0.025% for a 1 pF capacitor implemented in a CMOS technology using metal-insulator-metal (MIM) structure.

The operating configurations of MDAC in a pipeline stage here are duplicated in Fig. 2.14. Its operation is similar to that shown in Fig. 2.13, except including the effects of the opamp’s finite gain and offset.

*During the sample phase, the sampling switch, S0, is closed, and thus the inputs of*
*opamp are shorted. The charge at node X therefore is given by (2.11). The parasitic*
*capacitor, Cpi, of the opamp’s input stores no charge due to the shorted S0. During the*
*hold phase, the QX,sis redistributed. and the charge at node X becomes as*

*QX,h* =
"_{N}*s*
X
*y*=1
*Cs,y* *VX* *− Dj,y* *· Vr*
#
*+ CpiVX* *+ Cf(VX− Vj*+1) (2.21)

**Cs,1**
**Dj,1x Vr**
**Vj**
**Dj,2 x Vr**
**Cf**
**Vj+1**
**Cf**
**Vjos** **A0** **Vj+1**
**0**
**A**
**x Vr**
**Dj,Ns**
**Cs,2**
**Cs,2**
**S0**
**Cs,1**

**(a) Sample phase.**

**(b) Hold phase.**
**X**
**Cs,Ns**
**X**
**Cs,Ns**
**Cpi**
**Cpi**

Figure 2.14: Two phase operations of MDAC.

*Typically, the I/O relation of the opamp with the finite DC gain A*0 and o*ffset Vos*is given
by

*Vj*+1 *= A*0×*(0 − Vos− VX*) (2.22)
*thus, the voltage at node X is obtained by*

*VX* = −
* Vj*+1

*A*_{0} *+ Vos*

(2.23)

Again, according to the charge conservation theorem, equating the expressions (2.21) and
(2.11) yields
"_{N}*s*
X
*y*=1
*Cs,y* *VX* *− Dj,y· Vr*
#
*+ CpiVX+ Cf(VX− Vj*+1)= − *CfVj*+
*Ns*
X
*y*=1
*Cs,yVj*
!
(2.24)
which gives
*CfVj*+1 = *Cf*+
*Ns*
X
*y*=1
*Cs,y*
!
*Vj*−
*Ns*
X
*y*=1
*Cs,yDj,yVr*+ *Cpi+ Cf* +
*Ns*
X
*y*=1
*Cs,y*
!
*VX* (2.25)

2.3. SWITCHED-CAPACITOR IMPLEMENTATIONS 23
**A0**
β
**VX** **Vj+1**
**A0**
**Vj+1**
**Cf**
**Cs,Ns**
**s,2**
**C**
**Cs,1**

**(a) A simple feedback system.** **(b) Circuit for feedback factor calculation.**
**Cpi**

**X**

Figure 2.15: Relevant block diagram and circuit for feedback factor calculation.

*Then, replacing VX* with (2.23) yields

*CfVj*+1= *Cf* +
*Ns*
X
*y*=1
*Cs,y*
!
*Vj*−
*Ns*
X
*y*=1
*Cs,yDj,yVr*+ *Cpi+ Cf* +
*Ns*
X
*y*=1
*Cs,y*
!
−*Vj*+1
*A*_{0} *− Vos*
(2.26)
*and solving this for Vj*+1 obtains

*Vj*+1 =
1
1*+ εG*
×
"
1+
*Ns*
X
*y*=1
*Cs,y*
*Cf*
!
*Vj*−
*Ns*
X
*y*=1
*Cs,y*
*Cf*
*Dj,yVr*−*(A*0*× εG) Vos*
#
(2.27)
with
*εG* =
1
*A*0
·
* Cpi+ Cf* + P
*Ns*
*y*=1*Cs,y*
*Cf*
!
(2.28)

which is regarded as the gain error of the pipeline stage caused by the opamp’s finite dc gain.

*Since the MDAC output feeds back to node X during the hold phase configuration, its*
relevant block diagram is shown in Fig. 2.15(a) as well as the circuit shown in Fig. 2.15(b).
*The feedback amount is quantized by the feedback factor β and is given by*

*β* = *VX*
*Vj*+1
= *Cf*
*Cpi+ Cf*+ P
*Ns*
*y*=1*Cs,y*
(2.29)

*Note that the feedback factor is the ratio of the feedback capacitance Cf* to the total
*ca-pacitance at node X,*
*Cpi+ Cf* + P
*Ns*
*y*=1*Cs,y*

, during the hold phase. Replacing (2.29) into the expression of the gain error of (2.28) yields

*εG*=
1

*A*0*× β*

and also substituting this for the expression of (2.27) gives
*Vj*+1 =
1
1*+ εG*
×
"
1+
*Ns*
X
*y*=1
*Cs,y*
*Cf*
!
*Vj*−
*Ns*
X
*y*=1
*Cs,y*
*Cf*
*Dj,yVr*−
*Vos*
*β*
#
(2.31)

*Clearly, the gain accuracy of a stage is closely related to the dc loop gain A · β in its*
closed-loop configuration. Therefore, to maintain the gain accuracy, both the opamp’s
open-loop dc gain and the feedback factor are considered.

In addition to the finite dc gain, the opamp’s finite settling speed also causes error
*imposed on Vj*+1*. If only the settling error ετ* *is considered, the stage’s analog output Vj*+1
of (2.14) is modified as
*Vj*+1 *= (1 − ετ*) ×
"
1+
*Ns*
X
*y*=1
*Cs,y*
*Cf*
!
*× Vj*−
*Ns*
X
*y*=1
*Cs,y*
*Cf*
*× Dj,yVr*
#
(2.32)

*If only consider the exponential settling, the settling error ετ* at the end of the hold phase
is given by

*ετ* *= e−ω*−3dB*×Ton* (2.33)

*where Ton* *is the time for exponential settling, and ω*−3dB is the −3dB corner frequency

*of MDAC. Typically, Ton* is one third of the sampling clock period. The settling error is
time-dependent, and thus causes signal-dependent errors. The signal-dependent errors are
difficult to be cancelled or calibrated. Therefore, the opamp’s speed actually limits the
sampling speed of an SC pipelined ADC, and its settling behavior needs be particularly
considered.

Thermal noise is also particularly considered in the SC implementations of ADCs
required the resolutions higher than 10 bits. Two major error sources result in thermal
*noises. One is the kT/C noise caused by the sampling switches, and the other are resulted*
*from the opamp’s transistors. Here, only kT/C noise is discussed.*

The thermal noise from the sampling switch is stored on the sampling capacitors and results in a noise power of

*n*2* _{kT/C}* =

*kT*

*Cf*+ P

*Ns*

*y*=1*Cs,y*

(2.34)

*where k= 1.38×10*−23_{J/K is the Boltzmann’s constant, and T is the absolute temperature.}

2.4. SUMMARY 25

the signal-to-noise ratio (SNR) of an SC MDAC is given by

*SNRkT/C* =
*V _{F S}*2

*/*8

*n*2

*=*

_{kT/C}*V*2

_{F S}*Cf*+ P

*Ns*

*y*=1

*Cs,y*

*8kT*(2.35)

This indicates that the minimum size of the capacitors is determined by the total
*con-tribution of kT/C noise which does not degrade the SNR below that resulted from the*
quantization noise.

### 2.4

### Summary

In this chapter, the operating principles of a pipelined ADC is presented, as well as the corresponding mathematical derivation. The general error sources of a pipeline stage are also examined. Then, the most often used SC implementations and their nonidealities are investigated. Finally, the general mathematical description is given to indicate the limitations of SC pipelined ADC’s designs.

For a pipeline stage as shown in Fig. 2.2, the actual transfer function combining with
offsets of the subtractor and gain amplifier, sub-DAC errors, and interstage gain errors can
be written as
*Vj*+1 *= ˆGj*×*Vj*− ˆ*Vj*da*(Dj) − Vj*os
(2.36)
with
ˆ
*Gj* *= Gj*×*(1 − εG*) (2.37)
ˆ
*V _{j}*da

*(Dj*)

*= Vj*da

*(Dj) − ∆Vj*da

*(Dj*) (2.38) whereas the threshold level offsets of the sub-ADC are not included in this equation, since it is difficult to precisely described in mathematics.

*For an SC pipeline stage, assume the finite dc gain error εG* *and the settling error ετ*
are considered uncorrelated, as well as the opamp’s o*ffset Vos*. The effect of these errors
*can be superimposed on the stage’s analog output Vj*+1*, and the expression of Vj*+1is given
by
*Vj*+1 *= (1 − ετ*)
1
1*+ εG*
"
1+
*Ns*
X
*y*=1
*Cs,y*
*Cf*
!
*Vj*−
*Ns*
X
*y*=1
*Cs,y*
*Cf*
*Dj,yVr*−
*Vos*
*β*
#
(2.39)

which is a basis of designing an SC MDAC. Compare (2.39) to (2.36), and hence we have
ˆ
*Gj* *= (1 − ετ*)
1
1*+ εG*
× 1+
*Ns*
X
*y*=1
*Cs,y*
*Cf*
!
(2.40)
and
ˆ
*V _{j}*da

*(Dj*) =

*Ns*X

*y*=1

*Dj,y*·

*Cs,y*

*Cf*

*× Vr*(2.41)

## Chapter 3

## Techniques for Linearity Enhancement

### 3.1

### Introduction

Since ADC’s performance is degraded due to the imperfections of the circuit compo-nents, lots of techniques have been developed for compensating such degradations. In this chapter, the published methods for improving the linearity of SC pipelined ADCs are investigated and summarized, as well as the proposed technique. Three natures are dis-cussed. They are capacitor error averaging, foreground digital self-calibration, and digital background calibration.

As capacitor mismatch in a SC pipelined ADC is the most important error source of nonlinearity, capacitor error averaging (CEA) techniques have been developed for re-ducing this error effect. Active CEA (ACEA) can realize excellent linearity with poorly matched capacitors, but requires an extra opamp, capacitors and additional clock phases [13]. More power consumption and circuit complexity are hence added. Passive CEA (PCEA) was presented achieving good linearity without an extra opamp but still requires additional clock phases [1] [14]. Therefore, PCEA techniques conduct low power con-sumption, but sacrifice little speed due to adding additional clock phases. An alternative technique, DAC and feedback capacitor averaging (DFCA), was presented resulting in high SFDR by simultaneously shuffling the DAC and the feedback capacitors. The DFCA technique requires little analog circuits and no additional clock phases, but requires extra digital hardware [15] [16].

Foreground digital self-calibration techniques are presented to relieve the accuracy requirements of analog circuits by injecting a calibration signal. This kind of technique requires interrupting normal A/D conversion for measuring calibration parameters, and hence is so-called foreground or off-line calibration. DC signals, the white gaussian noise and ramp signals have been presented as the calibration signal to measure calibration parameters. DC signal is the most frequently used [17] [18], especially the threshold levels of a pipeline stage [19] [20] [21] [22] [23]. The reference levels of pipeline stages are also employed as the calibration signal sometimes [24]. White gaussian noise presented in [25] was indicated highly improving ADC’s linearity using Matlab simulation, but required an additional white gaussian noise generator. Literature [26] presented a on-chip ramp signal as a calibration signal. Therefore, the design of [26] required to implement a highly accurate ramp signal generator.

Background calibration is developed for considering the reliability for the long term of a pipelined ADC. It can be performed continuously without interrupting normal A/D conversion. Two digital background calibration methods are investigated. They are the equalization-based [27] [28] [29] and correlation-based background calibration [30] [5] [31].

### 3.2

### Capacitor Error Averaging

This section addresses the PCEA technique. Fig. 3.1 presents the schematic and the
corre-sponding timing diagram of a radix-2 1.5-b SC stage employing PCEA. Fig. 3.2 illustrates
the operations of the pipeline stage together with the next stage. Four operating phases
*are required for performing the PCEA. At sampling phase 1, φ*1 *= 1 and φ*11 = 1, the

*stage first input, Vj,*1*, is sampled by C*1*. At sampling phase 2, φ*1 *= 1 and φ*12 = 1, the

*second input, Vj,*2*, is sampled by C*2*. During hold phase 1, φ*21 *= 1, C*1 is connected in

*the feedback loop and the first residue output, Vj+1,1*, is generated and sampled by the
*following stage’s sampling capacitor, C*3*. During hold phase 2, φ*22 *= 1, C*1 *and C*2 are

3.2. CAPACITOR ERROR AVERAGING 29
**1**
**C2**
**C1**
**Vj+1**
φ**1**
φ**11**
φ**12**
φ**21**
φ**22**
**Clock**
**Dj xVr**
**Vj**
**11** **12**
**22**
**21**
**21**
**22**
**1** **1**

Figure 3.1: A radix-2 1.5-b SC stage with PCEA [1].

*Furthermore, Vj+1,1and Vj+1,2* are derived mathematically as follows. First, assume

*C*_{1} *= C × (1 + δ*_{1}) *C*_{2} *= C × (1 + δ*_{2})

*C*_{3} *= C × (1 + δ*_{3}) *C*_{4} *= C × (1 + δ*_{4})

*Vj,*1 *= V − ∆V/2* *Vj,*2*= V + ∆V/2* (3.1)

*where δ*1*, δ*2*, δ*3*, and δ*4 are independent random variables with zero mean and variance,

*σ*2*; ∆V is difference of Vj,*1 *and Vj,*2*; and V is average of Vj,*1 *and Vj,*2. According to the

charge reservation at the summing node X, we have

Hold phase 1: *C*1*× Vj,*1*+ C*2*× Vj,*2*= C*2*(Dj· Vr*)*+ C*1*× Vj+1,1*

Hold phase 2: *C*1*× Vj,*1*+ C*2*× Vj,*2*= C*1*(Dj· Vr*)*+ C*2*× Vj+1,2* (3.2)
Substituting (3.1) into (3.2) and rearranging the equation of (3.2) obtains

*Vj+1,1* ≈ *(2V − Dj× Vr*)*+ (δ*2*− δ*1*)(V − Dj× Vr*)
*+δ*1*(δ*1*− δ*2*)(V − Dj× Vr*)*+ (δ*1*− δ*2)
*∆V*
2
*Vj+1,2* ≈ *(2V − Dj× Vr) − (δ*2*− δ*1*)(V − Dj× Vr*)
*+δ*2*(δ*2*− δ*1*)(V − Dj× Vr*)*+ (δ*2*− δ*1)
*∆V*
2 (3.3)

**Vj,2**
**C1**
**C2**
**(b) Sampling phase 2**
**C4**
**Vj+1,1**
**Dj xVr**
**C4**
**Dj xVr**
**C1**
**C2** **C3**
**Next Stage**
**(d) Hold phase 2**
**Vj+1,2**
**X**
**C2**
**C1**
**Vj,1**

**(a) Sampling phase 1**

**C2**

**C1** **C3**

**Next Stage**
**(c) Hold phase 1**

**X**

3.3. FOREGROUND DIGITAL CALIBRATION 31

**Stage**

**j**

**Vj+1**

**Dj**

**Do,j**

**Vc**

**Vj**

**CAL**

**0**

**1**

**z−ADC**

**Dz**

**Dz**

**Param.**

**Calcu.**

**Wj**

**Ts**

**Digital Output Encoder**

Figure 3.3: Block diagram of foreground digital self-calibration.

*and C*4after charge sharing is given by

*Vj*+1 =
*C*_{3}*Vj+1,1+ C*4*Vj+1,2*
*C*_{3}*+ C*_{4} *= (2 + εj)Vj*−(1*+ εj)Dj× Vr* (3.4)
where
*εj* =
1
2*(δ*1*− δ*2*)(δ*1*− δ*2*− δ*3*+ δ*4)
with
(
*E{εj*}*= σ*2
*var{εj*}*= 3σ*4

It shows that the first order error in the input signal is suppressed to the second order; and hence, employing PECA technique enhances linearity.

### 3.3

### Foreground Digital Calibration

Fig. 3.3 shows the block diagram of foreground digital self-calibration for a pipelined
*ADC. During calibration phase (CAL* = 1), the normal A/D conversion is interrupted.
*During sample phase, the Vc* signal is applied to the input of the stage under calibration.
*During hold phase, the digital test signal, Ts*, is applied to the sub-DAC of the stage
*generate the Vj*+1*output. Then, the Vj*+1 signal is digitized by the following stages named

**Vj**
**Dj,l−1** **Dj,l** **Dj,l+1** **Dj**
**V _{l−1}th**

**V**

_{l}th**Vl−2th**

**Vl+1th**

**Calibrated**

**Actual**

**Ideal**

**0**

**Djz**

**a**

**Djz**

**b**

**Djz**

Figure 3.4: Transfer curve of (j+z)-ADC.

*as z-ADC, and generates Dz* *digital output. According to (2.36), the relationship of Dz*
*and Vj*+1 is given by
*Vj*+1 *= ˆGj*×*Vj*− ˆ*Vj*da*(Dj) − Vj*os
= *Gz*
ˆ
*Gz*
*Dz+ Oz+ Qz* (3.5)
*where Gz/ ˆGzis the gain error of z-ADC, Oz*is the digital o*ffset, and Qz*is the quantization
error of z-ADC. Hence, we have

*Vj*+1 *= ˆGj*×*Vc*− ˆ*Vj*da*(Ts) − Vj*os
= *Gz*
ˆ
*Gz*
*Dz+ Oz+ Qz* (3.6)
*To evaluate the calibration parameters, the transfer curve of the Vj* signal versus its
*corresponding digital output Djz* *is shown in Fig. 3.4 as an illustration. When the Vc*
*calibration signal is set as the V _{l}*th

*threshold level, and Ts*is set as the successive decision

*codes, Dj,l−*1

*and Dj,l*respectively, we have

*Vj*+1*(Dj,l−*1) *= ˆGj*×*[V _{l}*th− ˆ

*Vj*da

*(Dj,l−*1

*) − Vj*os] (3.7)

*Vj*+1*(Dj,l*) *= ˆGj*×*[Vl*th− ˆ*V*

da

*j* *(Dj,l) − Vj*os] (3.8)
*where Vj*+1*(Dj,l−*1*) and Vj*+1*(Dj,l) represent the stage analog output corresponding to Ts* =

3.3. FOREGROUND DIGITAL CALIBRATION 33

*Dj,l−*1 *and Ts* *= Dj,l*. By subtracting (3.7) from (3.8), we have
_{ˆ}
*V _{j}*da

*(Dj,l*) − ˆ

*Vj*da

*(Dj,l−*1) +

*Vj*+1

*(Dj,l) − Vj*+1

*(Dj,l−*1) ˆ

*Gj*= 0 (3.9)

*Rearranging (3.9) obtains the transition height when code Dj,l−*1*transfers to code Dj,l*; the
transition height is expressed as

ˆ

*Gj*× ˆ*Vj*da*(Dj,l*) − ˆ*Gj*× ˆ*Vj*da*(Dj,l−*1)*= Vj*+1*(Dj,l−*1*) − Vj*+1*(Dj,l*) (3.10)
*As Vj*+1 is digitized by z-ADC, the transition height can be given in digital form as

ˆ
*Gj*× ˆ*Vj*da*(Dj,l*)− ˆ*Gj*× ˆ*Vj*da*(Dj,l−*1)=
*Gz*
ˆ
*Gz*
*(Dz,l−*1*−Dz,l*)*+(Oz,l−*1*−Oz,l*)*+(Qz,l−*1*−Qz,l*) (3.11)
In reality, the evaluation for a transition height will be iteratively performed hundred
of times which are typical power of 2. The digital output codes of these evaluations are
accumulated and averaged to obtain the data which are immune of the influence of random
*noise. Here, define the digital calibration parameter of the j-th stage as Wj(Dj,l), for all l,*
and is given by
*Wj(Dj,l) ≡ E*
_{ˆ}
*Gj*× ˆ*Vj*da*(Dj,l*)
(3.12)
According to (3.11), we have
*Wj(Dj,l*)*= Wj(Dj,l−*1)*+ E*
* Gz*
ˆ
*Gz*
*(Dz,l−*1*− Dz,l*)*+ (Oz,l−*1*− Oz,l*)*+ (Qz,l−*1*− Qz,l*)
(3.13)
*where E{} is the evaluation operation of expected value. Evaluating all the calibration*
*parameters, Wj(Dj,l), for all l, and assume Wj*(0) = 0 without loosing generality. Then,
the calibrated transfer curve of the (j+z)-ADC can be constructed shown as the dash line
in Fig. 3.4. Employing this calibrated curve for (j+z)-ADC achieves the digital output,

*Djz*, without the first order errors.
From (3.5), we have
*Vj* *= ˆVj*da*(Dj*)+
*Vj*+1
ˆ
*Gj*
*+ V*os
*j* =
*Gjz*
ˆ
*Gjz*
*Djz+ Ojz+ Qjz* (3.14)
*With calibration, Vj*can be rewritten as

*Vj* =
*Gjz*
ˆ
*Gjz*
* Wj(Dj*)*+ Dz*
*Gj*
*+ Ojz+ Qjz* (3.15)

**Main ADC**

**fs**

**Adaptive**

**Filter**

**Do**

**Vi**

**Dr**

**fs /Md**

**Reference ADC**

**(SH−ADC)**

**Dd**

**De**

Figure 3.5: Block diagram of equalization-based digital background calibration.

with the gain error

*Gjz*
ˆ
*Gjz*
= *GjGz*
ˆ
*GjG*ˆ*z*
(3.16)
*and Ojz*is (j*+z)-ADC’s digital offset; Qjz*is quantization error. Furthermore, (j+z)-ADC
is used for calibrating the (j-1)-th stage. Calibration is performed toward the front-end
pipeline stage until finishing the first stage calibration, and the calibration cycle is
com-pleted. All the calibration parameters are stored in memories and used for combining
*with Dz* to generate the final ADC’s digital output as the ADC performs normal A/D
conversion.

### 3.4

### Background Digital Calibration

The equalization-based (EB) method based on least-mean-square (LMS) algorithm for estimating calibration parameters is discussed here. When an LMS approach is applied for calibration, a desired signal needs to be addressed to adaptively adjust calibration pa-rameters. A slow, high-resolution ADC (SH-ADC) is therefore employed for generating the desired signal.

Fig. 3.5 shows the block diagram of the EB digital background calibration. The input
*is applied into the main ADC operating at the sample rate of fs*, as well as the reference

3.4. BACKGROUND DIGITAL CALIBRATION 35

**D**

**D**

### µ

_{o}

_{o}

**Md**

**Md**

**De**

**Dd**

**Dr**

### µ

_{g}

_{g}

**fs**

**fs Md**

**/**

**Pipelined ADC**

**SH−ADC**

**Vi**

**g**

**o**

**Gain Cal.**

**Offset Cal.**

**Do**

Figure 3.6: EB digital background calibration using LMS algorithm.

*ADC operating at much lower sample rate, fs/Md. The Do* output is subtracted from the

*Dd* *desired output to produce the De* error signal. This error signal is then fed into the
*adaptive filter to adjust its parameters to minimize De*.

Fig. 3.6 shows the block diagram of the EB background calibration using the LMS
*al-gorithm. The Vj*stage input not only applies into the normal A/D pipes, but also injects to
*the SH-ADC every Md*clock cycles. The SH-ADC digitizes the stage input and generates
*the Dd* *digital desired signal as a reference for the LMS algorithm. Assume the Dr* raw
*digital output is corrected by gain g, and offset error o, and the corrected digital output is*
obtained by

*Do* *= g × Dr+ o* (3.17)

*where g and o are the calibration parameters determined by LMS adaptive mechanism.*
The LMS algorithm employed in the adaptive mechanism is summarized below:

*1. Initialize the parameters, (g[0], o[0]).*
2. Calculate error:

*De[n*0]*= Dd[n*0*] − Do[n*0] (3.18)
*3. Adjust parameter g[n*0* _{] and o[n}*0

_{] as:}

*g[n*0]*= g[n*0−1]*+ µg* *× De[n*
0
*] × Dr[n*
0
] (3.19)
*o[n*0]*= o[n*0−1]*+ µo× De[n*0] (3.20)
*where n*0 *indicates the time index downsampling by Md; µg* is the updating step size for
*gain, and µo* is the updating step size for offset. When the adjustment is convergent, the
*LMS algorithm gives a unique desired solution for the parameters g and o. Therefore,*
*the final digital output, Do*, is corrected according to (3.17). A trade-off exists between
convergent time and step size for the LMS algorithm. As the convergent time depends on
the updating step size, small step size makes long convergent time.

Employing the EB calibration produces the drawbacks that this calibration scheme requires an additional SH-ADC. Therefore,the complexity of analog circuits increases, and so is analog hardware, as well as analog power consumption. In addition, as the SH-ADC is binded at the input, large input loading capacitance appears such that increases the required input driving capability.

Digital background calibration using correlation-based (CB) method is used to
*im-prove the entire A/D linearity by applying a test signal, Ts*, to the stage under calibration,
*as shown in Fig. 3.7. The Tssignal is included in the Vj*+1stage output which is quantized
by the backend stages (z-ADC). A digital random sequence which is uncorrelated with
the input signal, and has zero mean is typically used as the test signal to dither calibration
parameter in analog domain and extract the calibration parameter in digital domain. A
*simplified model of the stage usder CB calibration is shown in Fig. 3.8. As the q random*
*signal dithers the Rc* calibration parameter of the j-th stage, the stage’s analog output,

*Vj*+1, is given by

*Vj*+1 *= ˆGj*×*Vj*− ˆ*Vj*da*(Dj*)*+ Vj*os

*+ q × Rc* (3.21)

*where assume q is zero mean and is uncorrelated with the input. The widely used dithering*
*signal is the binary-valued pseudo-random sequence, i.e. q= {−1, +1}.*

3.4. BACKGROUND DIGITAL CALIBRATION 37

**Stage**

**j**

**Vj+1**

**Backend**

**Stages**

**(z−ADC)**

**Vj**

**Dz**

**Correlator**

**c**

**W**

**Ts**

**Ts**

**j**

**D**

**Calibration Processing and Output Correction**

**Do,j**

Figure 3.7: Block diagram of calibration employing CB method.

**Dj**

**Vj**

**Dj**

**Vj**

**Vj+1**

**qxRc**

**Gj**

**sub**

**ADC**

**sub**

**DAC**

**(**

**)**

**da**

*The dithered Vj*+1is then digitized by the following z-ADC, and generates the digital
*output, Dz. According to (3.5), the Dz*output is given by

*Dz*=
ˆ

*Gz*

*Gz*

×*(Vj*+1*− Oz− Qz*) (3.22)
*Furthermore, the calibration parameter Rc*is extracted based on evaluating the correlation
*between q and Dz*by using a correlation filter. The extracted digital calibration parameter
*named Wj*, is obtained by
*Wj= E{q × Dz*}*= E*
*q ×*
_{ˆ}
*Gz*
*Gz*
*(Vj*+1*− Oz− Qz*)
= *G*ˆ*z*
*Gz*
*Rc+ var{Wj*} (3.23)
*Only q × Rcshown in (3.21) correlated with q survives after passing the correlation filter.*
*However, since q is pseudo random sequence, variance of Wj* appears, and it is denoted
*as var{Wj*}*in (3.23). The obtained Wjis used to generate Djz*. Then, calibration
proce-dure is performed for (j-1)-th stage; the calibration works toward the first pipeline stage
and then iterated from the j-th stage. Finally, calibration parameter for each stage under
calibration is obtained, and the entire ADC’s digital output is corrected in digital domain.
The major drawback of CB calibration is long calibration time. The calibration time
*is determined by the resolution requirement of Wj. To achieve a resolution of Nj*bits, the
*extracted Wj*needs to satisfy the following condition:

10 log_{10} ( ˆ*Gz/Gz) × Rc*
*var{Wj*}

≥*6.02 × Nj+ 1.76* (3.24)
*where (6.02 × Nj* *+ 1.76) is the required signal-to-quantization noise ratio (SNR) for*
*achieving Nj*-bit resolution. Because of the long calibration time, a pipelined ADC with
CB calibration is unsuitable for real-time systems. Therefore, reducing uncorrelated
*com-ponents before extracting Wj*was presented that significantly reduced the calibration time
by employing the ”split-ADC” A/D architecture [30] [32].

### 3.5

### Proposed Background Digital Calibration

A correlation-based method using a binary-valued pseudorandom sequence to dither cal-ibration parameters for an SC pipelined ADC is proposed [4]. This technique requires