Electrical Characterization of Excimer Laser-Crystallized Double-Gate

Transistors

Figure 4-8 (a) and 4-8(b) show the typical transfer and output characteristics of proposed ELC DG LTPS TFT (Fig. 4-1 (b)) and conventional SPC DG TFT and conventional ELC TG TFT (Fig. 4-1(a)) for W = L = 1 µm. The nominal mobility of the DG TFT was calculated from transconductance (g_m), which we defined as a TG TFT of the same gate length and gate width with a 100 nm gate-SiO2 layer. Owing to both of the uniformly large transverse grains grown in the device channel region and double-gate operation mode, this proposed ELC DG TFT exhibits better electrical characteristics than conventional SPC DG TFT and conventional ELC TG TFT. Table 4-1 lists several important electrical characteristics of these there different TFTs. Via the top and bottom gates connected together, the higher electron density in the channel region at on state and the channel is more efficiently modulated by both gate electrodes [4.36]. Obvious improvement in devices characteristics is obtained for ELC DG TFTs instead of ELC TG TFTs, the threshold voltage decreases from -1.60 to -1.55 V, SS decreases from 0.258 to 0.172 V/dec, field-effect-mobility increases from 186 to 550 cm²/Vs, Ion/Ioff increases from 4.37× 10⁷ to 4.35× 10⁸ , and DIBL decreases from 0.241 to 0.075.

Because the top and bottom gates are symmetrical, in which the gate oxide thickness is the same, and connect together electrically to obtain a perfect coupling between the surface potential in the channel region and the gate. Consequently, the influence of the source and drain depletion regions are kept minimal, which in turn reduce the short channel effects by screening the source and drain electrical field lines away from the channel. In addition, lateral silicon grains formed in the channel region as the bottom-gate TFTs is obtained, the DG devices have a higher driving current, steeper subthreshold slope, smaller drain-induced-barrier-lowering, superior short-channel effect immunity, and suppression of the floating-body effect. But the proposed ELC DG TFT has a high off-current under a large

negative gate bias at the Vds = 3 V from the Id-Vg transfer characteristics. The large leakage current indicates that ELC DG TFTs suffer a higher lateral peak electric field than the ELC TG TFT [4.37]. If offset, lightly-doped-drain (LDD) and gate-overlapped lightly-doped-drain (GOLDD) structures were applied to the ELC DG TFTs, the severe anomalous off-current could be relieved by reducing the lateral peak electric field in the drain region [4.38]-[4.45].

In order to avoid the threshold voltage difference, the applied gate driving voltages in Figure 4-8 (b) are kept at constant values of |Vg-Vth| = 4, 8, 12 and 16 V, respectively. It is demonstrated that the ELC DG poly-Si TFTs exhibit higher driving capability due to both of the location-controlled silicon grains in the channel and double-gate operation mode. Take the

|Vg-Vth| = 8 V as an example, the current drivability of ELC DG poly-Si TFTs is about 2.1 times as large as that of an ELC TG poly-Si TFT and 18.1 times as large as that of a SPC DG poly-Si TFT under the same bias condition. At higher gate voltages, however, the current ratio between these three devices decreases. The plausible reason is the self-heating effect due to the large driving current on the poor thermal conducting SiO2 substrate. It also clearly shows that ELC DG poly-Si TFTs provide better current saturation characteristics than the other two TFTs. The superior short channel characteristics and driving capability imply that the proposed ELC DG-TFT structure is more suitable for high-resolution active matrix liquid crystal displays, active matrix organic light emitting displays, and device scaled-down applications.

The grain boundary trap state densities (Nt) of the conventional TG and proposed DG poly-Si TFTs were estimated according to the modified Levinsons analysis [4.46]-[4.47]. The Nt was extracted from the slopes of ln(ID/VGS) versus 1/(VGS) at VDS=0.1 V and high VGS. Figure 4-9 displays that ELC DG poly-Si TFT exhibits the Nt of 9.72× 10¹⁰ cm^-2 four times smaller that of conventional ELC TG TFT. This result implies that DG TFTs with lateral silicon grains possess better crystallinity and fewer microstructure defects which are also confirmed by cross-sectional TEM image of excimer laser crystallized poly-Si thin films with

double-gate structure shown in the Figure 4-10.

The dependence of field effect mobility on temperature for ELC DG TFTs with lateral silicon grains, ELC TG TFTs with random silicon grains and SPC DG TFTs was investigated to study the electron-transport-scattering mechanism of poly-Si thin films, as shown in the Figure 4-11. For ELC TG TFTs with random silicon grains, the electron field-effect-mobility increases as the temperature increases. Such positive temperature dependency of field-effect-mobility is attributed to the reduced grain boundary scattering where the probability of carrier transport over the grain boundary potential barrier height by thermionic emission increases [4.48]-[4.49]. On the other hand, negative dependency of field-effect-mobility for ELC DG TFTs with lateral silicon grains indicates lattice-phonon scattering is the dominate scattering mechanism because only one grain boundary perpendicular to the direction of current flow in the channel region [4.50]. The field-effect-mobility of SPC DG TFTs increase as first and then starts to decrease as the temperature increases, indicating grain-boundary scattering and lattice-phonon scattering compete with each other and dominate under different temperature.

Figure 4-12 displays the dependence of field effect mobility on laser energy densities for DG TFTs and conventional TG ones whose channel length is 1 µm. Twenty TFTs were measured for each laser irradiation condition to investigate the device-to-device uniformity.

Compared to the conventional ELC TG-TFTs, it was found that ELC DG-TFTs with lateral silicon grains exhibited smaller electrical deviation since the number of spontaneous small grains and grain boundaries were reduced and the uniformity of TFTs performance could be improved with artificially laterally-grown grains.

The device transfer and output characteristics of high-temperature and low-temperature DG TFTs are shown in Figure 4-13 (a) and 4-13 (b), respectively. Some important electrical characteristics of LTPS TFTs are also listed in Table 4-2. Opened curves are for the

mobility was 550 cm² /Vs at Vds = 0.1 V. The off current was 1 pA/µm at Vds = 3 V. The on–off current ratio was 4.30x 10⁸. Threshold voltage was -1.55 V, and a subthreshold swing 0.180 V/decade, respectively. The output characteristic shows the kink current was mostly suppressed. Characteristics are also shown in Fig. 4-13 (a) by solid curves for the high-temperature processed TFT. The field-effect mobility was 1050 cm /Vs, the off current 0.2 pA/µm, the threshold voltage -2.58 V, the subthreshold voltage swing 0.166 V/decade, and DIBL 0.059 V/V, respectively.

The high field-effect mobility means that the single high angle grain boundary in the middle of the channel region does not disturb seriously the carrier drift transportion. And the low off current implies that the crystallinity and defect density of the grain at the drain region is pretty good and low. For the kink effect, there is also a room for perfect killing, since deep traps at the grain-boundary can act more effectively as carrier recombination centers, if the Si film thickness is reduced from 100 nm. In addition, we speculated that the further improved performance for the high temperature processed TFT with LPCVD gate oxide came predominantly from the better quality gate insulator and the thermally annealing of the insulator-semiconductor interface. Thus, we expect that the low-temperature TFT performance can be improved by better cleaning process and deposition process of high-quality SiO2. Figure 4-14 displays the basic electrical characteristics of the n-channel and p-channel ELC DG LTPS TFTs with LPCVD gate oxide. Some important electrical characteristics of high-temperature processed ELC DG LTPS TFTs are also listed in Table 4-3.

Ultra high-performance ELC DG LTPS TFTs with field effect mobility of 1050 cm^P2P/V-s for n-channel and 484 cm^P2P/V-s for p-channel, substhreshold swing of 166 mV/dec for n-channel and 96 mV/dec for p-channel, on/off current ratio more than 10^P9P for n-channel can be achieved. These values are superior to those of single-crystal silicon MOSFET.

Proposed double-gate TFTs are less prone to the self-heating effect than the conventional single-gate TFTs, shown in Figure 4-13 (b). Indeed, single-gate TFTs are thermally isolated

from the substrate owing to the thick buried oxide, which exhibits a low thermal conductivity.

In the case of double-gate TFTs, the device channel regions are isolated from the substrate by the top-gate electrode, bottom-gate electrode, and two thin gate-oxide layers, which exhibit a much better thermal conductivity path to the substrate than a thick buried oxide. Thus, in spite of the high driving current in the double-gate TFTs, slightly self-heating effect is observed in DG TFTs.

Figure 4-15 (a) shows the comparison of the transfer characteristics of top gate, bottom gate and double gate devices crystallized by ELC with plateau structure in which the channel length is 1µm and P-type carrier. It is found that the on current is enhanced with the double-gate TFTs. For the comparison of bottom gate and top gate devices, the current drive in the single gate operation is not the same between the top-gate and bottom-gate devices.

This is considered to be attributed to the asymmetrical channel structure resulting from the process steps of device fabrication. The top gate TFTs exhibit higher field-effect mobility than bottom gate ones. This might arise from the fact that the TG device is a self-aligned structure during ion implantation of source/drain regions, while the BG device is a non-self-aligned structure. Therefore, the parasitic resistance in TG device is smaller than that of BG device and the TG exhibit higher performance than BG one. For the comparison of double gate devices and top/bottom gate devices, we could refer to the extracted electrical characteristics listed in Table 4-4. The steeper subthreshold swing and smaller DIBL reveal the enhanced gate controlling ability of double gate structure. The equivalent field-effect mobility of p-channel double gate TFTs was 484cm²/V-s, while that of p-channel top gate TFTs and p-ahannel bottom gate TFTs was 221cm²/V-s and 130cm²/V-s, respectively. The driving current of double gate devices is higher than the sum of top gate and bottom gate devices, as shown in Figure 4-15(b). This phenomenon indicates that the top-gate electrode and bottom-gate electrode are well-coupled and give both influences on the channel carrier

4.4 Summary

A novel high-performance DG LTPS TFTs have been fabricated by excimer laser crystallization. The microstructure of poly-Si films and the completed device structure were analyzed by an analytical transmission electron microscopy. Because the top and bottom gates are symmetrical, in which the gate oxide thickness is the same, and connect together electrically to obtain a perfect coupling between the surface potential in the channel region and the gate. Consequently, n-channel DG LTPS TFTs exhibit high field-effect-mobility of 550 cm²/Vs, SS of 0.172 V/dec, I_on/I_off of 4.35× 10⁸, and DIBL of 0.075 and excellent short channel characteristics because of the large transverse grains artificially grown in the channel region and double-gate structure for better gate controllability. In addition, the experimental results reveal a steeper subthreshold value, smaller drain-induced-barrier-lowering, higher driving current, suppression of the floating-body effect, and excellent device uniformity in proposed DG TFTs. Moreover, ELC DG LTPS TFTs (W/L = 1/1 µm) with high-temperature processed LPCVD gate oxide have the equivalent field-effect-mobility exceeding 1050 cm²/Vs for the n-channel device, 484 cm²/Vs for the P-channel device, substhreshold swing of 166 mV/dec for n-channel and 96 mV/dec for p-channel, on/off current ratio higher than 10⁸ for both structures, smaller DIBL (59 mV/V) for n-channel ones, DIBL (33 mV/V) for p-channel ones. We also compare the electrical characteristics of top gate, bottom gate and double gate devices crystallized by ELC with plateau structure in which the channel length is 1µm and P-type carrier. From the experimental results, the performances are greatly improved in the double-gate TFTs as compared with the top-gate TFTs and bottom-gate TFTs. The larger on current, higher field-effect mobility, steeper subthreshold swing and smaller DIBL reveal the enhanced gate controlling ability of double gate structure. The ELC DG TFTs are,

therefore, ideally suitable for future system-on-panel and 3 dimensional integrated circuit applications.

Table 4-1

Measured electrical characteristics of ELC DG TFTs with lateral grain growth, SPC DG TFTs, and conventional ELC TG TFTs.

TFT Structures

Measured electrical characteristics of ELC DG TFTs with high-temperature LPCVD gate oxide and ELC DG TFTs with low-temperature PECVD gate oxide.

TFT Structures

Table 4-3

Measured electrical characteristics of high-temperature processed n-channel and p-channel ELC DG TFTs with lateral grain growth.

TFT Structures

Measured electrical characteristics of ELC DG TFTs with lateral grain growth, ELC TG TFTs with lateral grain growth, and ELC BG TFTs with lateral grain growth.

TFT Structures

Figure 4-1. The schematic cross-sectional view of the different poly-Si TFT devices. (a) Conventional n-channel top-gate TFT and (b) n-channel DG TFT.

poly-Si gate Oxidized Silicon Wafer

a-Si Gate oxide Thicker a-Si region

: Direction of grain growth Excimer Laser Irradiation

Figure 4-2. The key fabrication process steps for the proposed short-channel double-gate LTPS TFTs structure crystallized with excimer laser annealing.

Figure 4-3. (a) The optical micrograph, (b) the bird-eye SEM graph, and (c) the cross-sectional SEM graph of proposed excimer-laser-crystallized double-gate LTPS TFTs.

Figure 4-4. The Cross-sectional TEM photograph of connection of the top-gate electrode and the bottom-gate electrode and energy dispersive X-ray (EDX) Spectrometer analyses.

Figure 4-5. Atomic force microscopy (AFM) images of poly-Si thin film with bottom-gate structure after laser irradiation.

Source Drain

Channel

Impinged Grain

boundaries

Figure 4-6. Scanning electron microscope (SEM) micrographs of excimer laser crystallized poly-Si film with bottom-gate structure after Secco etching, in which the device channel length was (a) 1.2, (b) 1.5, and (c) 2 µm, respectively.

Figure 4-7. The cross-sectional TEM image and the selected-area electron diffraction patterns of the fabricated ELC double-gate poly-Si TFTs. The channel length of DG TFTs is 1.2 µm. The thickness of top-gate electrode, top-gate oxide, poly-Si channel layer, bottom-gate oxide, and the bottom-gate electrode all are 100 nm. The insets show the top-view SEM graph of excimer laser-crystallized poly-Si thin films with bottom-gate structure and the high-resolution cross-sectional TEM image of the grain boundary region.

Figure 4-8 (a). Transfer characteristics of proposed ELC DG TFT, conventional SPC DG TFT, and conventional ELC TG TFT.

Figure 4-8 (b). Output characteristics of proposed ELC DG TFT, conventional SPC DG TFT,

Figure 4-9. Plot of ln(I_D/V_GS) versus 1/(V_GS) curves at V_DS = 0.1 V and high V_GS for DG poly-Si TFTs and conventional TG ones.

Figure 4-10. FIB-prepared cross-sectional TEM image of excimer laser crystallized DG poly-Si TFTs.

2.4 2.6 2.8 3.0 3.2 3.4 0.7

0.8 0.9 1.0 1.1

ELC DG TFT with lateral silicon grains Conventional ELC TG TFT

ELC BG TFT with lateral silicon grains SPC DG TFT

Mobility Ratio

1/T (1/K)

Figure 4-11. The dependence of field effect mobility on temperature for ELC DG TFTs with lateral silicon grains, ELC TG TFTs with random silicon grains and SPC DG TFTs.

Figure 4-12. Dependence of field-effect mobility on applied laser energy density for ELC DG

-15 -10 -5 0 5 10 15

Figure 4-13 (a). Transfer characteristics of proposed high-temperature ELC DG TFT with LPCVD gate oxide and proposed low-temperature ELC DG TFT with PECVD gate oxide.

0 1 2 3 4 5 6

Figure 4-13 (b). Output characteristics of proposed high-temperature ELC DG TFT with LPCVD gate oxide and proposed low-temperature ELC DG TFT with PECVD gate oxide.

Figure 4-14(a). Transfer characteristics of high-temperature processed n-channel and p-channel ELC DG LTPS TFT with LPCVD gate oxide.

Figure 4-14(b). Output characteristics of high-temperature processed n-channel and p-channel

-15 -10 -5 0 5 10 15

DG TFTs with lateral grain growth TG TFTs with lateral grain growth BG TFTs with lateral grain growth

Fi el d Ef fect M obi lit y ( c m

/V -s )

Figure 4-15 (a). Transfer characteristics of proposed p-channel ELC DG TFT, proposed p-channel ELC TG TFT, and proposed p-channel ELC BG TFT which are crystallized with plateau structure.

-6 -5 -4 -3 -2 -1 0 0.00

0.05 0.10 0.15 0.20

l Vg-Vth l = 6 V

DG TFTs TG TFTs BG TFTs

Conv TG TFTs TG+BG TFTs

Dr ain Curr ent I

(m A )

Drain Voltage V

(V)

Figure 4-15 (b). Output characteristics of proposed p-channel ELC DG TFT, proposed p-channel ELC TG TFT, and proposed p-channel ELC BG TFT which are crystallized with plateau structure, and conventional p-channel TG TFT.

Chapter 5

Periodically Lateral Silicon Grains Fabricated by Excimer Laser Irradiation with Amorphous Silicon

Spacers and Its Application to High-Performance Low Temperature Polycrystalline Silicon

Thin Film Transistors

5.1 Introduction

Low-temperature polycrystalline silicon (LTPS) thin film transistors fabricated by excimer laser crystallization (ELC) have been extensively studied for active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting displays (AMOLEDs) owing to their high driving-current capability [5.1] - [5.2]. Although field-effect-mobility of 200 cm²/Vs for TFTs has been attained by ELC, it is difficult to make the laser energy density hit the super lateral growth regime everywhere due to the fluctuation of pulse-to-pulse energy and amorphous silicon (a-Si) layer thickness [5.1] - [5.5]. Furthermore, in the applications of system-on-panel (SOP), high-performance LTPS TFTs are still needed to integrate memory and controller with driver circuits on a single substrate. Thus, there is a great interest in improving the performance of LTPS TFTs by laser crystallization approaches, including sequential lateral solidification by laser beam scanning within several micrometers step by step [5.6]-[5.9], phase-modulated ELC using an optical phase-shift mask [5.10]-[5.12],

µ-Czochralski (grain filters) method [5.13]-[5.15], ELC of selectively floating a-Si layer [5.16]-[5.17], CLC method using the diode-pumped solid state continuous wave laser [5.18]-[5.19], and selectively enlarging laser crystallization (SELAX) [5.20]. However, most of them are complicated or not easy to be controlled from the viewpoints of LTPS TFTs fabrication.

In the previous works, the crystallinity of poly-Si thin film can be effectively enhanced via ELC with bottom-gate structure, however it is inevitable that there is a high angle grain boundary in the middle of channel region, which degrades the TFT performance and reliability. In this chapter, a novel and simple laser crystallization method which can remove the high angle grain boundary and produce the large and uniform grains in the desired local region is proposed to improve the field-effect mobility as well as the device uniformity.

Consequently, high-mobility poly-Si TFTs has been demonstrated owing to the periodically lateral silicon grains with 2 µm in length artificially grown in the channel regions via the amorphous silicon spacer structure with excimer laser irradiation. The concept of controlled lateral grain growth is first discussed. Then, the experimental details are described in detail.

Next, the microstructure of ELC poly-Si thin film with a-Si spacer structure is analyzed by SEM, Raman spectrum, and AFM. The electrical characteristics of the resulting ELC LTPS TFT performance are presented and analyzed. It leads to the enhancement of device performance and the improvement of device uniformity. The effect of the number of grain boundary on large dimension TFTs is also investigated.

5.2 The Basic Concept of Periodically Lateral Silicon

Grains Employing Excimer Laser Crystallization with a-Si

Spcaer Structures

It is well-known that the electrical characteristics of poly-Si TFTs are deeply influenced on the microstructure of poly-Si thin films, including grain crystallinity, grain size, grain structure, grain boundary, and grain orientation. Reducing the grain boundaries within the active channel region is an effective way to improving TFT performance and uniformity. As expected, the lateral large grains with excellent quality in the channel region are desirable for

It is well-known that the electrical characteristics of poly-Si TFTs are deeply influenced on the microstructure of poly-Si thin films, including grain crystallinity, grain size, grain structure, grain boundary, and grain orientation. Reducing the grain boundaries within the active channel region is an effective way to improving TFT performance and uniformity. As expected, the lateral large grains with excellent quality in the channel region are desirable for