Chapter 2 High-Performance Low Temperature Polycrystalline Silicon
2.5 Summary
A new crystallization technology for producing lateral silicon gains has been developed by excimer laser irradiation with bottom gate structure. The mechanism of lateral grain growth using plateau structure of a-Si thin film with excimer laser crystallization is based on the spatial thermal gradient. The microstructure of poly-Si thin film with bottom-gate structure was analyzed by several material analyses, including SEM, AFM, TEM, and the factors that affected the final lateral crystallization microstructure were also investigated, including thickness of a-Si thin film, thickness of gate dielectric, thickness of gate electrode, laser shot number, and laser energy density. It can be observed that the large longitudinal grains artificially grown measuring about 0.85 µm were observed in length in the device channel region, while small and fine grains are located near the edges of the bottom-gate electrode.
According to the TEM images, not only the interface between the poly-Si channel and bottom-gate oxide but also bottom-gate electrode and bottom-gate oxide is clear, implying that both the gate oxide and the bottom-gate electrode are not damaged during excimer laser irradiation. From the correlated selected-area diffraction pattern of poly-Si thin film, it is found that the crystallinity of the silicon grain silicon in the channel region is excellent.
Moreover, the process window could be broadened because the laser energy densities were
easier to be controlled for the wider laser energy density range. Therefore, the improved uniformity of TFTs performance is attained due to large silicon grains. In consequence, not only high-performance n-channel LTPS TFTs with field-effect-mobility exceeding 330 cm2/Vs in 1.5 µm design rule, but also excellent uniformity of device performance are also demonstrated owing to the artificially-controlled lateral grain growth in the device channel regions. The process steps in these technologies are highly compatible with the conventional commercial a-Si TFTs. Moreover, the experimental results revealed higher breakdown voltage and better reliability due to the smooth interface between gate dielectric and poly-Si channel films as thinner gate oxide were employed. LTPS BG-TFTs with lateral silicon grains are therefore promising for future SOP and AMOLED applications.
Table 2-1
Measured electrical characteristics of bottom-gate LTPS TFTs and conventional top-gate ones.
TFT structure
Measured electrical characteristics of bottom-gate LTPS TFTs and conventional top-gate ones.
(W = L = 1.5 µm and gate oxide thickness of 500 Å or 1000 Å.)
Figure 2-1. The schematic illustration of the mechanism of lateral grain growth using bottom-gate structure of a-Si thin film.
Figure 2-2. The schematic illustration of excimer laser crystallization system.
excimer laserKrF
attenuator
homogenizer
focus lens mirror
quartz window
lamp heaters specimen
vacuum system
monitorCCD
X-Y translation stage
Figure 2-3. The process procedures for the preparation of poly-Si thin films with bottom-gate structure crystallized by ELC.
Figure 2-4. The key processes for fabricating short channel bottom-gate LTPS TFTs with excimer laser annealing.
Figure 2-5. (a) The schematic cross-sectional drawing of conventional top- gate LTPS TFTs using the super lateral growth (SLG) excimer laser annealing condition. (b) Plane-view SEM micrograph of excimer laser crystallized poly-Si thin film with SLG laser annealing condition after Secco-etch.
Channel
Source Drain
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Figure 2-6. The SEM micrographs of excimer laser crystallized poly-Si thin films with bottom-gate structure after Secco etching, in which the device channel length was (a) 1.2 µm, (b) 1.5 µm, and (c) 2.0 µm, respectively. In this case, the laser shot number is single pulse and the poly gate thickness was 1000 Å. The laser energy density is 450 mJ/cm2.
~1.5um
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Figure 2-7. Scanning electron microscope micrographs of excimer laser crystallized poly-Si thin film with bottom-gate structure after Secco-etch, in which the device channel length was 1.5µm, and the laser shot number was (a) 1shot, (b) 20 shots, and (c)
Channel
Figure 2-8. Scanning Electron Microscope micrographs of excimer laser crystallized poly-Si thin film with bottom-gate structure after Secco-etch, in which the device channel length was 1.5µm, and the laser energy density was (a) 430, (b) 450, and (c) 490 mJ/cm2, respectively.
Channel
Source Drain
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Source Drain
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Source Drain
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Fig. 2-9. The SEM micrographs of poly-Si thin films irradiated by excimer laser shot number of 20 shots and the gate oxide thickness of (a) 30, (b) 50, and (c) 100 nm, respectively, in which the device channel length was 1.5 µm. The laser energy
2
Source Channel Drain
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Source Channel Drain
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Source Channel Drain
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Source Channel Drain
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Fig. 2-10. The SEM micrographs of poly-Si thin films irradiated by excimer laser shot number of 20 shots and the bottom-gate thickness of (a) 100, (b) 200, and (c) 300 nm, respectively, in which the device channel length was 1.5 µm.
Figure 2-11. The AFM image of 1000 Å-thick poly-Si thin films with bottom-gate structure after laser crystallization, in which the device channel length is 1.5 µm. In this case, the laser shot number is 20 shots and the bottom-gate thickness is 1000 Å.
Figure 2-12. The cross-sectional TEM image of 1000 Å-thick poly-Si thin films with bottom-gate structure after laser crystallization, in which the device channel length is 1.5 µm.
0 50 100 150 200 250 300 350 400 450 500
P31+ profile before laser annealing P31
+ profile after laser annealing at 490 mJ/cm2 P31
+ profile after laser annealing at 390 mJ/cm2
Secondary ion conut s ( a .u .)
Depth (nm)
Figure 2-13. The element SIMS depth profiles of the excimer laser-crystallized bottom-gate TFTs
Figure 2-14. Comparisons of (a) Transfer characteristics and (b) Output characteristics for ELC BG LTPS TFT with lateral silicon grains and conventional ELC TG TFT.
Figure 2-15. Dependence of field-effect-mobility on the device dimension for ELC BG LTPS TFTs with lateral silicon grins and conventional ELC TG ones. The field effect mobility was evaluated at Vds = 0.1 V.
Figure 2-16. Dependence of field-effect-mobility on applied laser energy density for ELC BG TFTs with lateral silicon grins and conventional ELC TG ones with random grain structures.
-15 -10 -5 0 5 10 15
Figure 2-17 (a). Comparison of the transfer characteristics of the n-channel LTPS BG-TFTs with lateral silicon grains and conventional TG ones with W = L = 1.5 µm and gate oxide thickness of 500 Å or 1000 Å.
0 1 2 3 4 5 6
Conventional TG TFT with oxide 50 nm Conventional TG TFT with oxide 100 nm Proposed BG TFT with oxide 50 nm Proposed BG TFT with oxide 100 nm
Figure 2-17 (b). Comparison of the output characteristics of the n-channel LTPS BG-TFTs with lateral silicon grains and conventional TG ones with W = L = 1.5 µm and gate oxide thickness of 500 Å or 1000 Å.
0 1 2 3 4 5 6 7 8 9 10 Gate oxide thickness = 50 nm W/L = 2µm/1.5µm
Figure 2-18 (a). The gate-breakdown field strength of two different TFT structures with 500 Å-thick TEOS gate oxide.
Figure 2-18 (b). Statistical distribution of the gate-breakdown voltage of two different TFT structures with 500 Å-thick TEOS gate oxide.
Chapter 3
High-Performance Self-Aligned Bottom-Gate Low Temperature Polycrystalline Silicon Thin-Film Transistors with Excimer Laser Crystallization
3.1 Introduction
Low-temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) have been extensively investigated for use in active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting displays (AMOLEDs) [3.1]-[3.7]. The mobility of poly-Si TFTs fabricated by excimer laser crystallization is generally two orders higher than amorphous-Si TFTs, therefore the peripheral driving circuits and pixel elements can be integrated on the same glass substrate. In the early stage of the LTPS TFTs development, bottom-gate (BG) TFT structure was attractive because the excimer laser annealing was thought as an additional process step to the a-Si TFTs. However, bottom-gate TFTs suffered from worse electrical performance than top-gate (TG) TFTs because of the smaller grain size and poor grain quality resulting from the bottom-gate metal acting as a heat sink during excimer laser crystallization [3.8]-[3.9]. Moreover, bottom-gate TFTs exhibited significant performance variation as the devices scaled-down resulted from the misalignment effect. Although some self-aligned (SA) BG TFTs have been demonstrated, the device processes were too complicated to be utilized in the large area fabrication [3.10]-[3.11]. As a result, only a few studies have been conducted for bottom-gate TFTs with short channel length and top-gate TFTs have been widely adopted
in AMLCD due to the self-alignment capability in the last decade. Although high field-effect-mobility for TG-TFTs has been attained by ELC, it is difficult to make the laser energy density hit the super lateral growth regime everywhere due to the fluctuation of pulse-to-pulse laser energy and amorphous silicon (a-Si) layer thickness [3.12]-[3.14].
Consequently, poor device uniformity and narrow process window were encountered in ELC TG-TFTs. Furthermore, in the applications of system-on-panel (SOP), TFTs must exhibit good uniformity of device-performance and high-reliability. Thus, many methods, such as sequential lateral solidification process [3.15], grain filters method [3.16], capping the reflective or anti-reflective layer [3.17], dual beam ELA [3.18], double–pulsed laser annealing [3.19], selectively floating a-Si active layer [3.20], CLC method using the diode-pumped solid-state continuous wave laser [3.21], and selectively enlarging laser crystallization (SELAX) [3.22], were proposed to solve the above problems. However, most of them need complex fabrication process or are problematic for circuit layout due to the anisotropy of the grain boundary spacing.
In the previous work, ELC BG LTPS-TFTs exhibit superior electrical characteristics, however, asymmetrical electrical characteristics are also observed due to the misaligned process effect. Besides, the mis-alignment effect will degrade the TFT performances more seriously in the short channel devices owing to the more percentage of the mis-alignment variation. Therefore, in this work, a self–aligned (SA) bottom-gate TFT with appropriate channel length has been fabricated by the simple excimer laser crystallization and backside exposure. The process steps in these technologies are not only highly compatible with the conventional commercial a-Si TFT process but also with minimum parasitic capacitance for high circuit performance. The detailed process procedures of self-aligned BG ELC LTPS TFTs will be described and the self-aligned photo-lithography process will be presented and analyzed by optical microscopy (OM) and scanning electron microscopy (SEM) material analyses. The phenomenon of controlled lateral grain growth using bottom-gate structure on
quartz wafer is also investigated. Meanwhile, the electrical characteristics of SA BG ELC LTPS TFTs with two kinds of bottom-gate thickness of 1000 Å and 1500 Å were taken in into comparison. The symmetrical electrical characteristics can be observed in the SA BG ELC LTPS TFTs. Owing to the lateral grain growth and self-aligned structure, SA BG LTPS TFTs exhibit higher performance and better uniformity.
3.2 Experiments
3.2.1 Sample Preparation for Material Analysis
For further improving the bottom-gate LTPS-TFTs performances, we combined lateral grain growth controlled in the device channel region with the backside exposure photo-lithography. Figure 3-1 shows the process procedures for the preparation of self-aligned bottom-gate structure with large silicon grains by the excimer laser crystallization and the backside exposure. Since the self-aligned technique uses g-line light exposure from the back surface, the selection of appropriate substrate is important. Quartz wafer is used as the starting substrate for its high transparency ratio with g-line light wavelength of 436 nm and free from increase in temperature of the substrate. At first, after the RCA clean process, the 1000 Å-thick amorphous silicon layers were deposited by pyrolysis of pure silane (SiH4) with low pressure chemical vapor deposition (LPCVD) at 550 °C on quartz wafers. Next, a phosphorus ion implantation with a dosage of 5×1015 cm-2 was performed. Then, the phosphorus-doped amorphous silicon layer was defined to form bottom-gate electrode by transformer-coupled plasma reactive ion etching (TCP-RIE). After defining the bottom-gate region, the 1000 Å-thick tetraethyl orthosilicate (TEOS) gate oxide layer was deposited by plasma-enhanced chemical vapor deposition (PECVD) at 385 °C. Then, after standard RCA clean process, the
1000 Å-thick amorphous silicon (a-Si) layers were deposited by decomposition of pure silane (SiH4) with LPCVD at 550 °C. After standard RCA clean process, the a-Si thin films were then subjected to 248 nm KrF excimer laser crystallization (ELC). During the laser irradiation, the samples were located on a substrate in a vacuum chamber pumped down to 10-3 Torr and the substrate was maintained at room temperature. The laser beam was homogenized into a semi-gaussian shape in the short axis and a flat-top shape in the long axis. The number of laser shots per area was 20 (i.e. 95 % overlapping) and the laser energy density was varied.
Then, a self-aligned photolithography by using the bottom-gate as an opaque mask is performed to form self-aligned source/drain to gate by backside exposure through the quartz substrate. Then, a phosphorous ion implantation with dose of 5×1015cm-2 was carried out to form source and drain regions.
The relations between the resulting laser-crystallized poly-Si thin films with bottom-gate structure and laser process conditions were investigated by utilizing scanning electron microscopy (SEM) analysis and transmission electron microscopy (TEM) analysis techniques.
SEM was utilized to analyze the grain size and grain structure under different laser process conditions. In order to facilitate the SEM observation, some samples were processed by Secco-etch before analysis. TEM was employed to analyze the microstructure and crystallinity of poly-Si films and the completed device. The self-aligned bottom-gate photolithography was investigated by the optical microscopy (OM) and SEM analyses.
3.2.2 Fabrication of Self-Aligned (SA) BG LTPS TFTs using ELC
Figure 3-2 illustrates the key processes for the fabrication of SA BG LTPS TFTs by ELC with backside exposure. At first, after the RCA clean process, the 1000 Å-thick and 1500
Å-thick amorphous silicon layers were deposited by pyrolysis of pure silane (SiH4) with low pressure chemical vapor deposition (LPCVD) at 550 °C on quartz wafers. Next, a phosphorus ion implantation with a dosage of 5×1015 cm-2 was performed. Then, the phosphorus-doped amorphous silicon layer was defined to form bottom-gate electrode by transformer-coupled plasma reactive ion etching (TCP-RIE). After defining the bottom-gate region, the 1000 Å-thick tetraethyl orthosilicate (TEOS) gate oxide layer was deposited by plasma-enhanced chemical vapor deposition (PECVD) at 385 °C. Then, after standard RCA clean process, the 1000 Å-thick amorphous silicon (a-Si) layers were deposited by decomposition of pure silane (SiH4) with LPCVD at 550 °C. After standard RCA clean process, the a-Si thin films were then subjected to 248 nm KrF excimer laser crystallization (ELC), as shown in Figure 3-2 (b).
During the laser irradiation, the samples were located on a substrate in a vacuum chamber pumped down to 10-3 Torr and substrate was maintained at room temperature. The number of laser shots per area was 20 (i.e. 95% overlapping) and laser energy density was varied. Figure 3-2 (c) exhibited a self-aligned photolithography using the bottom-gate as an opaque mask to form self-aligned source/drain to gate by backside exposure through the quartz substrate [3.23]-[3.29], while for the non-self-aligned BG TFT, a front-side UV light exposure is used to defining the source/drain regions which result in the offset region. The offset length in non-self-aligned TFT is about 0.45 µm due to the process of masker aligner and the offset length can be further reduced by using the I-line stepper system. It is worth mentioning that the fabrication processes of new self-aligned TFTs and conventional non-self-aligned ones are almost the same, except the lithography process of defining the source/drain regions. Then, a phosphorous ion implantation with dose of 5×1015cm-2 was carried out to form source and drain regions. Then, the device active region was etched by reactive ion etching (RIE). Next, a 3000 Å-thick passivation oxide layer was deposited by at PECVD 385 °C and the implanted dopants were activated by thermal annealing at 600°C for 12 h in the N2 ambient. After
was deposited by thermal evaporation and Al metal pads were patterned to complete the fabrication of SA-BG LTPS TFTs as shown in Figure 3-2(d). Finally, a 30-min sintering process was performed at 400°C in the N2 ambient to reduce the contact series resistance of the source and drain electrodes. No hydrogenation plasma treatment was performed during the device fabrication process. For comparison, the conventional non-self-aligned ELC LTPS bottom-gate TFTs with a channel thickness of 1000Å were also fabricated.
Current-voltage (I-V) characteristics of the fabricated devices were measured using a semiconductor parameter analyzer of Agilent technologies 4156C. The threshold voltage was defined as the gate voltage required to achieve a normalized drain current of Ids = (W/L) x 10-8 A at Vds = 0.1 V. The field-effect mobility and subthreshold swing were extracted at Vds = 0.1 V, and the Ion/Ioff current ratio was defined at Vds = 3 V. An analytical transmission electron microscopy (TEM) (JEM-2100FX, JEOL Ltd.) was employed to analyze the microstructure and crystallinity of poly-Si film in the channel region and the completed SA-BG TFT device.
3.3 Results and Discussion
3.3.1 Material Characterization of SA-BG LTPS Thin Films
3.3.1.1 Optical Microscopy (OM) Analysis
Figure 3-3 (a) and 3-3 (b) shows the optical microscope (OM) images of the samples with bottom gate structure from the transparent light source. The thickness of the amorphous silicon gate electrode was both 1000Å and the channel length was 2 µm and 5 µm, respectively. At first, it was confirmed that the bottom-gate maintained its original structure after excimer laser crystallization. In addition, the bottom amorphous silicon gate is thick
(100 nm) enough to act as a mask for the formation of the self-aligned bottom gate structure by using the back surface exposure. According to those pictures, the regions above the amorphous silicon bottom-gate were dark but the other regions were bright in both cases. It could be found that the g-line light could not pass through the region sheltered by the amorphous silicon (a-Si) bottom-gate but could pass through other regions not covered by bottom-gate electrode. The g-line light was mostly absorbed and reflected by the amorphous silicon bottom-gate electrode. Hence, the thicker a-Si bottom gate, the less g-line light crossed the bottom-gate. Therefore, the a-Si bottom-gates with thickness of 1000 Å and 1500 Å could act as the opaque masks of the photo-lithography process to stop the ultra violate light from the Hg light source. Figure 3-4 (a) and 3-4 (b) shows OM images of the mis-aligned and the self-aligned ion-implanted devices after photo-lithography from the reflected light source, in which the channel length was 2 µm. Due to the process of masker aligner, there were horizontal shifts of photo-resist (P.R.) on the region of a-Si bottom-gate in defining the source/drain regions which result in the offset region after the photo-lithography, as shown in the Figure 3-4 (a). The horizontal shift was about 0.45 µm which would lead to the mis-aligned process of the ion implantation and degrade the device performance. Figure 3-4 (b) show a self-aligned photo-lithography by backside exposure method. It could be observed that a photo-resist pattern designed on the 100 nm-thick a-Si bottom-gate after the backside exposure photo-lithography, as shown in Figure 3-4 (b). The bottom gate pattern was copied for the photo-resist coating on the bottom-gate. Owing to the perfect self-aligned back surface exposure, the P.R. on the bottom-gate would not absorb UV light. Therefore, the P.R. would be remained and perfectly aligned to the bottom-gate after the develop process. Consequently, the self-aligned ion implantation of source and drain regions to gate would be precisely carried out without any shifts.
Figure 3-5 shows the SEM micrograph of the self-aligned ion-implanted devices after the photo-lithography. According to the SEM micrograph, the P.R. with thickness of 1.2 µm was observed and the P.R. was perfectly aligned to the a-Si bottom-gate electrode which was consistent with the results obtained by OM graphs. To sum up, the a-Si bottom-gate could act as the opaque mask of the photo-lithography process to stop the ultra violate light from the Hg light source and this method leaded to the easy formation of a self-aligned bottom-gate TFTs.
As a result, the P.R. aligned to the amorphous silicon gate would benefit the ion implantation of source and drain regions for the minimal series resistance.
Figure 3-6 (a) and 3-6 (b) display the SEM photographs of excimer laser crystallized poly-Si with bottom-gate structure after Secco etching, in which the thickness of bottom-gate
Figure 3-6 (a) and 3-6 (b) display the SEM photographs of excimer laser crystallized poly-Si with bottom-gate structure after Secco etching, in which the thickness of bottom-gate