Fabrication, Assembly and Characterization

The key component in present stacked 3D structure is the planar neural probe arrays, which were made with multiple bio-sensing sites for neural recording [82]. The fabrication steps of the planar array are displayed in Fig. 4.3 (A) and briefly described as follows: 250nm-thick nitride deposition on 200μm-thick silicon wafer for electrical isolation. Then, 300nm/30nm-thick Pt/Ti layer was deposited and patterned by lift-off for wire interconnects on the probe shaft, following with 500nm-thick nitride deposition for encapsulation.

Electrode sites and wire-bonding pads were defined by RIE. Then, 2μm-thick SiO2 was deposited by PECVD to protect the probe structure. Finally, shape of probe array was defined and released by DRIE. Fig. 4.3 (B)-(C) display the fabrication results of the planar arrays.

Another similar fabrication process which using polyimide (PI) and Cr/Au as isolation and conduction layer is also developed. The thickness of PI and Cr/Au are 3um and 1um, following with 3um-thick, electroformed Au as electrode site and bonding pad material. The Au layer is somewhat over-electroformed to ensure that the electrode was in contact with the neural tissue while implantation. Also, the final shape of the planar array was defined and released by DRIE.

When the stacking method is used to construct the 3-D neural probe arrays, the overflow adhesion gel or glue between the stacking layers may cover the proximate bonding pads and make them ineffective. Using less gel may reduce the overflow problem, but reduce the adherent strength. To solve the overflow problem of the gel, an anti-flow mechanism design was applied in the stacking method. The anti-overflow mechanism was accomplished by creating a through-silicon-via around the edges of the spacers. It uses capillary action force to prevent the gel from overflowing to the bonding pads. The mechanism functions in the following condition: when the stacking process starts, the combined parts compress the adhesion gel and force it to flow around. The flowing glue will fill the via by capillary action as it passes the via. Therefore, there is no redundant glue covering the proximate bonding pads.

Fig. 4.3 (A)Fabrication steps of the planar array (B) FabricatedProbe tip. The tapered tip angle is about 23° (C) Fabricated parts on a one cent coin (D) Tip and electrode The radius of the via was one of the major design parameter in preventing overflow. The formula is given by the well-known capillary action principle [83] with definition of the liquid-air surface tension, contact angle, density of the liquid, acceleration due to gravity, the height of the liquid column and the radius of the via. In this case, the maximal height of the liquid column is the thickness of the spacer (250 μm), and the liquid-air surface tension is 0.033 N/m [84], contact angle is 70° [85], density is 2,000 kg/m³ and gravity acceleration is 9.8 m/s². The capillary action principle gives the radius of the via a theoretical result of 4,600 μm, which was even larger than the size of the spacer. In fact, there is some limitations should be put into consideration. For instance, the limited volume of glue, the viscosity of glue, the friction force between glue-substrate interface and the capillary force in the narrow gap between two parts will make the liquid column never reach the expected height. The final via radius was experimentally set as 250 μm to enhance the filing of the via with glue.

After probe arrays are fabricated, a pre-designed PCB is utilized as the multichip neural interface structure substrate. To demonstrate the proposed stacked-multichip neural probe array, a conceptual realization is achieved by using the dummy chips bonded with the planar arrays by thermosetting gel (EA2151, LIONTONG Inc., TAIWAN) to realize the interface structure assembly. Convenient flip-chip technology was employed to accomplish alignment, pressurization and heating process, while the thermosetting gel provided adhesive layer between arrays and dummy chips. The thermosetting glue was solidified at 185°C in 180 seconds with an adhesive strength of 150-180 kg/cm3. The temperature is low enough to prevent the melt of Al wires in the CMOS chips during practical bonding in the future work.

The maximal placement accuracy of the flip-chip was 0.5 μm in a single bonding step. Thus, the total miss-alignment error can be neglected. Moreover, the average assembly time for a 4 × 4 3-D microprobe array by manual alignment was approximately 35 minutes (including heat curing time). In the present study, we applied about 0.26 μL of gel between spacers and arrays. The appropriate amount of the adhesion get combined the stacking well without spilling to the proximate pads.

Fig. 4.4 (A)–(G) illustrate how the anti-overflow mechanism functions in the practical assembly process. The details are displayed as follows: (A) the fabricated 2-D array (Arrayn) was fixed on the flip-chip holder (not shown). (B) A drop of thermosetting polymer was deposited onto the 2-D probe array and the spacer (Spacern) was picked by the flip-chip bonder head and aligned. (C) Start bonding – the aligned spacer was moved downward and controlled by the flip-chip bonder head. After the spacer came into contact with the glue drop, the drop spread in random directions because it was squeezed by the spacer. (D) The spacer was moved continuously downward, and the glue filled the via by capillary force when it flowed past the via. (E) The spacer came into contact with the 2-D array. The gel bump occurred on the top of the via because the pressure from bonding. (F) The flip-chip bonding head was removed. (G) The assembly process was completed following thermal solidification of the thermosetting glue. The gel bump over the via rapidly receded after heat curing.

Fig. 4.4 Proposed assembly anti-flow process and related practical photographs After wire-bonding, the wires were covered by epoxy, then, the whole device is covered by PDMS for the isolation from the implanted tissue except the probe shaft. Fig. 4.5 (A) shows the stacked 4-layer arrays with dummy chips (spacers). Note that each layer of planar array

was wire-bonded individually with different level of height. Fig. 4.5 (B) shows the packaged result of the assembled 3D neural interface structure on a one cent coin. The white connectors located on the backend of the packaged array were used for further recording experiments.

Fig. 4.5 (A) Stacked 4-layer probe array with dummy chips with wire-bonded individually in different level of height (B)Packaged 3D neural interface structure on one cent coin Electrode impedance spectroscopy (EIS) was used to evaluate the impedance performance of the electrode-electrolyte interface [86]. When the electrode sites come into contact with tissue, electrode-tissue interface impedance was established. High interface impedance will cause signal attenuation and induce considerable thermal noise while recording. Fig. 4.6 is the test result of impedance characterization of all the 64 electrodes in physiological saline solution, which is used to simulate the recording condition. Test result shows that the impedance is around 100kΩ at 1 kHz, which is around the neuron activity frequency range.

Fig. 4.6 Impedance characterization of fabricated 3D probe array