Chapter 5 Conclusions and Future Work
5.2 Future Work
There are some interesting topics that are valuable for the further future research on LTPS NILC TFTs:
(1) Nanocrystalline p‐n junction diodes have been fabricated by the NILC process for the solar cell devices [101]. However the preparation of the p‐n junction diode is limited. This is because Ni metal diffuses downward during crystallization and more Ni‐silicides therefore trapped at the interface of the p‐n junction. These Ni‐related defects lead a large leakage current and thus degrade the performance of the solar cell [102]. Therefore, Ni contamination inside the Ni‐metal mediated crystallized poly‐Si should be reduced. Our proposed Ni‐gettering method would effectively reduce Ni residue inside NILC poly‐Si and improve the electrical properties of the thin‐film and nanowire transistors. Hence, the proposed method could be a candidate to solve this issue.
(2) High‐performance poly‐Si nanowires (NWs) TFTs have been fabricated by nickel‐metal induced lateral crystallization (NILC). The cross‐section of the fabricated Si NWs is similar to the triangular shape. H. C. Lin et al even could fabricate Si NWs in the
square shape of the cross‐section. Therefore it is desired to investigate the effect of NW geometry on NILC rate for the fabrication of NILC poly‐Si NWs TFTs. Moreover much research has been done to clarify the basic NILC mechanism, none has been reported on its geometry dependence.
References
[1] J. Hanari, “Development of a 10.4‐in. UXGA display using low‐temperature poly‐Si technology,” Journal of the SID, 10, 53‐56 (2002)
[2] Y. Oana, “Current and future technology of low‐temperature poly‐Si TFT‐LCDs,” Journal of the SID, 9, 169‐172 (2001)
[3] K. Yoneda, H. Ogata, S. Yuda, K. Suzuki, T. Yamaji, S. Nakanishi, T. Yamada, and Y.
Morimoto, ”Optimization of low‐temperature poly‐Si TFT‐LCDs and a large‐scale production line for large glass substrates,” Journal of the SID, 9, 173‐180 (2001)
[4] Z. Meng, and M. Wong, “Active‐matrix organic light‐emitting diode displays realized using metal‐induced unilaterally crystallized polycrystalline silicon thin‐film transistors,” IEEE Trans. Electron Devices, 49, 991‐996 (2002)
[5] M. Stewart, R. S. Howell, L. Pires, and M. K. Hatalis, “Polysilicon TFT technology for active matrix OLED displays,” IEEE Trans. Electron Devices, 48, 845‐851 (2001)
[6] M. Kimura, I. Yudasaka, S. Kanbe, H. Kobayashi, H. Kiguchi, S.‐I. Seki, S. Miyashita, T.
Shimoda, T. Ozawa, K. Kitawada, T. Nakazawa, and H. Ohshima, “Low‐temperature polysilicon thin‐film transistor driving with integrated driver for high‐resolution light emitting polymer display,” IEEE Trans. Electron Devices, 46, 2282‐2288 (1999)
[7] Z. Meng, M. Wang, and M. Wong, “High performance low temperature metal‐induced unilaterally polycrystalline silicon thin film transistors for system‐on‐panel applications,”
IEEE Trans. Electron Device, 47, 404‐409 (2000)
[8] S.‐W. Lee, and S.‐K. Joo, “Low temperature poly‐Si thin‐film transistor fabrication by metal‐induced lateral crystallization,” IEEE Electron Device Lett., 17, 160‐162 (1996)
[9] H. Kim, J. G. Couillard, and D. G. Ast, “Kinetic of silicide‐induced crystallization of polycrystalline thin‐film transistors fabricated from amorphous chemical‐vapor deposition silicon,” Appl. Phys. Lett., 72, 803‐805 (1998)
[10] S.‐W. Lee, T.‐H. Ihn, and S.‐K. Joo, “Low‐temperature dopant activation and its application to polycrystalline silicon thin film transistors,” Appl. Phys. Lett., 69, 380‐382 (1996)
[11] S.‐W. Lee, T.‐H. Ihn, and S.‐K. Joo, “Fabrication of high‐mobility p‐channel poly‐Si thin film transistors by self‐aligned metal‐induced lateral crystallization,” IEEE Electron Device Lett., 17, 407‐409 (1996)
[12] Z. Jin, H. S. Kwok, and M. Wong, “Performance of thin‐film transistors with ultrathin Ni‐MILC polycrystalline silicon channel layers,” IEEE Electron Device Lett., 20, 167‐169 (1999)
[13] P. J. van der Zaag, M. A. Verheijen, S. Y. Yoon, and N. D. Young, “Explanation of the leakage current in polycrystalline‐silicon thin‐film transistors made by Ni‐silicide mediated crystallization,” Appl. Phys. Lett., 81, 3404‐3406 (2002)
[14] G. A. Bhat, Z. Jin, H. S. Kwok, and M. Wong, “Effects of longitudinal grain boundaries on the performance of MILC‐TFT’s,” IEEE Electron Device Lett., 20, 97‐99 (1999)
[15] G. A. Bhat, H. S. Kwok, and M. Wong, “Behavior of the drain leakage current in metal‐induced laterally crystallized thin film transistors,” Solid‐State Electron., 44, 1321‐1324 (2000)
[16] D. Murley, N. Young, M. Trainor, and D. McCulloch, “An investigation of laser annealed
and metal‐induced crystallized polycrystalline silicon thin‐film transistors,” IEEE Trans.
Electron Devices, 48, 1145‐1151 (2001)
[17] H. Gleskova, S. Wagner, V. Gašparík, and P. Kováč, “150oC amorphous silicon thin‐film transistor technology for polyimide substrates,” J. Electrochem. Soc., 148, G370‐G374 (2001)
[18] K. Long, A. Z. Kattamis, I.‐C. Cheng, H. Gleskova, S. Wagner, and J. C. Sturm, “Stability of amorphous‐silicon TFTs deposited on clear plastic substrates at 250oC to 280oC,” IEEE Electron Device Lett., 27, 111‐113 (2006)
[19] S.W. Depp, A. Juliana, and B. G. Huth, "Polysilicon FET devices for large area input/output applications," in Proc. IEMD, 703‐706 (1980)
[20] W. G. Hawkins, “Polycrystalline‐silicon device technology for large‐area electronics,” IEEE Trans. Electron Devices, 33, 477‐481 (1986)
[21] I‐W Wu, "Celldesign considerations for high‐aperture‐ratio direct‐view and projection polysilicon TFT‐LCD," in SID Tech. Dig., 19‐21 (1995)
[22] A. Mimura, N. Konishi, K. Ono, J.‐I. Ohwada, Y. Hosokawa, Y. A. Ono, T. Suzuki, K. Miyata, and H. Kawakami, “High‐performance low temperature poly‐Si n‐channel TFT’s for LCD,” IEEE Trans. Electron Devices, 36, 351‐359 (1989)
[23] V. Subramanian, P. Dankoski, L. Degertekin, B. T. Khuri‐Yakub, and K. C. Saraswat,
"Controlled two‐step solid‐phase crystallization for high‐performance polysilicon TFTs,"
IEEE Electron Device Lett., 18, 378‐381 (1997)
[24] N. Yamauchi, and R. Reif, “Polycrystalline silicon thin films processed with silicon ion implantation and subsequent solid‐phase crystallization: theory, experiments, and
thin‐film transistor applications,” J. Appl. Phys., 75, 3235‐3257 (1994)
[25] K. Zellama, P. Germain, S. Squelard, J. C. Bourgoin and P. A. Thomas, “Crystallization in amorphous silicon,” J. Appl. Phys., 50, 6995‐7000 (1979)
[26] A. T. Voutsas and M. K. Hatalis, "Deposition and crystallization of amorphous Si low‐pressure chemical vapor deposited films obtained by low‐temperature pyrolysis of disilane," J. Electrochem. Soc., 140, 871‐877 (1993)
[27] A. T. Voutsas and M. K. Hatalis, "Structural characteristics of as deposited and crystallized mixed‐phase silicon films," J. Electro. Mater., 23, 319‐330 (1994)
[28] M.‐K. Ryu, S.‐M. Hwang, T.‐H. Kim, K.‐B. Kim, and S.‐H. Min, “The effect of surface nucleation on the evolution of crystalline microstructure during solid phase crystallization of amorphous Si films on SiO2,” Appl. Phys. Lett., 71, 3063‐3065 (1997)
[29] I.‐W. Wu, A. Chiang, M. Fuse, L. Öveçoglu, and T. Y. Huang, “Retardation of nucleation rate for grain size enhancement by deep silicon ion implantation of low‐pressure chemical vapor deposited amorphous silicon films,” J. Appl. Phys., 65, 4036‐4039 (1989)
[30] C.‐W. Chang, “Enhanced performance and reliability for solid‐phase crystallized poly‐Si TFTs with argon ion implantation,” J. Electrochem. Soc., 154, J375‐J378 (2007)
[31] R. S. Wagner, and W. C. Ellis, “Vapor‐liquid‐solid mechanism of single crystal growth,”
Appl. Phys. Lett., 4, 89‐90 (1964)
[32] M. S. Haque, H. A. Naseem, and W. D. Brown, “Aluminum‐induced crystallization and counter‐doping of phosphorous‐doped hydrogenated amorphous silicon at low temperatures,” J. Appl. Phys., 79, 7529‐7536 (1996)
[33] L. Hultman, A. Robertsson, H. T. G. Hentzell, I. Engström, and P. A. Psaras, “Crystallization
of amorphous silicon during thin‐film gold reaction,” J. Appl. Phys., 62, 3647‐3655 (1987)
[34] S. F. Gong, H. T. G. Hentzell, and A. E. Robertsson, “Initial solid‐state reactions between Sb and amorphous Si thin films,” J. Appl. Phys., 64, 1457‐1463 (1988)
[35] S. Y. Yoon, K. H. Kim, C. O. Kim, J. Y. Oh, and J. Jang, “Low temperature metal induced crystallization of amorphous silicon using a Ni solution,” J. Appl. Phys., 82, 5865‐5867 (1997)
[36] Z. Jin, G. A. Bhat, M. Yeung, H. S. Kwok, and M. Wong, “Nickel induced crystallization of amorphous silicon thin films,” J. Appl. Phys., 84, 194‐200 (1998)
[37] E. A. Guliants, W. A. Anderson, L. P. Guo, V. V. Guliants, “Transmission electron microscopy study of Ni silicides formed during metal‐induced silicon growth,” Thin Solid Films, 385, 74‐80 (2001)
[38] C. Hayzelden, and J. L. Batstone, “Silicide formation and silicide‐mediated crystallization of nickel‐implanted amorphous silicon thin films,” J. Appl. Phys., 73, 8279‐8289 (1993)
[39] S.‐W. Lee, Y.‐C. Jeon, and S.‐K. Joo, “Pd induced lateral crystallization of amorphous Si thin films,” Appl. Phys. Lett., 66, 1671‐1673 (1995)
[40] S.‐W. Lee, B.‐I. Lee, T.‐K. Kim, and S.‐K. Joo, “Pd2Si‐assisted crystallization of amorphous silicon thin films at low temperature,” J. Appl. Phys., 85, 7180‐7184 (1999)
[41] J.L. Batstone, and C. Hayzelden, “Microscopic processes in crystallization,” Solid State Phenom., 37‐38, 257‐268 (1994)
[42] C. R. M. Grovenor, Microelectronic Materials, p. 224, Adam Hilger, Bristol (1989)
[43] K. N. Tu, and J. W. Mayer, in Thin films: interdiffusion and reactions, edited by J. M. Poate, K. N. Tu, and J. W. Mayer, p. 359, John Wiley & Sons, New York (1978)
[44] Y. Kuo, Thin film transistors: materials and processes, volume 2: polycrystalline silicon
[48] S. M. Myers, M. Seibt, and W. Schröter, “Mechanisms of transition‐metal gettering in silicon,” J. Appl. Phys., 88, 3795‐3819 (2000)
[49] S. M. Hu, Method of gettering using backside polycrystalline silicon, United States Patent No. 4053335 (1977)
[50] S. Martinuzzi, I. Perichaud, and J. J. Simon, “External gettering by aluminum‐silicon alloying observed from carrier recombination at dislocations in float zone silicon wafers,” Appl. Phys. Lett., 70, 2744‐2746 (1997)
[51] M. Apel, I. Hanke, R. Schindler, and W. Schröter, “Aluminum gettering of cobalt in silicon,” J. Appl. Phys., 76, 4432‐4433 (1994)
[52] S. V. Koveshnikov, and G. A. Rozgonyi, “Mechanism of iron gettering in MeV Si ion implanted epitaxial silicon,” J. Appl. Phys., 84, 3078‐3084 (1998)
[53] S. M. Myers, G. A. Petersen, and C. H. Seager, “Binding of cobalt and iron to cavities in silicon,” J. Appl. Phys., 80, 3717‐3726 (1996)
[54] M. Zhang, X. Zeng, P. K. Chu, R. Scholz, and C. Lin, “Nickel precipitation at nanocavities in separation by implantation of oxygen,” J. Vac. Sci. Technol. A, 18, 2249‐2253 (2000)
[55] B. Mohadjeri, J. S. Williams, and J. W. Leung, “Gettering of nickel to cavities in silicon introduced by hydrogen implantation,” Appl. Phys. Lett., 66, 1889‐1891 (1995)
[56] A. Cacciato, C. M. Camalleri, G. Franco, V. Raineri, and S. Coffa, “Efficiency and thermal stability of Pt gettering in crystalline Si,” J. Appl. Phys., 80, 4322‐4327 (1996)
[57] F. Schiettekatte, C. Wintgens, and S. Roorda, “Influence of curvature on impurity gettering by nanocavities in Si,” Appl. Phys. Lett., 74, 1857‐1859 (1999)
[58] S. M. Myers, and G. A. Petersen, “Transport and reactions of gold in silicon containing cavities,” Phys. Rev. B, 57, 7015‐7026 (1998)
[59] S. M. Myers, and D. M. Follstaedt, “Interaction of copper with cavities in silicon,” J. Appl.
Phys., 79, 1337‐1350 (1996)
[60] M. Zhang, C. Lin, X. Duo, Z. Lin, and Z. Zhou, “Comparison of Cu gettering to H+ and He+ implantation‐induced cavities in separation‐by‐implantation‐of‐oxygen wafers,” J. Appl.
Phys., 85, 94‐98 (1999)
[61] D. Gilles, W. Schröter, and W. Bergholz, “Impact of electronic structure on the solubility and diffusion of 3d transition elements in silicon,” Phys. Rev. B, 41, 5770‐5782 (1990)
[62] J. L. Benton, P. A. Stolk, D. J. Eaglesham, D. C. Jacobson, J.‐Y. Cheng, N. T. Ha, T. E. Haynes, and S. M. Myers, “Iron gettering mechanisms in silicon,” J. Appl. Phys., 80, 3275‐3284 (1996)
[63] A. Ourmazd, and W. Schröter, “Phosphorous gettering and intrinsic gettering of nickel in silicon,” Appl. Phys. Lett., 45, 781‐783 (1984)
[64] A. Correia, B. Pichaud, A. Lhorte, and J. B. Quoirin, “Platinum gettering in silicon by silicon phosphide precipitates,” J. Appl. Phys., 79, 2145‐2147 (1996)
[65] C.‐Y. Hou, and Y. S. Wu, “A simple method for gettering of nickel within the Ni‐metal‐induced lateral crystallization polycrystalline silicon film,” Electrochem.
Solid‐State Lett., 9, H65‐H67 (2006)
[66] B.‐M. Wang, and Y. S. Wu, “Gettering of Ni from nickel‐induced lateral crystallization silicon using amorphous silicon and chemical oxide,” Electrochem. Solid‐State Lett., 12, J14‐J16 (2009)
[67] B.‐M. Wang, and Y. S. Wu, “Improved gettering efficiency of Ni from nickel‐mediated crystallization silicon using phosphorus‐doped amorphous silicon,” J. Electro. Mater., 38, 767‐771 (2009)
[68] C.‐M. Hu, and Y. S. Wu, “Gettering of nickel within the Ni‐metal induced lateral crystallization polycrystalline silicon film through the contact holes,” Jpn. J. Appl. Phys., 46, L1188‐L1190 (2007)
[69] C.‐M. Hu, Y. S. Wu, and C.‐C. Lin, “Improving the electrical properties of NILC poly‐Si films using a gettering substrate,” IEEE Electron Device Lett., 28, 1000‐1003 (2007)
[70] M. Im, J.‐W. Han, H. Lee, L.‐E. Yu, S. Kim, C.‐H. Kim, S. C. Jeon, K. H. Kim, G. S. Lee, J. S. Oh, Y. C. Park, H. M. Lee, and Y.‐K. Choi, “Multiple‐gate CMOS thin‐film transistor with polysilicon nanowire,” IEEE Electron Device Lett., 29, 102‐105 (2008)
[71] T.‐C. Liao, S.‐W. Tu, M. H. Yu, W.‐K. Lin, C.‐C. Liu, K.‐J. Chang, Y.‐H. Tai, and H.‐C. Cheng,
“Novel gate‐all‐around poly‐Si TFTs with multiple nanowire channels,” IEEE Electron Device Lett., 29, 889‐891 (2008)
[72] X. Duan, Y. Huang, and C. M. Lieber, “Nonvolatile memory and programmable logic from molecule‐gated nanowires,” Nano Lett., 2, 487‐490 (2002)
[73] X. Duan, C. Niu, V. Sahi, J. Chen, J. W. Parce, S. Empedocles, and J. L. Goldman,
“High‐performance thin‐film transistors using semiconductor nanowires and nanoribbons,” Nature, 425, 274‐278 (2003) PtSi source/drain and electrical junctions,” IEEE Electron Device Lett., 24, 102‐104 (2003)
[77] H. L. Chen, C. H. Chen, F. H. Ko, T. C. Chu, C. T. Pan, and H. C. Lin, “Thermal‐flow techniques for sub‐35 nm contact‐hole fabrication in electron‐beam lithography,” J. Vac.
Sci. Technol. B, 20, 2973‐2978 (2002)
[78] F.‐H. Ko, H.‐C. You, T.‐C. Chu, T.‐F. Lei, C.‐C. Hsu, and H.‐L. Chen, “Fabrication of sub‐60‐nm contact holes in silicon dioxide layers,” Microelectronic Engineering, 73‐74, 323‐329 (2004)
[79] Y.‐K. Choi, J. Zhu, J. Grunes, J. Bokor, and G. A. Somorjai, “Fabrication of sub‐10‐nm silicon nanowire arrays by size reduction lithography,” J. Phys. Chem. B, 107, 3340‐3343 (2003)
[80] X. Duan, Y. Huang, Y. Cui, J. Wang, and C. M. Lieber, “Indium phosphide nanowires as
building blocks for nanoscale electronic and optoelectronic devices,” Nature, 409, 66‐69 (2001)
[81] Y. Huang, X. Duan, Q. Wei, and C. M. Lieber, “Directed assembly of one‐dimensional nanostructures into functional networks,” Science, 291, 630‐633 (2001)
[82] A. Tao, F. Kim, C. Hess, J. Goldberger, R. He, Y. Sun, Y. Xia, and P. Yang, “Langmuir‐blodgett silver nanowire monolayers for molecular sensing using surface‐enhanced raman spectroscopy,” Nano Lett., 3, 1229‐1233 (2003)
[83] A. M. Morales, and C. M. Lieber, “A laser ablation method for the synthesis of crystalline semiconductor nanowires,” Science, 279, 208‐211 (1998)
[84] D. Wang, Q. Wang, A. Javey, R. Tu, H. Dai, H. Kim, P. C. McIntyre, T. Krishnamohan, and K.
C. Saraswat, “Germanium nanowire field‐effect transistors with SiO2 and high‐k HfO2 gate dielectrics,” Appl. Phys. Lett., 83, 2432‐2434 (2003)
[85] N. Wang, Y. F. Zhang, Y. H. Tang, C. S. Lee, and S. T. Lee, “SiO2‐enhanced synthesis of Si nanowires by laser ablation,” Appl. Phys. Lett., 73, 3902‐3904 (1998)
[86] C.‐J. Su, H.‐C. Lin, and T.‐Y. Huang, “High‐performance TFTs with Si nanowire channels enhanced by metal‐induced lateral crystallization,” IEEE Electron Device Lett., 27, 582‐584 (2006)
[87] H.‐C. Lin, M.‐H. Lee, C.‐J. Su, T.‐Y. Huang, C. C. Lee, and Y.‐S. Yang, “A simple and low‐cost method to fabricate TFTs with poly‐Si nanowire channel,” IEEE Electron Device Lett., 26, 643‐645 (2005)
[88] H.‐C. Lin, M.‐H. Lee, C.‐J. Su, and S.‐W. Shen, “Fabrication and characterization of nanowire transistors with solid‐phase crystallized poly‐Si channels,” IEEE Trans. Electron
Devices, 53, 2471‐2477 (2006)
[89] S. Zhao, Z. Meng, X. Li, B. Zhang, Z. Liu, M. Wong, and H.‐S. Kwok, “Metal induced continuous zonal domain polycrystalline silicon and thin film transistors,” in SID Tech.
Dig., 233‐236 (2007)
[90] F. S. d' Aragona, “Dislocation etch for (100) planes in silicon,” J. Electrochem. Soc., 119, 948‐951 (1972)
[91] T. Ma, and M. Wong, “Dopant and thickness dependence of metal‐induced lateral crystallization of amorphous silicon films,” J. Appl. Phys., 91, 1236‐1241 (2002)
[92] I. H. Song, C. H. Kim, S. H. Kang, W, J. Nam, and M. K. Han, “A new multi‐channel dual‐gate poly‐Si TFT employing excimer laser annealing recrystallization on pre‐patterned α‐Si thin film,” in Proc. IEMD, 561‐564 (2002)
[93] T.‐K. Kim, T.‐H. Ihn, B.‐I. Lee, and S.‐K. Joo, “High‐performance low‐temperature poly‐silicon thin film transistors fabricated by new metal‐induced lateral crystallization process,” Jpn. J. Appl. Phys., 37, 4244‐4247 (1998)
[94] K. R. Olasupo, and M. K. Hatalis, “Leakage current mechanism in sub‐micron polysilicon thin‐film transistors,” IEEE Trans. Electron Devices, 43, 1218‐1223 (1996)
[95] M. Yazaki, S. Takenaka, and H. Ohshima, “Conduction mechanism of leakage current observed in metal‐oxide‐semiconductor transistors and poly‐Si thin‐film transistors,” Jpn.
J. Appl. Phys., 31, 206‐209 (1992)
[96] Y. Lee, S. Bae, and S. J. Fonash, “High‐performance nonhydrogenated nickel‐induced laterally crystallized p‐channel poly‐Si TFTs,” IEEE Electron Device Lett., 26, 900‐902 (2005)
[97] C.‐W. Chang, S.‐F. Chen, C.‐L. Chang, C.‐K. Deng, J.‐J. Huang, and T.‐F. Lei,
“High‐performance nanowire TFTs with metal‐induced lateral crystallized poly‐Si channels,” IEEE Electron Device Lett., 29, 474‐476 (2008)
[98] J. Gu, S. Y. Chou, N. Yao, H. Zandbergen, and J. K. Farrer, “Single‐crystal Si formed on amorphous substrate at low temperature by nanopatterning and nickel‐induced lateral crystallization,” Appl. Phys. Lett., 81, 1104‐1106 (2002)
[99] T.‐E. Chang, C. Huang, and T. Wang, “Mechanisms of interface trap‐induced drain leakage current in off‐state n‐MOSFET’s,” IEEE Trans. Electron Devices, 42, 738‐743 (1995)
[100] R. E. Proano, R. S. Misage, and D. G. Ast, “Development and electrical properties of undoped polycrystalline silicon thin‐film transistors,” IEEE Trans. Electron Devices, 36, 1915‐1922 (1989)
[101] J. D. Hwang, and K. S. Lee, “A high rectification ratio nanocrystalline p‐n junction diode prepared by metal‐induced lateral crystallization for solar cell applications,” J.
Electrochem. Soc., 155, H259‐H262 (2008)
[102] J. R. Davis, A. Rohatgi, R. H. Hopkins, P. D. Blais, P. R. Choudhury, J. R. Mccormick, and H.
C. Mollenkopf, “Impurities in silicon solar cells,” IEEE Trans. Electron Devices, 27, 677‐687 (1980)
Vita
Bau-Ming Wang
Birth Date: Jan. 21, 1978 Sex: Male
Email: [email protected] Mobile‐phone: 0988314121
Address: 10F‐3, No.31, Juejiang St., Yancheng Dist., Kaohsiung, Taiwan 803
Education:
National Chiao Tung University, Hsinchu, Taiwan
Ph.D. of Science in Materials Science and Engineering Sep. 2003 – Jan. 2010
Major Field: Materials Science & Semiconductor Device Physics / VLSI Microfabrication.
Ph.D.’s Thesis: Improved Performance of NILC LTPS Thin‐Film & Nanowire Transistors through Ni‐Gettering.
Master of Science in Materials Science and Engineering Sep. 2001 ‐ Jul. 2003 Master’s Thesis: Formation and Characterization of Self‐Assembly Monolayer on Silicon
Substrate.
Bachelor of Science in Materials Science and Engineering Sep. 1997 ‐ Jun. 2001
Publication List
Journal Paper:
1. Bau‐Ming Wang, and YewChung Sermon Wu, “Gettering of Ni from nickel‐induced lateral crystallization silicon using amorphous silicon and chemical oxide,” Electrochem.
Solid‐State Lett., 12, J14‐J16 (2009)
2. Bau‐Ming Wang, and YewChung Sermon Wu, “Improved gettering efficiency of Ni from nickel‐mediated crystallization silicon using phosphorus‐doped amorphous silicon,” J.
Electro. Mater., 38, 767‐771 (2009)
3. Bau‐Ming Wang, and YewChung Sermon Wu, “Using phosphorus‐doped α‐Si gettering layer to improve NILC poly‐Si TFT performance,” J. Electro. Mater., 39, 157‐161 (2010) 4. Bau‐Ming Wang, Tzu‐Ming Yang, YewChung Sermon Wu, Chun‐Jung Su, and Horng‐Chih
Lin, “Effect of Ni residues on the performance and the uniformity of NILC poly‐Si nanowire TFTs,” Submitted to Mater. Chem. Phys.
5. 王寶明和吳耀銓, “利用磷布植非晶矽捉聚鎳金屬誘發結晶矽之殘留鎳金屬,” 奈米電
子元件技術專文,11 月號第 5 期, 1‐7 (2009) Conference Paper:
1. Bau‐Ming Wang, Bau‐Tong Dai, Ming‐Shih Tsai, and George C. Tu, “Electrochemical Characterization on Packing Density of Alkylchlorosilane Monolayer,” 205th ECS Meeting, San Antonio, Texas, US, May 9‐13 (2004) (Oral paper)
2. Bau‐Ming Wang, Tzu‐Ming. Yang, Ching‐Chieh Tseng, and YewChung Sermon Wu, “Using Chemical Oxide Layer to Getter Nickel inside Nickel‐Metal‐Induced Lateral Crystallization Polycrystalline Silicon,” 214th ECS Meeting, Honolulu, Hawaii, US, October 12‐17 (2008) (Oral paper)
3. Bau‐Ming Wang, YewChung Sermon Wu, Mei‐Yi Li, Tzu‐Ming. Yang, His‐Hao Huang, and Wang‐Shen Su, “Ni‐Gettering from Nickel‐Mediated Crystallization Silicon by Using Phosphorus‐Doped Amorphous Silicon,” in Symposium On Nano Device Technology