2. Introduction of Measurement and Simulation Tools
2.3 HFSS Introduction
2.3.2 HFSS Solution Process
The Solution Type defines the type of results, how the excitations are defined, and the convergence. Solution Types available are:
1. Driven Modal - calculates the modal-based S-parameters.
2. Driven Terminal - calculates the terminal-based S-parameters of multiconductor transmission line ports.
3. Eigenmode – calculate the eigenmodes, or resonances, of a structure.
The solution type used in this work is mostly Driven Modal and Driven Terminal, which the S-parameter of Inductor and Capacitor can be created easily after the simulation.
Figure 2.6 Solution Type Window
2.3.3 Boundary Condition
Boundary conditions enable you to control the characteristics of planes, face, or interfaces between objects. As a user of Ansoft HFSS you should be aware of the field assumptions made by boundary conditions.
Since boundary conditions force a field behavior we want to be aware of the assumptions so we can determine if they are appropriate for the simulation. Improper use of boundary conditions may lead to inconsistent results.
When used properly, boundary conditions can be successfully utilized to reduce the model complexity. In fact, Ansoft HFSS automatically uses boundary conditions to reduce the complexity of the model. Ansoft HFSS can be thought of as a virtual prototyping world for passive RF devices. Unlike the real world which is bounded by infinite space, the virtual prototyping world needs to be made finite. In order to achieve this finite space, Ansoft HFSS applies a background or outer boundary condition which is applied to the region surrounding the geometric model.
There are three types of boundary conditions.
1. Excitations
z Wave Ports (External) z Lumped Ports (Internal) 2. Surface Approximations
z Symmetry Planes
z Perfect Electric or Magnetic Surfaces z Radiation Surfaces
z Background or Outer Surface 3. Material Properties
z Boundary between two dielectrics z Finite Conductivity of a conductor
The background is the region that surrounds the geometric model and fills any space that is not occupied by an object. Any object surface that touches the background is automatically defined to be a perfect E boundary and given the boundary name outer.
Chapter 3 Experiment Sample and Environment
3.1 Sample and Measurement Preparation
In this thesis, inductor and capacitor were made by 0.25μm process technology as shown in Figure 3.1. Before and after packaging sample is shown in Figure 3.2 and 3.3 respectively. This component were measured using cascade microwave RF probe station using Vector Network Analyzer (VNA), as shown in Figure 3.4. The system consist of Cascade microwave RF probes station, Agilent 8364B network analyzer, and a computer with ADS (Advance Design System) software by Agilent. The network analyzer and microwave probes are connected by high-frequency cables. The measurement data are transferred from the network analyzer to a computer via the HP-IB bus. In this measurement, 500-μm pitch RF probe as shown in Figure 3.5, made by Cascade Microtech, is used to perform measurement. 2-ports S-parameters measurements were performed from 10 MHz to 12 GHz. In order to remove errors caused by the measurement
standard Short-Open-Load-Thru (SOLT) calibration is done.
Figure 3.1 Inductor and Capacitor layout
Figure 3.2 Microphotograph of an integrated spiral inductor and a MIM capacitor before packaging.
Figure 3.3 Top view and bottom view of spiral inductor and MIM capacitor after packaging of flip-chip BGA.
(a) (b)
(a) (b)
(a)
(b)
Figure 3.4 (a) Agilent 8364B network analyzer setup and (b) Experiment environment
Agilent 8364B network analyzer
High Frequency Cable
Figure 3.5 a 500-μm pitch RF probe made by Cascade Microtech
3.2 Packaging Substrate
Embedded passives manufacture using multi-layer substrate by etching and printing method. Packaging substrate issue must be checked for integrated passives device. In common, there are two kinds of substrate, one is known as Build-up substrate, the other is knows as laminated substrate. Figure 3.6 shows the build-up substrate structure, which core is made by a rigid material such as glass, BT resin, silicon, or plastic. Figure 3.7 shows the laminated substrate structure, which core is made by FR4, an organic substrate is laminated with heat and pressure.
In this work, a double layer shown in Figure 3.8 substrate will be used as the test vehicle which is finished BGA with a chip attached on it.
Substrate alone simulation will be shown in this chapter before passive devices mounted on it.
In this work, a double layer shown in Figure 3.8 substrate will be used as the test vehicle which is finished BGA with a chip attached on it.
Substrate alone simulation will be shown in this chapter before passive devices mounted on it.
Figure 3.6 Build-up substrate structure
(a) (b)
Figure 3.7 Laminate Substrate Structure (a) 2 layer laminated substrate (b) before and after lamination
Figure 3.8 cross-section of finished Flip-Chip BGA substrate
Di D ie e So S ol ld de er r B Bu um mp p
Un U nd de er rf f il i ll l
Su S ub bs st tr ra at te e
So S ol ld de er r B Ba al ll l
Measurement of substrate alone is not easy to obtain because the bump is too small and the requirement of “up and down” probing issue.
Thus a simulation is used to find the effect of the substrate. Figure 3.9 shown the packaging substrate modeled by using Ansoft HFSS, Table 3.1 is the material parameter used in substrate simulation.
Figure 3.9 package substrate 3-D models
Table 3.1 Substrate material data
Material Er Loss tangent
BT resin 3.8 0.0015
Soldermask 3.9 0.0015
The substrate model is simplified as shown in Figure 3.10 to find the s-parameter of one substrate via. Simulation result is shown in Figure 3.11.
Figure 3.10 Simplified substrate model
0 2 4 6 8 10 12 14
-60 -50 -40 -30 -20 -10 0
S-parameter (dB)
Frequency (GHz)
S11(dB) S21(dB)
Figure 3.11 Substrate S-parameters
After the simulation is done, the result is imported into ADS, as shown in Figure 3.12 which is the model of integrated passives after packaging. Part A and C is the substrate via and part B is the passive device. ADS simulation result shown that the simulation result of the model is fitted to the measurement data, which prove the substrate simulation is true.
S2P
Figure 3.12 Model of integrated passives after packaging in ADS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Chapter 4 Experiment Study
4.1 Measurement Result
Embedded MIM capacitor and inductor before and after packaging has been measured. Figure 4.1 show the measurement result for capacitor before and after packaging and Figure 4.2 show the measurement result for inductor before and after packaging. Measured device characteristics and simulated passive devices will be shown and compared to the measurement result.
0 2 4 6 8 10 12
Figure 4.1 Measured S-parameter of Embedded Capacitor before and after packaging (a) Return Loss (b) Transmission Loss
0 2 4 6 8 10 12
Figure 4.2 Measured S-parameter of Embedded Inductor before and after packaging (a) Return Loss (b) Transmission Loss
4.2 Simulation Result
Simulation work is done with High Frequency Structure Simulator (HFSS) by Ansoft. First, we must set up the passives structure, which is drawn 2D using AUTOCAD as shown in Figure 4.3. This study will focus on Ca1 and In1 on the test chip, which is circle on the figure. The next step is to separate each layer of the layout, after that, it is imported into HFSS; by using HFSS, we can sweep 2-D model into 3-D model as shown in Figure 4.6. To build a 3-D model we need to know the thickness of each layer as shown in Fig 4.5. Relative permittivity of the material of the material is also shown in the same figure.
Figure 4.3 Test Chip Layout
Table 4.1 Embedded Passive Value
Inductor 7.08 nH
Capacitor 0.485 pF
Figure 4.4 Ca and Inductor on test chip
Figure 4.5 Layer dimension of test chip
Figure 4.6 Structure is sweep into 3-D using HFSS
4.2.1 Simulation of Capacitor
In this section, the simulation result will be shown. The result of Simulation will be compared with the measurement data, which is s-parameter, phase, smith chart, Q-factor, E-field and H-field.
The measurement result of embedded MIM capacitor in comparison with simulated data was shown. Below is figure of models before and after packaging are the measured and simulated values of S11 and S21 before and after packaging. Related phase and smith chart are also shown to compare the RF characteristic for capacitor before and after packaging. In this work, the measurement and simulation data with packaging effect is fit well and reasonable.
Figure 4.7 Capacitor model before Packaging
0 2 4 6 8 10 12 14
0 2 4 6 8 10 12 14
Figure 4.9 Phase of Capacitor before Packaging
freq (10.00MHz to 12.00GHz)
measurement..S(1,1)S(1,1)
freq (10.00MHz to 12.00GHz)
measurement..S(2,1)S(2,1)
0 2 4 6 8 10 12 14
Figure 4.11 Quality factor of Capacitor before Packaging
.
Figure 4.12 E-Field and H-Field of Capacitor before Packaging (Last Adaptive Freq = 6GHz)
Later, we will see the result of capacitor after packaging. The model is shown in Figure 4.17. The result is shown below
Figure 4.13 Model of Capacitor after Packaging
0 2 4 6 8 10 12 14
Figure 4.14 Return loss and Insertion Loss of Capacitor after
0 2 4 6 8 10 12 14
Figure 4.15 Phase of Capacitor after Packaging
freq (10.00MHz to 12.00GHz)
S(1,1)simulation..S(1,1)
freq (10.00MHz to 12.00GHz)
S(2,1)simulation..S(2,1)
Figure 4.17 E-Field and H-Field of Capacitor after Packaging (Last Adaptive Freq = 1GHz)
4.2.2 Simulation of Inductor
The measurement result of embedded spiral Inductor in comparison with simulated data was shown. Below is figure of models before and after packaging are the measured and simulated values of S11 and S21 before and after packaging. Related phase and smith chart are also shown to compare the RF characteristic for inductor before and after packaging.
In this work, the measurement and simulation data with packaging effect is fit well and reasonable.
4.18 Model of Embedded Spiral Inductor before Packaging
0 2 4 6 8 10 12 14
0 2 4 6 8 10 12 14
Figure 4.20 Phase of Inductor before Packaging
freq (10.00MHz to 12.00GHz)
S(1,1)simulation..S(1,1)
freq (10.00MHz to 12.00GHz)
S(1,2)simulation..S(1,2)
Figure 4.21 Smith Chart of Inductor before Packaging
0 2 4 6 8 10 12 14 -4
-2 0 2 4 6 8
Q
Frequency(GHz)
Before Package-Measure Before Package-Simulate Before Package-HFSS
Figure 4.22 Quality factor of Inductor before Packaging
Figure 4.23 E-Field and H-Field of Inductor before Packaging
4.24 Model of Embedded Spiral Inductor after Packaging
0 2 4 6 8 10 12 14
Figure 4.25 Return loss and Insertion Loss of Inductor after
0 2 4 6 8 10 12 14
Figure 4.26 Phase of Inductor after Packaging
Figure 4.27 Smith Chart of Inductor after Packaging
freq (10.00MHz to 12.00GHz)
S(1,1)Simulation..S(1,1)
Freq=1GHz
Figure 4.28 E-Field and H-Field of Inductor after Packaging
Chapter 5 Conclusions
The focus of this thesis is the measurement and simulation of integrated passive devices (capacitor and inductor) before and after packaging. Passive components (Resistors, Capacitors, and Inductors) occupy a large area of the electronic circuit boards, and the number is increasing, these are a major hurdle to the miniaturization of many electronic systems. Analog and mixed-signal applications, which use a large number of passives than typical digital system, almost no through-hole, axial leaded resistors and disk capacitors are used anymore;
they have been replaced with smaller, rectangular surface-mount components with solder joints at both ends. The size of these modern discrete is described by a number such as 0603, which indicates a size of 60 × 30 mils (1.5 × 0.75 mm). The 0402 (1.0 × 0.5 mm) size is commonly used, and the smallest discrete passives today are 0201 (0.50 × 0.25 mm).
Part on of the thesis presented the Introduction of Integrated Passive devices, Device structure and theory is also discussed. In the second part, Ansoft HFSS is introduced as we used this software for doing simulation
Measurement and simulation result is shown in the last part, and they are quiet fit.
5.1 Future Research
Integrated Passive Devices have all benefits we want for future Integrated Circuit, as describe in the first chapter, but there are many problems with implementing integrated passives, such as:
1. Indecision on materials and processes. Research continues on many resistor materials and capacitor dielectrics.
2. Lack of design tools, for both component sizing and system layout.
3. Requires vertical integration. The same company must manufacture both substrates and passives.
4. Yield issues. One bad component can lead to scrapping the entire board.
5. Tolerance issues. Integrated passives cannot be presorted prior to inclusion on the board.
6. Lack of standardization. The various segments of the integrated passive industry aren’t speaking the same language [14].
7. Surface-mount technology is improving—moving towards 01005.
8. Lack of costing models. It is not easy to tell when integrated passives might be more cost effective.
Table 5.1 Issues and status of integrated components
Over one trillion passive devices mounted on organic boards this year, this number will increase rapidly in the future, Integrated Passive devices will provide a great benefit if all the problem mention above can be solve.
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