被動元件於模組化構裝之高頻量測模擬技術研究

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(1)國立高雄大學電機工程學系 (研究所-先進電子構裝組) 碩士論文. 被動元件於模組化構裝之高頻量測模擬技術研究 Measurement, Analysis, and Simulation of High Frequency Embedded Passive Devices Before and After Packaging. 研究生：陶恩路指導教授：葉文冠. 中華民國九十六年六月.

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(3) 被動元件於模組化構裝之高頻量測模擬技術研究指導教授：葉文冠博士（教授）國立高雄大學電機工程研究所. 學生：陶恩路國立高雄大學電機工程研究所摘要. 隨著電子產品操作頻率與速度提升及產品體積越來越小之要求，系統電路上被動元件(電阻，電容，電感)所佔的面積、數目及功能需求越來越增加及多樣化，如此將限制電子產品朝輕、薄、短小發展之趨勢，內藏式被動元件(Embedded passive components)提供了一可行之解決辦法。被動元件內藏，為將元件埋入基板內層，省下電路板表面面積以增加訊號線路佈線之自由度，並由於元件內藏後減少元件表面黏著時所需連接線路之電路寄生效應，提升了元件純度及可靠度，有效降低成本。本論文研究著重在封裝前以及封裝後的內埋式被動元件之量測以及模擬。一整合式晶片包含不同結構圈數之電容電感將被製造，且針對此一元件結構量測與模擬相關電性參數，提供有效且準確之內埋元件特性及其最佳化線路模型。. 關鍵字：內埋式被動元件、整合式被動元件、電容、電感、HFSS. iii.

(4) Measurement, Analysis, and Simulation of High Frequency Embedded Passive Devices Before and After Packaging Advisor: Dr.(Professor) Wen-Kuan Yeh Institute of Electrical Engineering National University of Kaohsiung Student: Endruw Jahja Institute of Electrical Engineering National University of Kaohsiung ABSTRACT The demand to archive electronic products operation frequency and speed increase, and size reduction, passive component (Resistor, Capacitor, and Inductor) occupy a large area of the electronic circuit boards, the number and functionality is also increased and varied, they become a hurdle to the miniaturization of many electronic systems. Embedded passives devices provide a practical solution for microelectronics miniaturization. Embedded passive, to place the passive component in to the inner layer of the substrate, embedded passives can reduce the system real estate and eliminate the need for discrete components, thus enhancing electrical performance as well as reliability, and reducing the overall cost In this thesis, embedded passive before and after packaging measurement data and simulation work will be shown. Integrated chip that include different circle number spiral inductor and MIM capacitor have been manufactured, and in this work will be aimed on one component structure, measurement and simulation to obtain electrical parameter, providing effective and accurate embedded passive component characteristic and optimization circuit model.. Keywords: embedded passives, Integrated Passive Device, capacitor, inductor, HFSS. iv.

(5) 誌謝在研究所兩年的日子中，從考上研究所開始到本論文的完成，ㄧ路走來感觸良多，在這條路上真的要感謝非常多的人，感謝指導教授葉文冠博士以及吳松茂博士在研究工作上的指導下，給予最大的支持與協助得以順利完成，這當中給予我許多的參考方向，讓我能夠ㄧ步ㄧ步完成論文的每ㄧ個環節。其次，也感謝實驗室裡的同學彥志，家維，韶華，還有學弟振安，啟彰，玄德對我各方面的幫助，並給實驗室帶來活力與朝氣，願大家都能順利朝著每個人預定的目標前進。最後要感謝的是我的家人，能在這兩年的時間不斷的支持鼓勵，讓我無後顧之憂，僅將此論文獻給你們，並與你們分享這喜悅，並在此感謝所有幫助過我，支持我的人。. 2007年6月. v.

(6) 目錄 1 IPD Introduction….………………………………………………….….……….…..1 1.1 Integrated Passive Device…………………………………...…….…..…......1 1.1.1 Device Structure……………………………………………………....6 1.1.2 Fabrication Flow……………………………………………...……….7 1.2 Passives Theory………………………………………………..……...……...8 1.2.1 Resistor……………………………………………….……….……....8 1.2.2 Capacitors………...……………………………….………...……….11 1.2.2.1 Decoupling Capacitance……………………..………….…....15 1.2.3 Inductor………...………………………...…..…………..….………16 1.4 Integrated Passive Devices for RF application…………………….……….21 2. Introduction of Measurement and Simulation Tools…………………………........24 2.1 Vector Network Analyzer……………………….………………….…….....24 2.1.1 Full Two Port Calibration………………………………………....…27 2.2 Finite Element Method (FEM)………………………………………….…..28 2.3HFSS Introduction……………………………………..……….…..…….....29 2.3.1 Design Flow………………………………………………..….…….31 2.3.2 HFSS Solution Process ……………………………………………..33 3.3.3 Boundary Condition…………………………………………………34 3. Experiment Sample and Environment…………………….…….…………...........36 3.1 Sample and Measurement Preparation……………………………………..36 3.2 Package Substrate…………………………………………………………..41 4. Experimental Study………………………………….……….…............................47 4.1 Measurement Result……………………….……….….................................47 4.2 Simulation Result……………………….…………….….............................50 4.2.1 Simulation of Capacitor………………………………..……………54 4.2.2 Simulation of Inductor………………………………………………66 5. Conclusions………………………………………………………………………..78 5.1 Future Research……………………………………………………………..79 References……………………………………………………………………………81 vi.

(7) 圖目錄 Chapter 1 IPD Introduction Figure 1.1 (a) Cross section of IMEC’s MCM-D technology…………..………...…...6 (b) Simple Structure of Integrated Passives device………………..…...….6 Figure 1.2 Fabrication process flow……………………………………………..…….7 Figure 1.3 Finished Embedded Passive devices top view (a) Spiral Inductor, (b) Capacitor, (c) Resistor …………….………………………………………....8 Figure 1.4 Layout of simple integrated resistor……………………………………….9 Figure 1.5 Resistor geometries expresses as numbers of squares…………….….…..10 Figure 1.6 Capacitor model with parasitic L and R…………………………....……..12 Figure 1.7 Capacitor equivalent circuit………………………………………...…….13 Figure 1.8 Impedance characteristic vs. frequency………………………………..…13 Figure 1.9 Two basics configuration of integrated capacitors…………….……..…...14 Figure 1.10 connection option for build-up integration capacitors…………………..15 Figure 1.11 Inductor model with parasitic C and R………………………………….16 Figure 1.12 Impedance characteristic vs. frequency for a practical and an ideal inductor……………………………………………………………………………….17 Figure 1.13 Distributed capacitance and series resistance in an inductor……………18 Figure 1.14 Spiral Inductor model…………………………………………………...19 Figure 1.15 Microstrip rectangular inductor (1.5turn)………………………….……20 Figure 1.16 Equivalent circuit of a spiral inductor on alumina substrate……………20 2. Introduction of Measurement and Simulation Tools Figure 2.1 Lightwave analogy to High-Frequency Device Characterization…….…..25 Figure 2.2 Common Terms for High-Frequency Device……………………….….…26 Figure 2.3 Schematic of full 2-port calibration…………………………………...….28 Figure 2.4 HFSS model of Inductor…………………………………………….……31 Figure 2.5 Design Flow of Ansoft HFSS………………………………………….…32 Figure 2.6 Solution Type Window……………………………………………….…..33 3. Experiment Sample and Environment Figure 3.1 Inductor and Capacitor layout……………………………………….……37 Figure 3.2 Microphotograph of an integrated spiral inductor and a MIM capacitor before packaging……………………………………………………………….….…38 Figure 3.3 Top view and bottom view of spiral inductor and MIM capacitor after vii.

(8) packaging of flip-chip BGA……………………………………………………...…..38 Figure 3.4 (a) Agilent 8364B network analyzer setup and (b) experiment environment……………………………………………………………………….….39 Figure 3.5 a 500-μm pitch RF probe made by Cascade Microtech……………..……40 Figure 3.6 Build-up substrate structure………………………………………………42 Figure 3.7 Laminate Substrate Structure (a) 2 layer laminated substrate (b) before and after lamination……………………………………………………………………….42 Figure 3.8 cross-section of finished Flip-Chip BGA substrate………………..……..43 Figure 3.9 package substrate 3-D models………………………..…..………………44 Figure 3.10 Simplified substrate model…………………………….……………..…45 Figure 3.11 Substrate S-parameters……………….……………………………...…..45 Figure 3.12 Model of integrated passives after packaging in ADS…………………..46 Figure 3.13 Simulation result that shown the S-parameter of measured passive that connected to simulated substrate………………………………..……………………46 4. Experimental Study Figure 4.1 Measured S-parameter of Embedded Capacitor before and after packaging (a) Return Loss (b) Transmission Loss…………………...………………………..…48 Figure 4.2 Measured S-parameter of Embedded Inductor before and after packaging (a) Return Loss (b) Transmission Loss……………………………………...………..49 Figure 4.3 Test Chip Layout………………………………………………………….51 Figure 4.4 Ca and Inductor on test chip………………………………………….…..52 Figure 4.5 Layer dimension of test chip………………………………………..……53 Figure 4.6 Structure is sweep into 3-D using HFSS…………………………………53 Figure 4.7 Capacitor model before Packaging……………………………………….55 Figure 4.8 Return loss and Insertion Loss of Capacitor before Packaging…………..56 Figure 4.9 Phase of Capacitor before Packaging……………….……………………57 Figure 4.10 Smith Chart of Capacitor before Packaging…………………………….58 Figure 4.11 Quality factor of Capacitor before Packaging………………….…….…59 Figure 4.12 E-Field and H-Field of Capacitor before Packaging (Last Adaptive Freq = 6GHz)………………………………………………………………………….……..60 Figure 4.13 Model of Capacitor after Packaging…………………………………….61 Figure 4.14 Return loss and Insertion Loss of Capacitor after Packaging…………...62 Figure 4.15 Phase of Capacitor after Packaging……………………………………..63 Figure 4.16 Smith Chart of Capacitor after Packaging……………………………....64 Figure 4.17 E-Field and H-Field of Capacitor after Packaging (Last Adaptive Freq = 1GHz)………………………………………………………………………….……..65 Figure 4.18 Model of Embedded Spiral Inductor before Packaging………………....67 viii.

(9) Figure 4.19 Return loss and Insertion Loss of Inductor before Packaging…………..68 Figure 4.20 Phase of Inductor before Packaging………………………………….....69 Figure 4.21 Smith Chart of Inductor before Packaging…………………………..….70 Figure 4.22 Quality factor of Inductor before Packaging………………………...….71 Figure 4.23 E-Field and H-Field of Inductor before Packaging………………….….72 Figure 4.24 Model of Embedded Spiral Inductor after Packaging…………………..73 Figure 4.25 Return loss and Insertion Loss of Inductor after Packaging….……...….74 Figure 4.26 Phase of Inductor after Packaging…………………………….……..….75 Figure 4.27 Smith Chart of Inductor after Packaging……….……………...………..76 Figure 4.28 E-Field and H-Field of Inductor after Packaging…………………….....77. 表目錄 Table 1.1 Passive and IC count for portable consumer products………….…………..3 Table 1.2 Number and type of passive components in personal computers……...…...4 Table 3.1 Substrate material data…………………………….………………...……..44 Table 4.1 Embedded Passive Value…………………………………………………..51. ix.

(10) Chapter 1 IPD Introduction. 1.1 Integrated Passive Device Wireless communication has become the trend in RF device applications. Passive elements such as inductors, capacitors play a critical part in RF application. This thesis will focus on the simulation of inductor and capacitor after and before packaging for their application in integrated passive devices, and related measurement of inductor and capacitor after and before packaging using VNA (Vector Network Analyzer) was also be fulfilled. The continuous of miniaturization of electronic packaging requires a new way to integrate the devices on a substrate. Traditionally the passive and active components are mounted on the board surfaces with surface mount technology (well known as SMT). The components size, I/O pitches and line width of the printed circuit board (PCB) has been decreased to its limit, it’s difficult to decrease the size anymore with the traditional technology. It has increased the interest in embedding passive and active component inside the substrate. Increasing packaging density will cause not only manufacturing and. 1.

(11) reliability issues but also thermal problems. Due to the demand of faster signal processing, higher clock frequency and lower power consumption, the electrical performance of the package become more important. In high frequency application, it required to have a low parasitic interconnection and small attenuation. When one component is placed near to each other, unwanted coupling will happens. There are more passive devices than active devices in any RF application. For example, an Ericsson CF388 PCS 1900 cell phone has 380. components,. including. 322. passives. and. 15. ICs. with. passive-to-active ratio of 21:1. Digital systems, such as desktop and laptop computers, have somewhat lower ratios from 5 to 15 passives for every IC, as shown in Table 1.1. All types of electronic systems are becoming more complex while pressure is simultaneously mounting to make them smaller and lighter. The numbers of passives are steadily increasing and the required range of values is very wide. Manufacture and placement of 0201 discrete may represent the size and density limit for SMT devices.. 2.

(12) Table 1.1 Passive and IC count for portable consumer products [1]. 3.

(13) In order to meet the demand for higher integration, the interest toward passive component embedding was increasing during the past few years. Demanding for higher packaging density is one of the main reasons for the growing interest toward embedded active components, and is the need for better electrical performance of the component assemblies.. Table 1.2 Number and type of passive components in personal computers [1]. 4.

(14) Here there are some reasons for integrated passive devices: 1. Reduce system volume; individual package is eliminated and passives can go underground, leaving some space on the surface for chip. 2. Improve electrical performance; because integrated passives can have lower parasitic, particularly, much lower inductance in capacitors 3. Improve reliability; lead-free, solder joints are eliminated. 4. Reduce cost; integrated passives can be formed simultaneously and with very low incremental cost. Also, they are lead-free. 5.

(15) 1.1.1 Device Structure Passive elements such as inductors, capacitors, and resistor play a critical part in RF application. They reduce system volume because the individual package is eliminated and passives can go underground, leaving some space on the surface for chip as shown in Figure 1.1.. (a) TaN Ta2O5 Al BCB Cu/Ti. (b) Figure 1.1 (a) Cross section of IMEC’s MCM-D technology (b)Simple Structure of Integrated Passives device. 6.

(16) 1.1.2 Fabrication Flow Fabrication process flow of Integrated Passive Device (IPD) is as shown in Figure 1.2 allows the wafer level fabrication of IPD with planar coils, MIM capacitors, resistors, passivation layer and pad metallization.. 1. 10. 2. 11. 3. 12. 4. 13. 5 14. 6. 15. 7. 16. 8. Phase 1 RC Module completed 17. 18. Phase 2 Inductor completed 9.. Figure 1.2 Fabrication process flow 7.

(17) (a). (b). (c). Figure 1.3 Finished Embedded Passive devices top view (a) Spiral Inductor, (b) Capacitor, (c) Resistor. 1.2 Passives Theory 1.2.1 Resistor Resistor is one of the characteristics of conductor, which obstruct the current, when the current past through resistor, it will dissipated as heat. Integrated resistor are fabricated either by depositing and patterning layer of resistive material or by printing resistive paste in series with an interconnect line on an insulating substrate. In keeping with the concept of planar, stacked assembly, the resistor will be a film of material, probably between a few hundred angstroms and a few microns thick Assuming that all of the resistance is in the resistor material and not in the interconnects, the resistance of the structure is. R= 8. ρL Wt.

(18) where: R =resistance (Ω) ρ = resistivity of the material (Ω-cm). L = length of the strip (cm) W = thickness of the strip (cm). W L. Figure 1.4 Layout of simple integrated resistor. For thin films, the resistivity can be somewhat different from that of bulk materials, and is generally higher. The reciprocal of the resistivity is conductivity in (Ω-cm)-1, sometimes referred to as “Siemens”. ⎛ ρ ⎞⎛ L R = ⎜ ⎟⎜ ⎝ t ⎠⎝W where:. R=. ρ t. =sheet resistance (Ω/square). 9. ⎞ ⎟ = Rs N s ⎠.

(19) Ns =. L W. = the number of squares (Ω-cm). L = length of the strip (cm). L. Current ｔ W L. W. Square. W. Figure 1.5 Resistor geometries expresses as numbers of squares. 10.

(20) 1.2.2 Capacitor Capacitor is used extensively in radio frequency, as bypass circuit, resonance circuit, and filter. Practically capacitor is the arrangement of two conductors separated by an electric insulator (i.e. dielectric) is a capacitor. An electric charge deposited on one of the conductors induces an equal charge of opposite polarity on the other conductor. As a result, an electric field exists between the two conductor surfaces and there is a potential difference between them. The electric field anywhere between the conductor surfaces is directly proportional to the magnitude of the charge Q on the conductors. And the potential difference V is also directly proportional to the charge Q. The ratio Q/V is thus a constant for any electric field distribution as determined by the shape of the conductors, the distance of separation, and the dielectric in which the field exists. The ratio Q/V is called the capacitance, C, of a particular arrangement of conductors and dielectric. Thus, C = Q/V, where Q and V are in units of coulomb and volt. C has the unit’s farad (F).. 11.

(21) C=. ε rε o A d. (Farads ). Where: A = plate area [m2] = cross section of electric field, d = distance between plates [m], -12. ε o = permittivity of free space = 8.854 x 10. F/m. ε r = relative permittivity of the dielectric between the plates [dimension. less].. R Rp L `. R Rs C Cp. Figure 1.6 Capacitor model with parasitic L and R [3]. At high frequency, the equivalent circuit of capacitor is shown in Figure 1.6, where C equals the capacitance, Rp is the parasitic resistance, which is heat-dissipation loss; Lp is inductance of the leads and plates.. 12.

(22) Re. Xe. Figure 1.7 Capacitor equivalent circuit [3]. Figure 1.8 Impedance characteristic vs. frequency [3]. The effect of imperfection in the capacitor is seen in Figure 1.8. As the frequency of operation increased, the lead inductances become important. Finally, the Fr, the inductor is resonance with the capacitor. Then, above Fr, the capacitor act like inductor. 13.

(23) The Impedance of capacitor is Zc=Re+jXc,. Xc =. where Dissipation factor is DF = (Quality Factor) is Q =. 1 ω = 2π f ωC ;. Re , where Re is series resistance. Capacitor Q Xc. 1 Xe = , We expect Q to be high, DF to be small. DF Re. There are two basics configuration for integrated capacitors, parallel and floating plated, as shown in Figure 1.9.. Figure 1.9 Two basics configuration of integrated capacitors [1] A more accurate representative is shown for a built-up integrated capacitor in Figure 1.10.. 14.

(24) Figure 1.10 connection options for build-up integration capacitors [1]. 1.2.2.1 Decoupling Capacitance In electronic packaging substrate, decoupling capacitance is very important. The job of a decoupling capacitor is to provide enough current to run the chip for one clock cycle without its voltage dropping excessively and to deliver this charge very quickly. The amount of charge needed to satisfy the first requirement can usually be provided by only a few hundred nF of capacitance. Decoupling capacitance often placed in electronic packaging substrate to reduce switching noise. Because what they intended to do, decoupling capacitance must have a low parasitic inductance. Embedded capacitance inherently has much less parasitic inductance than surface mount can ever achieve because the embedded dielectric is very thin, currents travel in opposite directions instead of the 15.

(25) same way in most discretes, and because of the absence of vias up to the surface and back, which create an inductive current loop.. 1.2.3 Inductor Inductor is use extensively in radio frequency, as resonance circuit, phase shift and filter.. Radio frequency choke also the part of inductor, use to blocking high frequency signal. Inductor equivalent circuit is shown on Figure 1.11, where L is Inductor, Rs as coil resistance, Cd is total capacitance form of each circle as shown in Figure 1.12.. L L. R Rs. C Cd. Figure 1.11 Inductor model with parasitic C and R [3]. 16.

(26) Figure 1.12 Impedance characteristic vs. frequency for a practical and an ideal inductor [3]. The effect of Cd upon the reactance of an inductor is shown in Figure 1.12. Initially, at lower frequency, the inductor’s reactance parallels that of an ideal inductor. Soon, the reactance departs from the ideal curve and increases as much faster rate until it reaches a peak at the inductor’s parallel resonant frequency (Fr). Above Fr, the inductor’s reactance begins to decrease with frequency and, thus, the inductor begins looks like capacitor.. 17.

(27) Figure 1.13 Distributed capacitance and series resistance in an inductor [3] Inductor Q factor is Q =. Xe . If inductor were wound with a perfect Re. conductor, its Q would be infinite and we would have a lossless inductor. Of course there is no perfect inductor; an inductor always has some finite Q. Some method of increasing Q of an inductor: 1. Use larger diameter wire, this increase the ac and dc resistance of the windings. 2. Spread winding apart. Air has a lower dielectric constant than most insulators. Air gap between the windings decrease the interwinding capacitance. 3. Increase the permeability of the flux linkage path. This is most often done by winding the inductor around a magnetic-core material, such as iron or ferrite.. 18.

(28) In this thesis, Spiral inductor simulation will be measured using VNA and simulated by HFSS. Here is some introduction of spiral inductor. The spiral inductor is implemented on-chip or substrate using microstrip lines. The model of spiral inductor is shown in Figure 1.14.. Figure 1.14 Spiral Inductor model. An example of rectangular planar spiral inductor is shown in Figure 1.15. The key device geometry parameters are also indicated in the figure. L1 us the length of first segment, L2 is the length of second segment, L3 is the length of third segment, Ln is the length of last segment, W is the conductor width, and S is the spacing between the conductors.. 19.

(29) Figure 1.15 Microstrip rectangular inductor (1.5turn) [1]. A basic lumped-element representation of the spiral inductor is shown in Figure 1.16.. C Ci. Port 1 L C Ls Csub1. Port 2 R Rs. C Csub2. Figure 1.16 Equivalent circuit of a spiral inductor on alumina substrate [3]. 20.

(30) In designing the layout of the spiral inductor, the objective is to obtain the desired value of inductance in the smallest area, while keeping the parasitic capacitance low to ensure that the self-resonance frequency of the element is outside of the designed frequency band. The Q-factor is very important parameter in the design of the inductor, and it is a function of frequency and geometrical parameters. By changing the geometry, the inductor Q-factor can be optimized to the highest value for frequency range at which the inductor will operate.. 1.4 Integrated Passive Devices for RF Application The demands on today’s wireless systems, both in terms of functionality and form factor, are driving the trend towards more compact, lightweight and better performance components and subsystems, placing huge demands on component and assembly technologies. Passive components form the majority of the devices mounted on the circuit board, there is considerable incentive to identify ways of reducing the number and size of these devices without compromising system performance. Integrated passive devices can provide a large number of passive components and functional blocks within a single device, reducing the overall complexity at the board level and improving the ease 21.

(31) of assembly. In order to be effective, however, both the manufacturing and packaging technologies need to be selected to optimize performance, area density and cost. Chip-scale packaging, combined with a thin film passive device technology and a large area format manufacturing capability offers a solution to these issues, as well as providing a package form factor compatible with existing surface mount assembly operation. While silicon integration grows rapidly in terms of providing increased functionality within a reduced device foot print, a similar trend has been lacking in the passive component area. This is apply demonstrated by considering the circuitry within a cell phone, where the passive component count now outweighs the number of active integrated circuits by a factor of 20: 1, with some products containing nearly one thousand passive components. Most efforts in the passives area have focused not on improving the functionality of the passive device, but on reducing the discrete component size, to a point at which 0603 (60mils x 30 mils, or = 1.5 mm x 0.75 mm) and even 0402 (40 mils x 20 mils, or = 1 mm x 0.5 mm) single components are now in use. Such components can increase the onboard component density and cause some problems for the assembly houses, due to their very small size. One alternative is to. 22.

(32) combine many of the discrete components with one device - an integrated passive device or IPD - that can provide the same, if not, performance while alleviating the assembly difficulties by providing a more easily manageable format. To this end, the methods used to package these IPDs play a major role in determining their acceptance in the marketplace. The devices must be presented in a format that conforms to the existing, generally surface mount standards, while the packaging must add a minimum of overhead to the device in terms of cost and size, so as to maintain its competitiveness with the discrete component solutions. New packaging solutions are therefore needed to address these requirements.. 23.

(33) Chapter 2 Introduction of Measurement and Simulation Tools. In this chapter, Vector Network Analyzer (VNA) will be introduced as it is used for measuring embedded passive. Furthermore, Ansoft HFSS will be briefly introduced as it is a tool used to simulating the structure of embedded passive.. 2.1 Vector Network Analyzer Network analysis is the process by which user measure the electrical performance of the components and circuits used in more complex systems. When these systems are conveying signals with information content, we are most concerned with getting the signal from one point to another with maximum efficiency and minimum distortion. Vector network analysis is a method of accurately characterizing such components by measuring their effect on the amplitude and phase of swept-frequency and swept power test signals. Fundamentally, Network analysis involves the measurement of incident, reflected, and transmitted waves that travel along transmission lines. Using optical wavelengths as an analogy, when light strikes a clear 24.

(34) lens (the incident energy), some of the light is reflected from the lens surface, but most of it continues through the lens (the transmitted energy) (Figure 2.1). If the lens has mirrored surfaces, most of the light will be reflected and little or none will pass through it.. Figure 2.1 Lightwave analogy to High-Frequency Device Characterization [4]. Wavelengths are different for RF and microwave signals, the principle is the same. Network analyzers accurately measure the incident, reflected, and transmitted energy, e.g., the energy that is launched onto a transmission line, reflected back down the transmission line toward the source (due to impedance mismatch), and successfully transmitted to the terminating device (such as an antenna).. 25.

(35) Network analyzer terminology generally denotes measurements of the incident wave with the R or reference channel. The reflected wave is measured with the A channel, and the transmitted wave is measured with the B channel as shown in Figure 2.2. Figure 2.2 Common Terms for High-Frequency Device Characterization [4]. 2.1.1 Full Two Port Calibration Vector Network Analyzers (VNA) is very flexible measuring instruments - the microwave engineers’ most powerful tool. Their basic capability is to measure the S Parameters of an RF or microwave device and display the result in the frequency domain. This provides valuable. 26.

(36) data for the design engineer to develop a design and for the production engineer to substantiate the performance of the device or system. Before VNA is connected to DUT, it is necessary to do a calibration. Its purpose is to reduce the effects of error sources existing between the DUT and the instrument’s calibration plane. There is some way to do VNA calibration, but in here only full two port calibrations will be introduced. Full two port calibration also well known as SOLT (Short, Open, Load, Thru) calibration is a reflection and transmission measurements in which 12 systematic error terms measured, this usually requires 12 measurements on four know standards (SOLT) as shown in figure 2.3. SOLT calibration removes directivity source, load match, reflection tracking, transmission tracking, and crosstalk.. SHORT. SHORT. OPEN. OPEN. LOAD. LOAD. Figure 2.3 Schematic of full 2-port calibration [4] 27.

(37) 2.2 Finite Element Method (FEM) First, Finite Element Method (FEM) will be introduced here; Ansoft HFSS is FEM software. FEM software is a design tool for engineers and physicists, utilizing rapid computations to solve large problems insoluble by analytical, closed-form expressions. The FEM involves subdividing a large problem into individually simple constituent units which are each soluble via direct analytical methods, then reassembling the solution for the entire problem space as a matrix of simultaneous equations. FEM software can solve mechanical (stress, strain, vibration), aerodynamic or fluid flow, thermal, or electromagnetic problems. An FEM “Element” is a single subdivided ‘unit’ of the overall problem to be solved.. HFSS uses tetrahedral elements, with triangular. faces. The “Mesh” is the mapping of tetrahedral elements to the 3D geometry for which a solution is desired. Meshing is the process of defining the position of vertices which comprise all the tetrahedral locations in a problem space. The “Matrix” is the assembly of simultaneous equations related to the mesh which permit solution of behavior in a defined solution space. HFSS’s matrix equations are formulated to solve for electromagnetic field behavior.. 28.

(38) 2.3 HFSS introduction The function of Ansoft HFSS version 9.0 will be briefly introduced in this chapter. HFSS is a High Frequency Structure Simulator, a full wave electromagnetic field simulator for 3D volumetric modeling of passive devices. HFSS integrates simulation, visualization, solid modeling, and automation in familiar windows GUI environment. 2.5D simulation tools like Advanced Design System (ADS), Ansoft Designer (Planar EM) and IE3D are based on Method of Moments and mesh only the outside of metals, assuming all currents are on the surface. Internal metal fields are not simulated. That’s why HFSS is important, because full 3D is not restricted. HFSS is slower than 2.5D software but more accurate.. It deals with custom and arbitrary geometries.. It has. meshing capability on planes, and all internal fields are modeled showing current crowding. Figure 2.4 is an inductor modeling using Ansoft HFSS. HFSS is possible for modeling uses of: 1. Package Modeling – BGA, QFP, flip-chip 2. PCB Board Modeling – ground planes 3. Silicon/GaAs – spiral inductors, transformers 4. EMC/EMI – coupling, near/far field radiation. 29.

(39) 5. Antennas/Mobile Communications – patches, dipoles, horns, cell phone antennas 6. Connectors – coax, backplanes, SFP/XFP, vias 7. Waveguides – filters, resonators, couplers 8. Filters – cavity filters, microstrip, dielectric. Figure 2.4 HFSS model of Inductor. 30.

(40) 2.3.1 Design Flow Ansoft HFSS Desktop provides a friendly interface for the simulation of passive RF devices models. It creates designs, with the following steps: 1. Parametric Model Generation – Creating the geometry, boundaries and excitation 2. Analysis Setup – defining solution setup and frequency sweeps 3. Results – creating 2-D reports and field plots 4. Solve Loop – the solution process is fully automated. 31.

(41) Design. Solution Type Boundaries 1. Parametric Model. 2. Analysis Solution Setup Frequency. Excitation. Mesh Operation. Analyze. Mesh Refinement. NO 3. Result 2D Reports Field. Solve. Converge YES. Update. Finished. Figure 2.5 Design Flow of Ansoft HFSS [5]. 32.

(42) 2.3.2 HFSS Solution Process The Solution Type defines the type of results, how the excitations are defined, and the convergence. Solution Types available are: 1. Driven Modal - calculates the modal-based S-parameters. 2. Driven Terminal - calculates the terminal-based S-parameters of multiconductor transmission line ports. 3. Eigenmode – calculate the eigenmodes, or resonances, of a structure.. The solution type used in this work is mostly Driven Modal and Driven Terminal, which the S-parameter of Inductor and Capacitor can be created easily after the simulation.. Figure 2.6 Solution Type Window. 33.

(43) 2.3.3 Boundary Condition Boundary conditions enable you to control the characteristics of planes, face, or interfaces between objects. As a user of Ansoft HFSS you should be aware of the field assumptions made by boundary conditions. Since boundary conditions force a field behavior we want to be aware of the assumptions so we can determine if they are appropriate for the simulation. Improper use of boundary conditions may lead to inconsistent results. When used properly, boundary conditions can be successfully utilized to reduce the model complexity. In fact, Ansoft HFSS automatically uses boundary conditions to reduce the complexity of the model. Ansoft HFSS can be thought of as a virtual prototyping world for passive RF devices. Unlike the real world which is bounded by infinite space, the virtual prototyping world needs to be made finite. In order to achieve this finite space, Ansoft HFSS applies a background or outer boundary condition which is applied to the region surrounding the geometric model.. 34.

(44) There are three types of boundary conditions. 1. Excitations z Wave Ports (External) z Lumped Ports (Internal) 2. Surface Approximations z Symmetry Planes z Perfect Electric or Magnetic Surfaces z Radiation Surfaces z Background or Outer Surface 3. Material Properties z Boundary between two dielectrics z Finite Conductivity of a conductor The background is the region that surrounds the geometric model and fills any space that is not occupied by an object. Any object surface that touches the background is automatically defined to be a perfect E boundary and given the boundary name outer.. 35.

(45) Chapter 3 Experiment Sample and Environment. 3.1 Sample and Measurement Preparation In this thesis, inductor and capacitor were made by 0.25μm process technology as shown in Figure 3.1. Before and after packaging sample is shown in Figure 3.2 and 3.3 respectively. This component were measured using cascade microwave RF probe station using Vector Network Analyzer (VNA), as shown in Figure 3.4. The system consist of Cascade microwave RF probes station, Agilent 8364B network analyzer, and a computer with ADS (Advance Design System) software by Agilent. The network analyzer and microwave probes are connected by high-frequency cables. The measurement data are transferred from the network analyzer to a computer via the HP-IB bus. In this measurement, 500-μm pitch RF probe as shown in Figure 3.5, made by Cascade Microtech,. is. used. to. perform. measurement.. 2-ports. S-parameters measurements were performed from 10 MHz to 12 GHz. In order to remove errors caused by the measurement system and obtain accurate characteristics of devices, a. 36.

(46) standard Short-Open-Load-Thru (SOLT) calibration is done.. Figure 3.1 Inductor and Capacitor layout. 37.

(47) (a). (b). Figure 3.2 Microphotograph of an integrated spiral inductor and a MIM capacitor before packaging.. (a). (b). Figure 3.3 Top view and bottom view of spiral inductor and MIM capacitor after packaging of flip-chip BGA.. 38.

(48) Agilent 8364B network analyzer High Frequency Cable. (a). (b) Figure 3.4 (a) Agilent 8364B network analyzer setup and (b) Experiment environment 39.

(49) Figure 3.5 a 500-μm pitch RF probe made by Cascade Microtech. 40.

(50) 3.2 Packaging Substrate Embedded passives manufacture using multi-layer substrate by etching and printing method. Packaging substrate issue must be checked for integrated passives device. In common, there are two kinds of substrate, one is known as Build-up substrate, the other is knows as laminated substrate. Figure 3.6 shows the build-up substrate structure, which core is made by a rigid material such as glass, BT resin, silicon, or plastic. Figure 3.7 shows the laminated substrate structure, which core is made by FR4, an organic substrate is laminated with heat and pressure. In this work, a double layer shown in Figure 3.8 substrate will be used as the test vehicle which is finished BGA with a chip attached on it. Substrate alone simulation will be shown in this chapter before passive devices mounted on it. In this work, a double layer shown in Figure 3.8 substrate will be used as the test vehicle which is finished BGA with a chip attached on it. Substrate alone simulation will be shown in this chapter before passive devices mounted on it.. 41.

(51) Figure 3.6 Build-up substrate structure. (a). (b). Figure 3.7 Laminate Substrate Structure (a) 2 layer laminated substrate (b) before and after lamination. 42.

(52) Die Solder Bump Underfill Substrate Solder Ball Figure 3.8 cross-section of finished Flip-Chip BGA substrate. 43.

(53) Measurement of substrate alone is not easy to obtain because the bump is too small and the requirement of “up and down” probing issue. Thus a simulation is used to find the effect of the substrate. Figure 3.9 shown the packaging substrate modeled by using Ansoft HFSS, Table 3.1 is the material parameter used in substrate simulation.. Figure 3.9 package substrate 3-D models. Table 3.1 Substrate material data Material Er Loss tangent BT resin 3.8 0.0015 Soldermask 3.9 0.0015. 44.

(54) The substrate model is simplified as shown in Figure 3.10 to find the s-parameter of one substrate via. Simulation result is shown in Figure 3.11.. Figure 3.10 Simplified substrate model. 0. S-parameter (dB). -10. -20. -30. -40. S11(dB) S21(dB). -50. -60 0. 2. 4. 6. 8. 10. 12. Frequency (GHz). Figure 3.11 Substrate S-parameters. 45. 14.

(55) After the simulation is done, the result is imported into ADS, as shown in Figure 3.12 which is the model of integrated passives after packaging. Part A and C is the substrate via and part B is the passive device. ADS simulation result shown that the simulation result of the model is fitted to the measurement data, which prove the substrate simulation is true.. 1. 2. Term Term1 Num=1 S2P Z=50 Ohm A. 1. 2. Ref. 1. Ref. 2. Term Term2 Num=2 Z=50 Ohm. Ref. S2P B. S2P C. Figure 3.12 Model of integrated passives after packaging in ADS. 0. -5. dB(circuit_all..S(1,2)) dB(circuit_all..S(1,1)) dB(S(1,2)) dB(S(1,1)). -10. -15. -20. -25. -30. -35. -40 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. freq, GHz. Figure 3.13 Simulation result that shown the S-parameter of measured passive that connected to simulated substrate 46.

(56) Chapter 4 Experiment Study 4.1 Measurement Result Embedded MIM capacitor and inductor before and after packaging has been measured. Figure 4.1 show the measurement result for capacitor before and after packaging and Figure 4.2 show the measurement result for inductor before and after packaging. Measured device characteristics and simulated passive devices will be shown and compared to the measurement result.. 47.

(57) 10. 0. -10. S11(dB). -20. -30. After Packaging Before Packaging. -40. -50 0. 2. 4. 6. 8. 10. 12. Frequency (GHz). (a). 0 -10. S21 (dB). -20 -30 -40 -50. After Packaging Before Packaging. -60 -70 0. 2. 4. 6. 8. 10. 12. Frequency (GHz). (b) Figure 4.1 Measured S-parameter of Embedded Capacitor before and after packaging (a) Return Loss (b) Transmission Loss. 48.

(58) 0. -5. S11 (dB). -10. -15. -20. After Packaging Before Packaging. -25. -30 0. 2. 4. 6. 8. 10. 12. 10. 12. Frequency (GHz). (a) 0. -5. S21 (dB). -10. -15. -20. -25. After Packaging Before Packaging. -30 0. 2. 4. 6. 8. Frequency (GHz). (b) Figure 4.2 Measured S-parameter of Embedded Inductor before and after packaging (a) Return Loss (b) Transmission Loss. 49.

(59) 4.2 Simulation Result Simulation work is done with High Frequency Structure Simulator (HFSS) by Ansoft. First, we must set up the passives structure, which is drawn 2D using AUTOCAD as shown in Figure 4.3. This study will focus on Ca1 and In1 on the test chip, which is circle on the figure. The next step is to separate each layer of the layout, after that, it is imported into HFSS; by using HFSS, we can sweep 2-D model into 3-D model as shown in Figure 4.6. To build a 3-D model we need to know the thickness of each layer as shown in Fig 4.5. Relative permittivity of the material of the material is also shown in the same figure.. 50.

(60) Figure 4.3 Test Chip Layout. Table 4.1 Embedded Passive Value Inductor. 7.08 nH. Capacitor. 0.485 pF. 51.

(61) Figure 4.4 Ca and Inductor on test chip. 52.

(62) Figure 4.5 Layer dimension of test chip. Figure 4.6 Structure is sweep into 3-D using HFSS 53.

(63) 4.2.1 Simulation of Capacitor In this section, the simulation result will be shown. The result of Simulation will be compared with the measurement data, which is s-parameter, phase, smith chart, Q-factor, E-field and H-field. The measurement result of embedded MIM capacitor in comparison with simulated data was shown. Below is figure of models before and after packaging are the measured and simulated values of S11 and S21 before and after packaging. Related phase and smith chart are also shown to compare the RF characteristic for capacitor before and after packaging. In this work, the measurement and simulation data with packaging effect is fit well and reasonable.. 54.

(64) Figure 4.7 Capacitor model before Packaging. 55.

(65) 0. Before Package-Measure Before Package-HFSS Before Package-ADS. -2. S11(dB). -4. -6. -8. -10. -12 0. 2. 4. 6. 8. 10. 12. 14. Frequency (GHz). 0. -10. S21(dB). -20. -30. -40. Before Package-Measure Before Packaging-HFSS Before Package-ADS. -50. -60 0. 2. 4. 6. 8. 10. 12. 14. Frequency(GHz). Figure 4.8 Return loss and Insertion Loss of Capacitor before Packaging 56.

(66) 30. Before Package-Measure Before Package-HFSS Before Package-ADS. Phase(S(1,1)). 0. -30. -60. -90. -120 0. 2. 4. 6. 8. 10. 12. 14. Frequency(GHz). 120 90 60. Phase(S(2,1)). 30 0 -30 -60 -90. Before Package-Measure After Packaging-HFSS Before Package-ADS. -120 -150 -180 0. 2. 4. 6. 8. 10. 12. Frequency(GHz). Figure 4.9 Phase of Capacitor before Packaging 57. 14.

(67) S(1,1) measurement..S(1,1) S(2,1) measurement..S(2,1). freq (10.00MHz to 12.00GHz). freq (10.00MHz to 12.00GHz). Figure 4.10 Smith Chart of Capacitor before Packaging 58.

(68) Q=. −imag ( Z11 ) real ( Z11 ). 100 90. Before Package-Measure Before Packaging-HFSS Before Package-ADS. 80 70 60. Q. 50 40 30 20 10 0 -10 0. 2. 4. 6. 8. 10. 12. 14. Frequency(GHz). Figure 4.11 Quality factor of Capacitor before Packaging. .. 59.

(69) Figure 4.12 E-Field and H-Field of Capacitor before Packaging (Last Adaptive Freq = 6GHz). 60.

(70) Later, we will see the result of capacitor after packaging. The model is shown in Figure 4.17. The result is shown below. Figure 4.13 Model of Capacitor after Packaging. 61.

(71) 0.5 0.0. After Package-Measure After Package-HFSS After Package-ADS. -0.5. S11(dB). -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 0. 2. 4. 6. 8. 10. 12. 14. Frequency (GHz). 0. -10. S21(dB). -20. -30. -40. After Package-Measure After Packaging-HFSS After Package-ADS. -50. -60 0. 2. 4. 6. 8. 10. 12. 14. Frequency (GHz). Figure 4.14 Return loss and Insertion Loss of Capacitor after Packaging 62.

(72) 30 0. After Package-Measure After Package-HFSS After Package-ADS. Phase(S(1,1)). -30 -60 -90 -120 -150 -180 -210 0. 2. 4. 6. 8. 10. 12. 14. Frequency(GHz). 120 90 60. Phase(S(2,1)). 30 0 -30 -60 -90. After Package-Measure After Packaging-HFSS After Package-ADS. -120 -150 -180 0. 2. 4. 6. 8. 10. 12. Frequency(GHz). Figure 4.15 Phase of Capacitor after Packaging 63. 14.

(73) simulation..S(1,1) S(1,1) simulation..S(2,1) S(2,1). freq (10.00MHz to 12.00GHz). freq (10.00MHz to 12.00GHz). Figure 4.16 Smith Chart of Capacitor after Packaging 64.

(74) Figure 4.17 E-Field and H-Field of Capacitor after Packaging (Last Adaptive Freq = 1GHz) 65.

(75) 4.2.2 Simulation of Inductor The measurement result of embedded spiral Inductor in comparison with simulated data was shown. Below is figure of models before and after packaging are the measured and simulated values of S11 and S21 before and after packaging. Related phase and smith chart are also shown to compare the RF characteristic for inductor before and after packaging. In this work, the measurement and simulation data with packaging effect is fit well and reasonable.. 66.

(76) 4.18 Model of Embedded Spiral Inductor before Packaging. 67.

(77) 0. -5. S11(dB). -10. -15. -20. Before Package-Measure Before Packaging-HFSS Before Package-ADS. -25 0. 2. 4. 6. 8. 10. 12. 14. Frequency(GHz). 5. 0. S21(dB). -5. -10. -15. -20. Before Package-Measure Before Packaging-HFSS Before Package-ADS. -25. -30 0. 2. 4. 6. 8. 10. 12. 14. Frequency(GHz). Figure 4.19 Return loss and Insertion Loss of Inductor before Packaging 68.

(78) 80. Before Package-Measure Before Package-HFSS Before Package-ADS. 70 60 50. Phase(S(1,1)). 40 30 20 10 0 -10 -20 -30 -40 -50 -60 0. 2. 4. 6. 8. 10. 12. 14. 10. 12. 14. Frequency(GHz). 200. Before Package-Measure Before Package-HFSS Before Package-ADS. 150. Phase(S(2,1)). 100 50 0 -50 -100 -150 -200 0. 2. 4. 6. 8. Frequency(GHz). Figure 4.20 Phase of Inductor before Packaging 69.

(79) simulation..S(1,1) S(1,1) simulation..S(1,2) S(1,2). freq (10.00MHz to 12.00GHz). freq (10.00MHz to 12.00GHz). Figure 4.21 Smith Chart of Inductor before Packaging. 70.

(80) 8. Before Package-Measure Before Package-Simulate Before Package-HFSS. 6. Q. 4. 2. 0. -2. -4 0. 2. 4. 6. 8. 10. 12. 14. Frequency(GHz). Figure 4.22 Quality factor of Inductor before Packaging. 71.

(81) Figure 4.23 E-Field and H-Field of Inductor before Packaging. 72.

(82) 4.24 Model of Embedded Spiral Inductor after Packaging. 73.

(83) 5 0 -5 -10. S11(dB). -15 -20 -25 -30 -35. After Package-Measure After Packaging-HFSS After Package-ADS. -40 -45 -50 0. 2. 4. 6. 8. 10. 12. 14. 10. 12. 14. Frequency(GHz). 5 0 -5. S21(dB). -10 -15 -20 -25. After Package-Measure After Package-HFSS After Package-ADS. -30 -35 -40 0. 2. 4. 6. 8. Frequency(GHz). Figure 4.25 Return loss and Insertion Loss of Inductor after Packaging 74.

(84) 80. After Package-Measure After Package-HFSS After Package-ADS. 60 40. Phase(S(1,1)). 20 0 -20 -40 -60 -80 -100 -120 0. 2. 4. 6. 8. 10. 12. 14. Frequency(GHz). 0. After Package-Measure After Package-ADS After Package-HFSS. Phase(S(2,1)). -50. -100. -150. -200. 0. 2. 4. 6. 8. 10. 12. Frequency(GHz). Figure 4.26 Phase of Inductor after Packaging 75. 14.

(85) Simulation..S(1,1) S(1,1). freq (10.00MHz to 12.00GHz). Figure 4.27 Smith Chart of Inductor after Packaging. 76.

(86) Freq=1GHz. Figure 4.28 E-Field and H-Field of Inductor after Packaging 77.

(87) Chapter 5 Conclusions. The focus of this thesis is the measurement and simulation of integrated passive devices (capacitor and inductor) before and after packaging. Passive components (Resistors, Capacitors, and Inductors) occupy a large area of the electronic circuit boards, and the number is increasing, these are a major hurdle to the miniaturization of many electronic systems. Analog and mixed-signal applications, which use a large number of passives than typical digital system, almost no through-hole, axial leaded resistors and disk capacitors are used anymore; they have been replaced with smaller, rectangular surface-mount components with solder joints at both ends. The size of these modern discrete is described by a number such as 0603, which indicates a size of 60 × 30 mils (1.5 × 0.75 mm). The 0402 (1.0 × 0.5 mm) size is commonly used, and the smallest discrete passives today are 0201 (0.50 × 0.25 mm). Part on of the thesis presented the Introduction of Integrated Passive devices, Device structure and theory is also discussed. In the second part, Ansoft HFSS is introduced as we used this software for doing simulation of IPD. Packaging substrate used in experiment study is discussed.. 78.

(88) Measurement and simulation result is shown in the last part, and they are quiet fit.. 5.1 Future Research Integrated Passive Devices have all benefits we want for future Integrated Circuit, as describe in the first chapter, but there are many problems with implementing integrated passives, such as: 1. Indecision on materials and processes. Research continues on many resistor materials and capacitor dielectrics. 2. Lack of design tools, for both component sizing and system layout. 3. Requires. vertical. integration.. The. same. company. must. manufacture both substrates and passives. 4. Yield issues. One bad component can lead to scrapping the entire board. 5. Tolerance issues. Integrated passives cannot be presorted prior to inclusion on the board. 6. Lack of standardization. The various segments of the integrated passive industry aren’t speaking the same language [14]. 7. Surface-mount technology is improving—moving towards 01005. 79.

(89) 8. Lack of costing models. It is not easy to tell when integrated passives might be more cost effective.. Table 5.1 Issues and status of integrated components. Over one trillion passive devices mounted on organic boards this year, this number will increase rapidly in the future, Integrated Passive devices will provide a great benefit if all the problem mention above can be solve.. 80.

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