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CHAPTER 4 . HARDWARE INTEGRATION

4.3 I NTEGRATION R ESULT

The hardware analysis reference is from [1] proposed in ISSCC2006, and is listed in Table 4-1. In Table 4-1, It shows the synchronization function and the relative gate count.

Table 4-1 the hardware gate count of synchronization function in [1]

Function Gate count

GI/Mode detector 7861 Coarse symbol Sync. 8590 SP mode detection 2963 Fractional CFO Sync. 8219 Integer CFO Sync. 12224 SCO tracking 11006 Residual CFO tracking 11686

Total 62549

The proposed hardware integration result is listed in Table 4-2, in Table 4-2, it shows the gate count of proposed synchronization function and the reused part, moving correlation core and tracking core.

Table 4-2 the hardware gate count of synchronization function for the proposed design

Function Gate count

GI/Mode detector 784 Coarse symbol Sync. 1535 SP mode detection 329 Fractional CFO Sync. 1117 Integer CFO Sync. 5020 Moving correlation core 7268

SCO tracking 1195

Residual CFO tracking 1399 Tracking core 10156

Total 28803

In Table 4-1 and Table 4-2, we can calculate the proposed design hardware integration. The hardware decreases from 62549 to 28803, and the saving of hardware reaches 46% than conventional design [1] in ISSCC2006.

Chapter 5 .

Conclusion and Future Work

The synchronization system for DVB-T/H standard is completed in this paper. In this paper, we propose three synchronization designs: carrier phase alignment, sampling clock synchronization and fast synchronization. First, Carrier phase alignment solves worst channel in the mobile environment. At SCO 20ppm and Doppler frequency 70Hz in Rayleigh multipath with SNR 34dB, our DVB-T/H system still reaches Quasi Error Free (QEF) criterion. Second, sampling clock synchronization separates into two parts: SCO estimation and SCO tracking. The target is different for these two parts. Target of SCO estimation is estimation accuracy and targets of SCO tracking are tracking convergence and convergent time. In this paper, the proposed design improves the SCO estimation accuracy 2~5 times and reduces the SCO tracking time 3 times. Third, in fast synchronization discussion, our proposed design can decrease the synchronization time 2~4.5 times. It also means that, in timing slicing architecture for DVB-H standard, we can save power consumption 65%~95%

and reduce receiver buffers 1Mbits~3Mbits. Finally, the overall system performance of the proposed synchronization system loses below 0.31dB for all kinds of channels, including static and mobile environments.

In this paper, we also integrate the hardware of synchronization schemes. We proposed to reuse the similar part of the synchronization architecture. The proposed hardware integration method decreases 46% gate counts than the conventional design [] proposed in ISSCC2006.

In the future, we plan to integrate the proposed designs, including the 3 proposed synchronization designs and proposed hardware integration, with the DVB-T/H system in [1].

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作 者 簡 歷

姓名 :李家豪

出生地 :台灣省台南市 出生日期:1982. 8. 22

學歷: 1989. 9 ~ 1994. 6 台南市立永華國民小學 1994. 9 ~ 1997. 6 台南市立新興國民中學 1997. 9 ~ 2000. 6 國立台南第一高級中學

2000. 9 ~ 2004. 6 國立暨南國際大學 電機工程學系 學士 2004. 9 ~ 2006. 7 國立交通大學 電子研究所 系統組 碩士

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