3.3 The Analysis of Reliability in nMOSFET Devices
3.3.2 IFCP for High-K Devices 20
the oxide and nitride respectively,
φ
2e is the normalized conduction band offset (V) of the interfacial layer and the HfSiON as shown in Fig 3.1.3.3.2 IFCP for High-K Devices
Charge-pumping is commonly used to measure the interface trap density, but based on previous section, it can also sense traps in HfSiON defect band. By varying the charge-pumping frequency, we can sense the different component of the trap density in HfSiON away from the interfacial layer.
The Icp current has three components, Nit, Not and leakage current, respectively. From IFCP, we can eliminate the contribution of Nit and leakage current and the remaining part is Not. Now, let me describe the procedures as the following:
Fig. 3.1 Bandgap diagram of the high-k dielectric in the excess electron state, showing trap-to-band tunneling (T-B).
e
φ 2
φ T
X ot
Si Substrate HfSiON φ 2 e SiO 2
φ T
X ot
Si Substrate
HfSiON SiO 2
1. First, we can obtain the Icp,100K from the subtraction Icp,5M from Icp,5.1M. At these high frequencies, the Icp,100K can only be treated as the contribution of Nit. 2. Then, we choose two frequencies which correspond to the particular position.
Using the above method, we could eliminate the contribution of Nit from the two frequencies we choose.
3. Later, we take the difference of ICP’S at two close frequencies. By this way, it can remove the DC leakage. The remainder is only the Not component.
4. Because it does not sense the same trap in HfSiON every time, so that the low frequency Icp is unstable. In order to solve this problem, we examined five times and tale an average of these values.
3.4 Results and Discussion
The trap density of vertical direction in HfSiON by halo implants with different halo implant species is plotted in Fig. 3.2. It seems that the sample with halo(2) causes more damage in the HfSiON near the interfacial layer, while does not affect the remaining part of the high-k layer. The higher trap density near the interfacial layer in halo(2) may be caused by using heavier atoms of the implant. And, it seems that it does not have influence on the location of the films away from the interfacial layer.
In order to measure the trap generation during electrical stress, a constant voltage stress is interrupted at regular intervals and a non-stressing voltage is applied before evaluation with charge-pumping. A schematic diagram of the stress and measurement sequence is shown in
Fig. 3.2 Comparison of the trap density in HfSiON for two different halo implant species, where halo(2) causes more damage in HfSiON close to the interfacial layer.
0.0 0.4 0.8
0 2 4 6 8 10
Trap Density(10 10 /c m 2 )
Depth(nm)
nMOSFET W/L= 10/0.09 µ m EOT=10.2Å
Halo(2)
Halo(1)
Fig. 3.3 The measurement flow used to monitor the trap generation. Before each set of charge-pumping measurements, a short non-stressing negative voltage is applied.
Fresh Device
Charge Pumping V amp = 1 V V base = - 1 V
at Various Frequency
Stress @ V G >0
Discharge - 1 V for 15 sec
Fresh Device
Charge Pumping V amp = 1 V V base = - 1 V
at Various Frequency
Stress @ V G >0
Discharge
- 1 V for 15 sec
HfSiON. And, it does not cause damage to the device as can be seen in Fig. 3.4. The increase of the bulk HfSiON trap density with different halo implant species during positive and negative gate voltage stress is plotted in Fig. 3.5, Fig. 3.6, Fig. 3.7, and Fig. 3.8. It can be found that, for VG < 0V, the variation of bulk trap is not obvious. On the contrary, we can see clearly the increase of bulk trap during the positive gate voltage stress.
In order to explain this phenomenon further, we see the trap generation versus stress time at fixed certain depth clearly. Fig. 3.9, Fig. 3.10, Fig. 3.11, and Fig. 3.12 show the increase of the interface trap density and the bulk trap density versus time during positive and negative gate voltage stresses. We can see that the interface trap generation is larger during gate injection than that for substrate injection. While, the bulk trap generation is just the reverse compared to the interface trap generation in that the bulk trap generation is larger during positive gate voltage stress. We can utilize Fig. 3.13 and Fig. 3.14 to explain the phenomenon.
During substrate injection, the electron will be attracted toward the gate dielectric. Then, it generates electron-hole pairs at the anode. The generated hot hole moves toward cathode and causes the injury on the gate dielectric. So, for positive stress polarity, trap creation occurs mainly in high-k dielectric. During negative gate voltage stress, trap generation is located at the interface. In case of gate injection, high energetic electrons arrive at the anode and hole injection leads to interface degradation. Because of the large difference in k-value between SiO2 and HfSiON, the voltage drop occurs mainly in the interfacial layer and electrons can enter the anode with energy with respect to the Si conduction band. This is why it produces more interface traps during negative gate voltage stress.
Fig. 3.4 The correlation between the shift of threshold voltage and time dependence. It seems not to cause the obvious damage using the discharging voltage.
10 100 1000
0.00018 0.00020 0.00022 0.00024 0.00026 0.00028 0.00030
Delta Thresholde Voltage, ∆ V th
stress time(s)
nMOSFET halo(1) W/L= 10/0.09
µ
m EOT=10.2Å stress@VG=-1V
Fig. 3.5 Comparison of the trap density in HfSiON in halo(1) during negative gate voltage stress.
0.0 0.2 0.4 0.6 0.8
0 5 10 15 20
T rap s Den s ity( 10 10 /cm 2 )
Depth (nm)
nMOSFET Halo(1) W/L= 10/0.09
µ
m EOT=10.2Å Stress@VG=-2V
fresh stressed
Fig. 3.6 Comparison of the trap density in HfSiON in halo(2) during negative gate voltage stress.
0 2 4 6 8
1 2 3 4 5 6 7 8 9 10
Traps Densi ty(10 10 /cm 2 )
Depth (nm)
nMOSFET Halo(2) W/L= 10/0.09 µ m EOT=10.2Å Stress@V
G
=-2V 1000s fresh
stressed
Fig. 3.7 Comparison of the trap density in HfSiON in halo(1) during positive gate voltage stress.
0.0 0.2 0.4 0.6 0.8
0 5 10 15 20 25 30
Traps Density(10 10 /cm 2 )
Detpth (nm)
nMOSFET Halo(1) W/L=10/0.09 µ m EOT=10.2Å
stress@V
G=+2V 1000s fresh
stressed
Fig. 3.8 Comparison of the trap density in HfSiON in halo(2) during positive gate voltage stress.
0.0 0.2 0.4 0.6 0.8
2 4 6 8 10 12 14
Tarp Density(10 10 /c m 2 )
Depth, (nm)
nMOSFET Halo(2) W/L=10/0.09
µm EOT=10.2Å
fresh stress@V
G
=2V 1000s
Fig. 3.9 Comparison of the interface trap density in halo(1) for two different stress voltages.
The interface trap generation is faster, during negative voltage stress.
10 100 1000
2.7 2.8 2.9 3.0 3.1 3.2 3.3
Interface Trap, D it (10 11 /cm 2 )
stress time (S)
nMOSFET Halo(1) W/L= 10/0.09
µ
m EOT=10.2Åstress@V
G=2V 1000s stress@-2Vg
Fig. 3.10 Comparison of the interface trap density in halo(2) for two different stress voltages.
The interface trap generation is faster, during negative voltage stress.
10 100 1000
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3
Interface Trap, D it (10 11 /cm 2 )
stress time (S)
nMOSFET Halo(2) W/L= 10/0.09
µ
m EOT=10.2Åstress@V
G=+2V stress@VG=-2V
Fig. 3.11 Comparison of the bulk trap density in halo(1) for two different stress voltages. The bulk trap in HfSiON generation is faster, during positive voltage stress.
10 100 1000
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Trap Density (10 10 /cm 2 )
stress time (S)
nMOSFET Halo(1) W/L= 10/0.09 µ m EOT=10.2Å
stress@V
G=+2V
stress@V
G=-2V
Fig. 3.12 Comparison of the bulk trap density in halo(2) for two different stress voltages. The bulk trap in HfSiON generation is faster, during positive voltage stress.
10 100 1000
2.0 2.5 3.0 3.5 4.0 4.5
Trap Density (10 10 /cm 2 )
stress time (S)
nMOSFET Halo(2) W/L= 10/0.09
µ
m EOT=10.2Åstress@VG=+2V stress@VG=-2V
Fig. 3.13 Schematic band diagram of a SiO2/HfSiON gate stack for substrate injection. High energetic electrons arrive at the anode and generate electron-hole pair.
n + pol HfSiON Si 2 S
n + pol HfSiON Si 2 S
substrate
Fig. 3.14 Schematic band diagram of a SiO2/HfSiON gate stack for gate injection. High energetic electrons arrive at the anode and hole injection leads to interface degradation.
n + pol HfSiON Si 2 S
substrat
n + pol HfSiON Si 2 S
substrat
3.5 Summary
In this chapter, we combine IFCP method and trap-to-band tunneling time constant to calculate the trap position in the HfSiON. The IFCP method improves traditional charge pumping measurement by eliminating direct tunneling leakage current in ultra-thin gate dielectric films for MOS devices, and helps us to calculate more accurate traps in the HfSiON.
On the other hand, we successfully separate Nit and Qot with IFCP method for high-k dielectrics.
According to the experimental results, we found the correlation between trap generation and stress polarity dependence. During substrate injection, it will cause more oxide traps in the high-k dielectrics. While during gate injection, it induces more damage in the Si/IL interface. Based on the above analysis, the developed method is useful for the understanding of the properties and reliability in the high-k dielectric devices.
Chapter 4
The Analysis of PBTI and PBTI-like Reliabilities in Different Halo Implant High–K N-MOSFET’s
4.1 Introduction
In order to improve the electrical properties and reliability of ultra-thin gate dielectric films for MOS devices, extensive studies have been made. The PBTI effect arises at high temperatures under the influence of small positive voltages on the gate of n-channel transistors. The effect seen is a shift in the threshold of the transistor to more positive gate voltages, and a decrease in the ID,sat curve due to an increase in the amount of trap charge in the HfSiON, as well as an increase in interface state densities.
In chapter 3, we have already used the IFCP method to investigate the properties under constant voltage stress (CVS). In this chapter, we will also use the method to investigate the device reliability under PBTI and PBTI-like stress conditions. Through the PBTI reliability testing, we found that PBTI was not sufficient to distinguish halo implant with different atomic mass unit. Because PBTI testing is a sensitive measurement for monitoring a uniformly distributed high K film quality, in regarding to the gate edge damage caused by halo implant, it can not provide a better way to study the device reliability. As a consequence, in order to clearly identify the degradation at the gate edge, we use the IFCP measurement to observe Not and Nit by employing PBTI-like stress.
4.2.1 The Devices Under Test
The devices used in this work were fabricated using 90nm CMOS technology. In this section, we use the devices with gate dielectric thickness (EOT= 10.2Å) to investigate the PBTI and PBTI-like stress with different halo implant species with halo(1) and halo(2), respectively.
4.2.2 PBTI Stress
First, we stress the nMOSFET with VG= 2V at 100oC for 1000 seconds. After finishing the stress, we use the method described in the previous chapter to calculate traps in the HfSiON and interface trap, as described in chapter 2. We can draw the distribution of traps along the direction of gate dielectric thickness. As revealed in Fig. 4.1 and Fig. 4.2, we observe the PBTI effect for different halo implant species. Fig. 4.3 shows the variation of interface traps during PBTI stress. The difference between halo(1) and halo(2) is the edge damage. It seems that it has not being able to characterize these two samples with different halo implant species clearly. Because through the PBTI reliability testing, it was not sensitive enough to distinguish halo implant with different atomic mass unit. PBTI testing is a sensitive measurement for monitoring overall high K film quality, as regards gate edge damage caused by halo implant is not the best examination. In order to investigate the degradation of gate edge more clearly, we use the IFCP measurement to observe Not and Nit after employing PBTI-like stress. This PBTI-like will be described as follows.
Fig. 4.1 Comparison of the trap density in HfSiON in halo(1) pre-PBTI stress and post-PBTI stress.
0.0 0.2 0.4 0.6 0.8
4 6 8 10 12 14 16 18
Oxide T rap , N ot (10 10 /cm 2 )
Depth (nm)
nMOSFET(Halo1) W/L= 10/0.09 µ m EOT=10.2Å
stress@V
G=2V 1000s Temperature=100 ° C
fresh
stress
Fig. 4.2 Comparison of the trap density in HfSiON in halo(2) pre-PBTI stress and post-PBTI stress.
0.0 0.2 0.4 0.6 0.8
4 6 8 10 12 14 16 18
Trap Densi ty(10 10 /cm 2 )
Depth (nm)
nMOSFET Halo(2) W/L= 10/0.09
µ
m EOT=10.2Å stress@VG=2V 1000s Temperature=100
°
Cfresh stress
Fig. 4.3 Comparison of the interface trap density in different halo implant species pre-PBTI stress and post-PBTI stress.
0.0 In terfa ce Trap D ensi ty, D
it(1 0
11/c m
2)
Halo(1)
4.2.3 PBTI-like Stress
In this section, the nMOSFET was stressed under PBTI-like condition (VG= VD= 2V, Temp= 100oC) for 1000 seconds. We may expect that the damage of PBTI-like includes the combined PBTI effect and HC effect. From IFCP results for two different samples, we can observe the amount of Nit and Not under PBTI-like stress condition. Since high K film has many traps, electrons will be trapped in the high-k gate dielectric near the source and drain edge, during hot carrier stress. This phenomenon has already been reported recently [15].
From this depiction, we find that the amounts of traps generated in halo(1) are less than that of halo(2). According to Fig. 4.4 and Fig. 4.5, we confirm halo(2) with heavy AMU implant form significantly more trap in the high-k film. For longer-channel length nMOSFET, local degradation does not greatly affect device characteristics. In contrast, for shorter-channel devices, this local degradation affects the device characteristics significantly. This can also be revealed from Fig. 4.6. Since more oxide traps cause more serious delta threshold voltage shift, for longer-channel nMOSFET, local degradation does not greatly affect device characteristics. In contrast, for shorter-channel devices, this local degradation affects the device characteristics significantly. Therefore, the increase of interface trap comparison between halo(1) implant and halo(2) implant can reflect the damage in the interface close to the gate edge after PBTI-like stress condition as shown in Fig. 4.7. The less amount of traps seen in HfSiON with halo(1) implant compared to halo(2) implant explains more serious damage at gate edge for halo(1) implant sample. In brief, the interface trap generation correlates closely with the traps in high-k gate dielectric near the source and drain side. When a large number of oxide traps are generated near gate edge border, the damage at gate edge will be lowered.
Fig. 4.4 Comparison of the trap density in HfSiON in halo(1) pre-PBTI-like stress and post-PBTI-like stress.
0.0 0.2 0.4 0.6 0.8
2 4 6 8 10 12 14 16 18 20
Trap Dens ity (10 10 /cm 2 )
Depth (nm)
nMOSFET halo(1) W/L= 10/0.09 µ m EOT=10.2Å
stress@V
G=V
D=2V 1000s Temperature=100 ° C
fresh
stressed
Fig. 4.5 Comparison of the trap density in HfSiON in halo(2) pre-PBTI-like stress and post-PBTI-like stress.
0.0 0.2 0.4 0.6 0.8
2 4 6 8 10 12 14 16
Trap Density(10 10 /cm 2 )
Depth (nm)
nMOSFET halo(2) W/L= 10/0.09
µ
m EOT=10.2Å stress@VG=V
D=2V 1000s Temperature=100
°
Cfresh Stressed
Fig. 4.6 The threshold voltage shift for different halo implant species.
10 100 1000
0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
Delt a Threshol de Vol tage, ∆ V th
stress time(S)
nMOSFET W/L= 10/0.09
µ
m EOT=10.2Åstress@VG=VD=2V 1000s Temperature=100
°
CHalo(2) Halo(1)
Fig. 4.7 Comparison of the interface trap density in different halo implant species during pre-PBTI-like stress and post-PBTI-like stress.
0.0 In ter face Tr ap Densit y , D
it(1 0
11/c m
2)
Halo(1)
4.3 Summary
In this chapter, we use the IFCP method and trap-to-band tunneling time constant to obtain the traps in the HfSiON and Nit after various stress conditions. We have investigated the degradation of PBTI and PBTI-like condition from the observation of Nit and Not. We can find that the amounts of oxide traps in halo(1) implant are less than that in halo(2) implant, it results in a higher effective stress field that causes worse damage to the interface near the drain extension region under PBTI-like stress condition. On the other hand, for nMOS, the decrease of the impact ionization rate is due to negative charge trapping which reduces the gate dielectric electric field.
Chapter 5
Summary and Conclusion
Alternative gate oxide material is a trend on the scaling of oxide thickness, but the direct tunneling leakage is still large with EOT scaled down to below 16Å. We utilize IFCP method and trap-to-band tunneling time constant to obtain the distribution of Qot in the HfSiON. The IFCP method has been validated to remove the tunneling leakage current during measurement such that Nit and Qot can be separated.
In this thesis, the test samples with different halo implant species, Halo(1) and Halo(2), representing Halo implant species with light AMU and heavy AMU have been used for the study. The stress polarity and time dependence of CVS effect were performed. Subsequently, the halo implant species dependence of PBTI and PBTI-like effect were evaluated.
Based on the experimental results, we have identified the correlation between trap generate and stress polarity dependence. During substrate injection, it will cause more oxide traps in the high-k dielectrics. While, during gate injection, it induces much more damage in the Si/IL interface. Furthermore, our study shows that the amounts of traps in Halo(1) are lower than in HfSiON, resulting in higher effective stress field that causes worse damage to the interface near the gate edge under PBTI-like stress condition. On the other hand, for nMOS, the decrease of the impact ionization rate is due to negative charge trapping which reduces the gate dielectric electric field. Therefore, for reliability test, the content of nitrogen in gate oxide will become increasingly important in future nanoscale CMOS devices before using high-k dielectrics.
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