Chapter 3 Low Power Ultra-Wideband Active
3.3 Improved Low Power Ultra-Wideband Active Balun…
Discussed in section 3.2, the gain error and phase error rise when frequency increase. According to the measurement result, we can find out two critical effects cause this result. First is the measurement environment. As mentioned, the probe parasitic are well calibrated for the two ports under test, the third port is terminated into an un-calibrated probe. The unexpected parasitic greatly affects measurements accuracy, especially for phase imbalance. It is found that by adding a parasitic inductance of 50fH at the third port output, simulation data approaches to measurement data. But this issue could be resolved by four-port measurements.
Second, unpredictable effects like process variation will affect the measurement result, too. Process variation will affect the circuit itself and change the output loading (the input impedance of the next stage). It is difficult to prevent this issue. So the active balun with a tunable function to calibrate the mismatch from the process variation is necessary.
And when active baluns combine with the next stage, the input impedance of the next stage (the output loading of the active balun) may changes. So it is necessary to see the variation of the gain difference and the phase difference when the RL in Fig. 3.14 changes. GD(200) and PD(200) mean the gain difference and the phase difference when RL in Fig. 3.14 equals 200Ω, respectively. We can observe the gain difference and the
phase difference both increase when RL increases in Fig. 3.15. So we need to design a tunable active balun for the output loading variation.
L
Fig. 3.14. Proposed active balun combined with the next stage.
-3.0
GD(200) GD(100) GD(50) GD(25)
PD(200) PD(100) PD(50) PD(25)
Fig. 3.15. The simulated gain difference and phase difference with difference RL.
Vdd
Vdd
3.3.1 Design on 0~10 GHz Ultra Wide-Band Low Power Tunable Active Balun for Loading Variation and Process Variation Compensation
The tunable ultra wide-band active balun is shown in Fig. 3.16. According to Eq.
(3-3), as gm >>2ω2CgdnCgdpin the frequency range of interest, the choice of R2 an R3
in Fig. 3.3 holds over a broad frequency range. Appropriate R2 and R3 can make minimum gain and phase error over the desirable bandwidth. So, use an active tunable resister M1 to replace R2 in Fig. 3.3 for tuning if it is necessary.
L
Vdd
R1
R3
Mn(W/L)
Mp(3W/L) C1
RFin
Out1
Out2 Vg
Va M1
Vtune
Fig. 3.16. The proposed tunable active balun.
0 2 4 6 8 10 12
0 0.2 0.4 0.6 0.8 1 1.2 Vsd (volt)
Id (mA)
Fig. 3.17. PMOS I_V curve.
Vg
Vs Vd
Cgd Cgs
Cdb Csb
Rds(R2)
Fig. 3.18. The equivalent model of the PMOS M1on the triode region.
The PMOS M1 works in the triode region. The I_V curve of the PMOS is shown in Fig. 3.17. On the triode region, MOS can be an active resister. When tuning VSG of the PMOS, the value of the active resister Rds (
dId
dVsd ) changes. The
equivalent model of the PMOS in the triode region shows in Fig. 3.18. Cgs and Csb of PMOS M1 can be ignored because Vg and Vs in Fig. 3.17 connect to ground directly.
Let Rds as R2 and Cgd//Cdb=C.
The small-signal equivalent circuit is as shown in Fig. 3.19. Critical to affect output imbalance, the gate-drain parasitic capacitance, Cgd, shall be included in the analysis. Derived from the core circuit, the common-source voltage, va, is related to the gate voltage, vg, as
If the voltage v is one half of the gate voltage v , two outputs can reach a well-balanced (3-4)
Fig. 3.19. Small-signal equivalent circuit model of the proposed tunable balun circuit.
condition. This leads to the requirement of gmn = gmp and C1+Cgsn = Cgsp. To do so, the PMOS size is chosen as three times of the NMOS size. An external capacitor, C1, is also added for the latter requirement. Under these conditions, the voltage ratio of the two outputs is given by
As can be seen, the impedance matching components affect no gain and phase imbalance. A balanced output demands vo1 = -vo2. If biasing current is large, then
gdn
m C
g >>ω and the condition is fulfilled. In low-power cases, the condition can be fulfilled if the values of R2 and R3 follow these equations,
) R3 holds over a broad frequency range. It concludes that the effect on imbalance from the transistor parasitic is less than that from the compensation feedback and the current source parasitic.
When process variation occurs, gain error and phase error will rise. Tuning the gate voltage of the PMOS M1 to changes the value of R2 to minimize the mismatch.
Fig. 3.20 and Fig. 3.21 show phase difference and gain difference shift when the gate
3
voltage of the PMOS M1 changes. As the gate voltage of the PMOS M1 rise 0.1V, gain difference and phase difference shift 1dB and 1.5°, respectively. According to the simulated result, when the output loading changes from 25 to 200Ω, the improved active balun still can achieves the desired performance. For constant DC power consumption, the bottleneck of the DC current is on the PMOS Mp not PMOS M1. So, when tuning the value of R2, DC power consumption almost will not increase.
-4
Fig. 3.21. Gain difference vs. Vtune.
174
Fig. 3.20. Phase difference vs. Vtune.
3.3.2 Microphotograph of Chip
A tunable balun circuit was designed in a standard 0.18um CMOS technology.
Fig. 3.22 shows the micrograph of the fabricated circuit. The total chip area is 0.5mm by 0.68mm including bonding pads for on-wafer probing measurements. The area of the core circuit could be much reduced in a fully integrated circuit. The RF input and output ports are placed on the opposite sides of the chip to improve the isolation.
According to the last measurement result of the 8GHz ultra wideband active balun, we find out there is the unaccounted parasitic at the gate-port of the PMOS resulting in higher gain error. So adding bypass capacitors to prevent this issue.
Vdd
RFin
gnd
(Out 1)
(Out 2) G
G G S
S Vtune
Fig. 3.22. Micrograph of the fabricated tunable active balun.
3.3.3 Simulation and Measurement results and Discussion
The load impedance at each output port is the same as the source of 50-Ω. As
such, the circuit presents an impedance transformation ratio of 1:2. Specified for ultra-wideband application, the design is optimized at the frequency of 8-GHz for minimum phase error and gain imbalance based on Eq. (3-6). The ideal design gives gain and phase imbalance of ±1dB and ±2°, respectively, up to 10-GHz. Post-layout simulation shows that the circuit achieves imbalance of 2dB and 3° up to 10-GHz. The optimized frequency shifts from 8-GHz to 6-GHz when Vtune rise from 0.3V to 0.4V.
Based on process variation, choosing the appropriate value of Vtune to minimize gain error and phase error. This circuit operates under supply voltage 1.2V with reasonable balanced outputs.
According to the DC measured result, the DC current of this proposed tunable active balun chip reduces greatly to only 0.75mA. 0.75mA is much less than post-layout simulation about 1.2mA. The DC current under Slow/Slow corner test is 0.65mA much close to the DC measured result. Fig. 3.23 shows the method to measure I_V curve of the active resister M1 to hope to find out the reason of the DC mismatch. Add a bias tee at the output 1 and measure the DC current flow through from Vdd.
Vdd
M1
V
tunebias tee V
1Fig. 3.23. Measure I_V curve of the active resister.
Fig. 3.24. Measured I_V curve of the active resister M1.
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0 0.2 0.4 0.6 0.8 1 1.2
Vsd (volt)
I (mA)
VG=0.1V VG=0.2V VG=0.3V VG=0.4V VG=0.5V
Fig. 3.24 shows the measured I_V curve of the active resister. The measured I_V curve of the active resister compares with the simulated I_V curve under the typical/typical and slow/slow corner test is shown in Fig. 3.25 (Vdd = 1.2V, Vtune = 0.3V). We can observe the measured I_V curve is even less than the simulated I_V curve under the slow/slow corner test. Fig. 3.26 shows the DC voltage at node A and node B. DC voltage gives a good agreement with simulation. The voltage at node B reduces because DC current decreases. DC current mismatch will affects the performance of the proposed tunable active balun greatly.
Fig. 3.25. The measured I_V curve of the active resister compared with the simulated IV curve under TT & SS corner test.
0 1 2 3 4 5 6
0 0.2 0.4 0.6 0.8 1 1.2 Vsd (volt)
I (mA)
Measurement Slow/Slow Typical/Typical
The measured S11 and measured S12 are shown in Fig. 3.27. S12 is better than -20dB from 0 to 5GHz. Gain difference and phase difference are shown in Fig. 3.28. As the gate voltage of the PMOS M1 rise 0.1V, gain difference and phase difference shift 1dB and 2°, respectively. The performance of this active balun is summarized in Table 3.2.
DC current VA VB
Simulation 1.2mA 1.11V 0.12V
Mea1 0.756mA 1.09V 0.067V
Mea2 0.762mA 1.09V 0.068V Mea3 0.778mA 1.09V 0.068V
A
B Vdd
in
Out1
Out2 Vtune
Fig. 3.26. DC voltage at node A and node B.
-16
Fig. 3.27. Measured S11 and Measured S12.
Fig. 3.28. Measured Gain Difference and Measured Phase Difference
-10
TABLE 3.2 Summary of measured performance and comparison to the simulated performance
Simulation Measurement
Vdd 1.2V 1.2V
Freq. 0 ~10 GHz 0 ~ 5 GHz
Max. Gain error ±2 dB ±8 dB
Max. Phase error 3° 5°
Gain Difference tunable region ±1 dB / ±0.1V ±1 dB / ±0.1V Phase Difference tunable region ±1.5° / ±0.1V ±1.75° / ±0.1V Output Loading variation region 25 ~ 200 Ω
Power consumption 1.44 mW 0.9 mW
Chapter 4
Low Power Ultra-Wideband CMOS Mixer with Active Balun
4.1 Introduction
In this chapter a mixer with an active balun is proposed for low-power and low-voltage operation. The mixer circuit is constructed in a folded configuration, while the balun in a cascoded configuration combining an NMOS and a PMOS. Thus, the total power consumption in the proposed circuit is as low as 1.5mW.
In the following sections 4.2, we first introduce the circuit design of the mixer. We also provide design analysis. In section 4.3, we will explain the circuit of the proposed mixer combined with the proposed active balun which mentioned in chapter 3.
4.2 Low Voltage 0.2-mW CMOS Mixer
Mixers are commonly used for frequency translation in Radio frequency (RF) communication systems. The frequency translation results from multiplication of the RF input signal with a “local oscillator” (LO) signal. In practice, mixers are
preferably implemented using “hard switching” via a large LO signal, which mathematically corresponds to multiplication with a square wave, instead of a sine
wave. This renders 2 dB higher conversion gain (2/π instead of 1/2) and lower noise figure. And a sufficiency of VDS (> 0.5V) achieves an IIP3 well above 0dBm.
A key problem for the realization of analog circuits in current and future digital CMOS technology is the continuously reducing supply voltage for each technology generation, resulting in nonconducting or poorly conducting switches conveying voltages in the “middle voltage range” between the supply voltages. This is a severe problem in analog and mixed analog—digital circuits exploiting switches, like A/D and D/A converters and switched capacitor circuits, but also in mixers.
Fig. 4.1 shows the schematic of the proposed CMOS mixer circuit. It consists of a modulating stage with differential-pair transistors, M5~M8, for frequency mixing, and a CMOS amplifier stage, M1~M4, for LO signal buffer. To accommodate low supply voltage, these two stages are constructed in a folded topology, rather than in a cascode configuration of the Gilbert cell. To account for the operation condition in each stage, DC biasing is blocked to each other by capacitors C3 and C4 to allow appropriate biasing in each stage.
Frequency mixing occurs at the modulating stage by utilizing the nonlinear I-V characteristic of MOS transistors, instead of switching current of the transconductance stage as in [3]. Differential RF signal is driven into the transistor gate ports while the LO signal is driven into the source ports. Actually transistors are biased in the subthreshold region, not only providing the necessary nonlinearity but also saving power consumption. It is found that this mixer functions at a supply voltage even lower than 1-V. Note that the voltage swing of LO at the source of M5~M8 must be a little smaller signal. Because if Lo at the source of M5~M8 is large signal, the propose mixer
R 4 R 5
+ IF
-M 1 M 2
M 3 M 4
V D D= 1 V
+ LO
-C 3 C 4
L 1 L 2
M 5 M 6 M 7 M 8
+ R
F-V D D= 1 F-V
R 1 R 2
M odulating stage
C M O S am plifier
Fig. 4.1 Schematic of the proposed mixer circuit.
does not operates in the subthreshold region. Actually the propose mixer operates in the saturation region at the most of time. Fig. 4.2 shows the real current (DC+AC) when the voltage swing of LO signal at the source of M5~M8 is about 0 dBm. We can observe that although the DC power consumption is very low (0.05 mW) but the actual power consumption is much higher than the DC power consumption (about 20 times lager than DC power consumption). This proposed mixer reserves the elasticity of the further mixer design for low voltage and low power. Those inductors L1 and L2 provide DC biasing paths to the modulating stage. Combined with C3 and C4, these components give high pass filtering to the LO signal and make the large LO signal to become the small LO signal. When the mixer is combined with the active balun, these components can also be further tuned to obtain flat conversion gain over the broad frequency range of interest.
The LO buffer is essentially a CMOS inverter amplifier. The typical voltage transfer characteristic is as shows in Fig. 4.2.1 Large voltage swing of LO signal makes the operation in regions I and V over the most time period. As is well known, a CMOS amplifier consumes no DC power in those regions. Consequently the time averaged power consumption in the mixer is reduced substantially. The mixer’s power consumption is only 0.2 mW.
The down-converted IF signal is taken from the double-balanced outputs of the modulating stage. The conversion gain of the mixer is proportional to load resistance of R4 and R5, and the amplitude of LO. Since the modulating stage is biased in the
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
0.0 2.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2
-0.2 1.4
time, nsec
I_Probe1.i, mA
Fig. 4.2 The real current (DC+AC) when the voltage swing of LO at the source of M5~M8 is about 0 dBm.
subthreshold region, or small biasing current, the DC voltage drop across the load resistor is very small. It is possible to apply a large resistance value to obtain high conversion gain. Further the amplitude of LO signal is swept to determine the optimized level for the suitable conversion gain.
The double-balanced output benefits noise performance as far as the noise from the CMOS amplifiers and the LO port is concerned. Such configuration generates noise output current in the common-mode form, which is rejected in the differential output.
The main noise contribution comes from the modulating stage. Operated in the subthreshold region, those transistors contribute somewhat higher noise.
Fig. 4.2.1 The voltage transfer characteristic of a CMOS amplifier.
4.3 Low Voltage 1.5-mW 6~10.6-GHz Ultra-Wideband CMOS Mixer With Active Balun
Fig. 4.3 shows the complete schematic of the proposed mixer with the active balun circuit. Two circuits are DC-blocked by capacitors C5 and C6 such that the gate port of the modulating stage in the mixer is biased properly. To increase the IIP3 of the active balun and decrease the voltage drop across the load resistors in the balun, resistors R2 and R3 are replaced by L4 and L5, which are implemented by on-chip low-Q resisters R7 and R8 for broad frequency response.
Fig. 4.3 Schematic of the proposed mixer with the proposed active balun circuit.
M13 M14 M15 M16
RFin
Gain flatness is realized by superimposing gain of the active balun and the mixer.
Although the frequency response of two circuits appears as narrow-band tuned, the composite response achieves broadband gain flatness with appropriate design. As illustrated in Fig. 4.4, the frequency response of the active balun is tuned with peaking around 6-GHz, while that of the mixer around 10-GHz. As a result, the frequency response of the mixer combined with the active balun yields to broadband gain flatness.
The load impedance at each balun output port is the same as the source. As such, the balun presents an impedance transformation ratio of 1:2. Specified for ultra-wideband application, the design is optimized at the frequency of 8-GHz for minimum phase error and gain imbalance based on Eq. (4-1).
Fig. 4.4 Illustration of broadband gain flatness, (a) conversion gain for the active balun, (b)conversion gain for the mixer, and (c) conversion gain
4.3.1 Microphotograph of Chip
The layout of the mixer with the active balun is shown in Fig. 4.5 The total chip area is 0.698mm by 1.04mm. All long interconnects should be minimized and built on the most top metal to minimize the substrate loss.
Fig. 4.5 Micrograph of the fabricated mixer with the active balun.
G
G (RFin) S
G G (LO)
G
S S
(IF+)
(IF-) VDD
VDD VDD
VDD VDD
gnd
gnd
gnd
4.3.2 Simulation and Measurement results and Discussion
Fig. 4.6 shows gain difference and phase difference at the balun outputs of node A and B in Fig 4.3. The active balun provides differential signal of the gain and phase imbalance within 0.5 dB and 1.5°, respectively, over the frequency range from 6 to 10.6-GHz. Fig 4.7 shows the measurement diagram. A unit gain output buffer is used to transform the differential signal into the signal-ended form, and provides high input impedance to reduce loading effect. Fig. 4.8 shows the measured S11. Real inductor and capacitor is larger than the TSMC model. That is why the difference between the simulated S11 and measured S11. Fig. 4.9 shows the measured conversion gain. We can observe the measured conversion gain fits the simulated conversion gain under the slow/slow corner test. The circuit achieves conversion gain of 10 dB. Gain flatness is within 1.5 dB variation. The measured IIP3 is between 2.5 to 3 dBm shown in Fig 4.10.
The measured NF is between 19 to 24 dB shown in Fig 4.11. The circuit consumes DC power level of 1.5 mW, significantly much less that of previous work. The performance summaries of the mixer and the mixer with the active balun are listed in Table 4.1 and 4.2.
178
Phase Difference Gain Difference
Fig 4.6 Gain Difference & Phase Difference at Node A and B in Fig 4.3.
Fig 4.7 Measurement diagram including unit gain output buffer
Fig. 4.8 Measured S11 -30
-25 -20 -15 -10 -5 0
4 5 6 7 8 9 10 11 12
Freq.(GHz)
S11(dB)
Measured S11 Simulated S11
Fig. 4.9 Measured Conversion Gain.
-5 0 5 10 15 20 25
4 6 8 10 12
Freq (GHz)
Conversion Gain (dB)
Measured CG
Simulated CG under T/T corner test Simulated CG under S/S corner test
1 1.5 2 2.5 3 3.5
6 7 8 9 10
Freq. (GHz)
IIP3 (dBm)
Fig. 4.10 Measured IIP3.
Fig. 4.11 Measured NF 14
16 18 20 22 24 26
6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 Freq. (GHz)
NF (dB)
Simulated NF under S/S corner test Measured NF
TABLE 4.1 PERFORMANCE SUMMARUY FOR THE MIXER
This work [3] [4]
Frequency 6~10.6GHz 0.5~6GHz 2.5 GHz Conversion Gain 14~17dB 6~10 dB 9dB
NF 15~18dB 23~27dB 12dB
IIP3 -1~1dBm 2~5dBm -1dBm
Power 0.2mW 1mW 2.8mW
TABLE 4.2 PERFORMANCE SUMMARUY FOR THE MIXER WITH THE ACTIVE BALUN
Simulation (T/T) Simulation (S/S) Measurement
Frequency 6~10.6 GHz 6~10.6 GHz 6~10.6 GHz
Conversion Gain 17 dB ± 0.5 dB 9.5 dB ± 0.5 dB 10 dB ± 1.5 dB
NF 13 ~ 16 dB 17 ~ 22 dB 19 ~ 24 dB
IIP3 0 ~ -1 dBm 2 ~ 3 dBm 2.5 ~ 3 dBm
S11 < -10 dB < -10 dB < -10 dB
Supply Voltage 1.2 V 1.2 V 1.2 V
Power 1.75mW 1.2mW 1.5mW
Chapter 5
Low-Power Front-End Circuit
5.1 Introduction
In recent years research on low-power systems is still an emergent topic in order to prolong battery lifetime. Operating at high frequencies, RF integrated circuits are critical circuit blocks to consume a high power level. The front-end circuits, including the low noise amplifier and the mixer, must be on at all times even at the standby mode. Saving power in these circuits shall significantly increase the allowed standby time.
This chapter is aimed at the low-power RF front-end circuit in wireless receivers.
For the concern of low power consumption, Direct Conversion Receiver is chosen as the system architecture. It offers great possibility of better from factor, low cost, less power consumption, and the single-chip solution. In this work, a low-voltage, low-power direct down-conversion front-end circuit is implemented. The front-end circuit includes a low noise amplifier and a direct down-conversion mixer, as shown in Fig. 5.1.
LNA Mixer
+LO-+ IF -
Fig. 5.1 The block diagram of the front-end circuit
5.2 Low Voltage 0.86mW 5 ~ 6 GHz Front-End
In this section, the design principle of the low-power front-end circuit is introduced.
Fig. 5.2 shows the schematic of the low-power front-end circuit. R is a large resister
Fig. 5.2 shows the schematic of the low-power front-end circuit. R is a large resister