INTRODUCTION - Design of a Low Power, Low Voltage and Low Phase

Chapter 4 Design of a Low Power, Low Voltage and Low Phase

4.1 INTRODUCTION

Among the building blocks of a radio frequency (RF) transceiver, the voltage-controlled oscillator (VCO) is an important block since it affects the system performance of the transceiver to a large extent. In designing a VCO, low power consumption and low phase noise are two important parameters. The low power consumption may be achieved by reducing the supply voltage and/or the current in the VCO core circuit. Forward body bias (FBB) has been proposed as an effective method for improving the device performance in MOSFETs. Forward bias the body to source voltage VBS and source to body voltage VSB of NMOS and PMOS reduce the threshold voltage (Vt). The increase in high frequency noise with ∣VBS∣ was qualitatively explained by considering the contributions from nonequilibrium channel noise and substrate resistance noise in 0.18 µm CMOS transistors.

Therefore, in RF circuit applications, an FBB scheme is not favorable if high frequency noise is an important concern [3].

However, the low voltage limits the signal amplitude, which in turn limits the signal-to-noise ratio (SNR) and leads to an increase of the phase noise of the VCO. There is a tradeoff between the VCO phase noise and power consumption due to the degradation of the phase noise with the increased VCO gain needed for a larger power consumption. Therefore,

how to control a low phase noise effectively at the low power level becomes an important and challenging issue. [4] suggests adding an external circuit called a harmonic tuned (HD) LC tank to suppress the harmonic frequency of the circuit. This method can reduce the phase noise effectively, but it also increases both the die area and power consumption.

In this chapter, a low power, low voltage and low phase noise LC-VCO circuit is proposed.

An external negative-resistance cell is also added between the different outputs, which can effectively reduce both the power consumption, supply voltage and the phase noise. The proposed LC-VCO is validated by an implementation using the TSMC 0.18 µm 1P6M process.

4.2.1 Current-reused VCO with Low Power and Low voltage

V_dd

M_p3 M_p4 Buffer Amplifier

Core circuit

Figure 4.1 Proposed VCO1 circuit.

Y

_in

L C

var

R

C

_eq

Negative -resistance cell

LC - Tank

R

_eq

Figure 4.2 Parallel LC oscillator model of the proposed VCO1.

Figure 4.3 (a) Negative-resistance cell circuit; (b) Series circuit model of the negative-resistance cell.

Our design, as shown in Fig. 4.1, adds a negative-resistance cell (Mp5 and Cgs5-Cds5) shunt to the L-C tank to a current-reuse topology (Mp1-Mn2) [8], which effectively enlarges the negative resistance and leads to the reduction of both the core power consumption, supply voltage and phase noise of the VCO. Fig. 4.2 shows a simplified equivalent circuit of the proposed VCO shown in Fig.1 in the steady state, where the resistance Rp represents the tank loss. Rc is the negative resistance created by the current-reused topology, which is

approximately equal to -(1/gmN1 + 1/gmP2). Req and Ceq, which represent the equivalent resistance and capacitance of the negative-resistance cell, are given by

2 2

where gm5 is the transconductance of Mp5, the symbols (Cgs5 , Cds5) represent the (gate-source drain-source) capacitor of pMOS Mp5 and ω is the operating frequency. They are derived by using a small-signal model as shown in Fig. 4.3(a). The series circuit mode of the cell circuit is given in Fig. 4.3(b) and then the input im

pedance of the differential negative-resistance cell, Zin = vin/iin, is given by

plify the analysis, conductance Yin is given as 1/Z

e 2 2

Thus, equations (1) and (2) are derived. By tuning W/L for MOSFET (Mp5) in the typical

design, we can easily achieve g_m₅ω²(C_gs₅+C_ds₅)²and ₅ ₅ ₂ ²⁵

Then, (1) is simplified and given by

In (5), the magnitude of the negative resistance Req is inversely proportional to the square of ω and is linearly proportional to the transconductance of Mp5 which is proportional to the transistor current. This means that the larger the frequency or the smaller current is, the larger the negative resistance is, which shows that our proposed circuit can achieve a much larger negative resistance than conventional designs in RF circuit applications. The small current flow has the advantage of a low power consumption. To analyze the effect of the negative resistance

C ≈C + (6)

on the phase noise level, the pioneering work by Hajimiri and Lee is applied to evaluate the phase noise L of the circuit at an offset frequency Δω from the carrier [5]. L is given by

with Atank being the oscillation amplitude across the resonator. Ceq is the tank capacitance, and Γrms is the root mean square value of the impulse sensitivity function (ISF). Equation (7) demons

( ) 10log( )

L Δω = (7)

trates that a larger Ceq of the resonant tank results in a lower phase noise. In (6), Cgs5

nd Cds5 are equivalent to Ceq by using a negative-resistance cell. Thus can lower the phase a

noise.

4.3 EXPERIMENTAL RESULTS

The die microphotograph of the proposed VCO is shown in Fig. 4.4, where the proposed VCO is fabricated by using the TSMC 0.18 μm CMOS process. Its die area is 0.67× 0.81 mm² including the pads. An on-wafer measurement is carried out for RF characterization. The measured oscillation frequencies cover 3.6 GHz to 3.4 GHz while the control voltage Vct is changed from 0 V to 1.3 V, as shown in Fig. 4.5. Fig. 4.6 shows the VCO output spectrum

with values of -5 dBm. As shown in Fig. 7, the measured phase noise of the proposed VCO is about -116.89 dBc/Hz at 1MHz offset frequency. The power consumption of the proposed

CO core is 0.54 mW at the supply voltage of 0.93 V. The figure

V of merit (FOM) of the

proposed VCO is -190.4 dBc/Hz with the FOM defined by

{ } ^{10 log} ^{20 log} ⁰

PDC f

FOM L f

mW f

⎛ ⎞

= Δ + × ⎜⎝ ⎟⎠− × ⎜⎝Δ ⎟⎠ (8)

where f0 is the oscillating frequency, Δf is the offset frequency, L{Δf} is the measured phase noise at Δf, and PDC is the DC power consumption of VCOs in mW. Table I summarizes the measured phase noise (PN), f0, power consumption a

⎛ ⎞

nd FOM of the proposed VCO and other ublished results. The comparison shows that our proposed work yields very low power consumption and achieve a high FOM performance.

Figure 4.4 Microphotograph of the VCO1.

Figure 4.5 Measure tuning range of the VCO1.

Figure 4.6 Measured the VCO1 output spectrum at 3.5 GHz.

Figure 4.7 Measured phase noise versus offset frequency of the VCO1 at 3.5 GHz.

TABLE I

Current-reused VCO with Low Power and Low voltage MEASURED PERFORMANCE SUMMARY AND COMPARISON

4.4 Current reused VCO with Low Power and Low Phase Noise

Figure 4.8 Proposed VCO2 circuit.

Figure 4.9 Parallel LC oscillator model of the proposed VCO2.

Figure 4.10 (a) Negative-resistance cell circuit; (b) Series circuit model of the negative-resistance cell.

e 2 5

1 2

R _q g^m

ω C C

≈ − (8)

2 1 2

5 1 2

eq m

C C C

g C C

≈ ω

+ (9)

Form (9), C1−C2 can be enlarged to Ceq by using a negative-resistance cell, and Ceq is positively correlated with (ω/gm5)² without any additional capacitance and thus can lower the phase-noise.

4.5 EXPERIMENTAL RESULTS

The die microphotograph of the proposed VCO is shown in Fig. 4.11, where the proposed VCO is fabricated by using the TSMC 0.18 μm CMOS process. Its die area is 0.56× 0.71 mm² including the pads. An on-wafer measurement is carried out for RF characterization. The measured oscillation frequencies cover 2.52 GHz to 2.41 GHz while the control voltage Vct is changed from 0 V to 1.3 V, as shown in Fig. 4.12. Fig. 4.13 shows the VCO output spectrum with values of -3.5 dBm. As shown in Fig. 4.14, the measured phase noise of the proposed VCO is about -125 dBc/Hz at 1MHz offset frequency. The power consumption of the proposed VCO core is 1.9 mW at the supply voltage of 1 V.

The figure of merit (FOM) of the proposed VCO is -190 dBc/Hz with the FOM defined by

{ } 10 log 20 log ⁰

where f0 is the oscillating frequency, Δf is the offset frequency, L{Δf} is the measured phase noise at Δf, and PDC is the DC power consumption of VCOs in mW. Table II summarizes the measured phase noise (PN), f0, power consumption and FOM of the proposed VCO and other published results. The comparison result shows that our proposed work yields very low phase noise even with a relatively low power consumption, and shows the best FOM performance.

Figure 4.11 Microphotograph of the VCO2.

Figure 4.12 Measure tuning range of the VCO2.

Figure 4.13 Measured the VCO2 output spectrum at 2.4 GHz.

Figure 4.14 Measured phase noise versus offset frequency of the VCO2 at 2.4 GHz.

50 TABLE II

Current reused VCO with Low Power and Low Phase Noise MEASURED PERFORMANCE SUMMARY AND COMPARISON

Chapter 5 Conclusion

A low power、low voltage and low phase noise LC-VCO operating at 2.5 GHz and 3.5 GHz is proposed and implemented by TSMC 0.18-μm 1P6M CMOS process. Our design, based on a current-reused topology and adding a negative-resistance cell shunt to the L-C tank, can effectively reduce of both the power consumption and supply voltage. With the current-reused topology, the proposed LC-VCO can operate using only half amount of DC current compared with the conventional topologies. An external negative-resistance cell is also added between the different outputs, which can effectively reduce both the power consumption and supply voltage. The proposed LC-VCO consumes 1.9 mW and 0.54 mW at 2.5 GHz and 3.5 GHz, respectively. The measured phase noise at 1 MHz offset frequency is -125 dBc/Hz and -116.89 dBc/Hz in the 2.5 GHz and 3.5 GHz. The FoM of proposed LC-VCO is -190 dBc/Hz and -190.4 dBc/Hz at operating frequency 2.5 GHz and 3.5 GHz, respectively. Although the power consumption is obviously improved, there is still a lot of space for noise reduction. Several extensive studies have been underway to further reduce phase noise of LC-VCOs. In this field, it may be worth our effort in the future works, such as low phase noise LC-VCOs.

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Appendix A Basic Oscillator Theory

Ring Oscillators

Ring oscillators employing more than three stages are also feasible. The total number of inversions in the loop must be odd so that the circuit does not latch up. For example, as shown in Fig A.1(a), a ring can incorporate N inverters, providing a frequency of 1/(2NTD). On the other hand, the differential implementation can utilize an even number of stages by simply configuring one stage such that it does not invert. Illustrated in Fig A.1(b), this flexibility demonstrates another advantage of differential circuits over their single ended counterparts.

1 2 3 N

Figure A.1 (a) N-stage single ended ting oscillator, (b) four-stage differential ring oscillator

Let A G R= _m _p ¹

ω = RC

Assume N is an odd number, according to Barkhausen criterion

( )^N 1 1 ( )2

H jω A ω

≥ ⇒ ≥ + ω ^∠

[

^{H j}⁽ ^ω⁾

]

^N ⁼²^k^π (3 To find minimum gain A, we have

N N

As shown in Fig A.2(a), an inductor L1 placed in parallel with a capacitor C1 resonates at a frequencyω_res =1/ L C_{1 1} . At this frequency, the impedances of the inductor, jL1ωres, and the capacitor, jC1ωres, are equal and opposite, thereby yielding an infinite impedance. We say the circuit has an infinite quality factor, Q. In practice, inductors and capacitors suffer from resistive components. For example, the series resistance of the metal wire used in the inductor can be modeled as shown in Fig A.2(b). We define the Q of the inductor as L1ω/Rs. For this circuit, the reader can show that the equivalent impedance is given by

Figure A.2 (a) Ideal and (b) realistic LC tanks

and hence,

That is, the impedance does not go to infinity at any s=jω. We say the circuit has a finite Q.

The magnitude of Zeq in (6) reaches a peak in the vicinity ofω=1/ L C_{1 1} , but the actual resonance frequency has some dependency on Rs.

The circuit of Fig A.2(b) can be transformed to an equivalent topology that more easily lends itself to analysis and design. To this end, we first consider the series combination shown in Fig A.3(a). For a narrow frequency range, it is possible to convert the circuit to the parallel configuration of Fig A.3(b). For the two impedances to be equivalent:

Considering only the steady state response, we assume s=jω and rewrite (7) as

1 1 2

(L R_p+L R j_{p s}) ω+R R_s _p−L L_pω =R L j_{p p} ω

(8) This relationship must hold for all values of ω, mandating that

1 p p s p

Figure A.3 Conversion of a series combination to a parallel combination

Calculating Rp from the latter and substituting in the former, we have

Recall that L1ω/Rs=Q, a value typically greater than 3 for monolithic inductors. Thus,

In other words, the parallel network has the same reactance but a resistance Q² times the series resistance.

Let us now consider the tuned stage of Fig A.4(a), where an LC tank operates as the load.

At resonance, jLpω=1/(jCpω) and the voltage gain equals –gm1Rp. The phase shift approach +90° at very low frequency and -90° at very high frequency. At resonance, the total phase shift around the loop is equal to 180°. Thus, the circuit does not oscillate.

Figure A.4 (a)Tuned gain stage, (b) stage of (a) in feedback

Crossed-Coupled Oscillator

Figure A.5 Two tuned stages in a feedback loop

Suppose we place two stages of Fig. A.4(a) in a cascade, as depicted in Fig. A.5.

Furthermore, at resonance, the total phase shift around the loop is zero because each stage contributes zero frequency dependent phase shift. That is, if gm1Rpgm2Rp≧1, then the loop oscillates.

The circuit of Fig. A.5 serves as the core of many LC oscillators and is sometimes drawn as in Fig. A.6(a). However, the drain currents of M1 and M2 and hence the output swings heavily depended on the supply voltage. Since the waveforms at X and Y are differential, the

drawing in Fig. A.6(a) suggests that M1 and M2 can be converted to a differential pair as depicted in Fig. A.6(b), where the total bias current is defined by Iss.

Lp Rp Cp

Figure A.6 (a) Redrawing of the oscillator shown in Fig. 8 (b) adding of tail current source to lower supply

sensitivity

The oscillator of Fig. A.6(c) is constructed in fully differential form. The supply sensitivity of the circuit is nonzero even with perfect symmetry. This because the drain junction capacitance of M1 and M2 vary with the supply voltage.

Assume Cp=0, consider only the drain junction capacitance, CDB, of M1 and M2. Since CDB

varies with the drain-bulk voltage, if VDD changes, so does the resonance frequency of the tank. Noting that the average voltage across CDB is approximately equal to VDD, we write

Note that the relationship between ωout and Vcont is nonlinear because KVCO varies with VDD and ωout.

Colpitts Oscillator

Figure A.7 (a) Colpitts oscillator (b) equivalent circuit of (a) with input stimulus

Approximating M1 by a single voltage dependent current source, we construct the equivalent circuit of Fig. A.7(b). Since the current through the parallel combination of Lp and Rp is given by Vout/(Lps)+Vout/Rp, the total current through C1 is equal to Iin-Vout/(Lps)-Vout/Rp,

The circuit oscillates if the closed-loop transfer function goes to infinity at an imaginary value of s.

We determine the ratio C1/C2 for minimum required gain. The reader can prove that the minimum occurs for C1/C2=1, requiring

(24)

m p 4 g R ≥

For cross-coupled LC-tank oscillator the minimum gain requirement (=1), (better than Colpitts oscillator). Consider the parasitic capacitance (Cp) in parallel with the inductor

Mathematical model of VCOs

Consider two waveforms V1(t) = Vm sin[φ1(t)] and V2(t) = Vm sin[φ2(t)], where φ1(t)=ω1t, Figure A.8 Variation of phase for two signals

The faster the phase of a waveform varies, the higher the frequency of the waveform, suggesting that the frequency can be defined as the derivative of the phase with respect to time:

A VCO senses a small sinusoidal control voltage Vcont=Vmcosωmt.

0 0 0 0

The output therefore consists of three sinusoids having frequency of ω0, ω0-ωm, and ω0+ωm. The spectrum is shown in Fig. A.9. The components at ω0±ωm are called “sidebands”

Figure A.9

Variation of the control voltage with time may create unwanted components at the output.

In practice, depending on the type and speed of the oscillator, the output may contain significant harmonics. If Vcont varies by ΔV, then the frequency of the first harmonic varies by KVCOΔV, the

frequency of the second harmonic varies by 2KVCOΔV.

1 0 1 2 0

( ) cos( ) cos(2 2 )

out VCO cont VCO cont

v t =V ω t K+

∫

V dt+θ +V ω t+ K

∫

V dt+θ ⁽³⁵⁾

TABLE III Comparison of oscillator topologies

Parameter Ring oscillator Colpitts LC resonator Cross-couples

Max. oscillation parasitic of at least three gates determine

Very high since minimum voltage gain as low as 1 is required

Output power Depends on output buffer

Depends on output buffer, advantage of differential following stage has to be driven, multistage

Moderate to low depends on buffer

Noise High since no high Q

frequency stabilisation Moderate to low

Moderate, noise generated in gate resonator is amplified

Low given weak loading of core by means of high impedance buffer, high voltage swing, differential inductor has higher Q Immunity against

single-ended Low since differential

Circuit size Very compact since no inductors required

Moderate, at least one differential inductor

Effect of Phase Noise in RF Communications

To understand the important of phase noise in RF systems, consider a generic transceiver as depicted in Fig. A.10, where a local oscillator provides the carrier signal for both the receive and transmit paths. If the LO output phase noise, both downconverted and

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