低功率和低電壓之電壓控制振盪器設計

國 立 交 通 大 學

電信工程學系

碩 士 論 文

低功率和低電壓之電壓控制振盪器設計

Current-reused VCO with

Low Power and Low Voltage

研 究 生：李明宗

指導教授：唐震寰 教授

Current-reused VCO with Low Power and Low Voltage

研 究 生：李明宗 Student：Ming-Tsung Li

指導教授：唐震寰 教授 Advisor：Jenn-Hwan Tarng

國 立 交 通 大 學

電 信 工 程 學 系 碩 士 班

碩 士 論 文

A Thesis

Submitted to Department of Communication Engineering College of Electrical Engineering and Computer Science

National Chiao Tung University in Partial Fulfillment of the Requirements

for the Degree of Master

in

Communication Engineering

July 2009

Hsinchu, Taiwan, Republic of China

I 

研究生：李明宗 指導教授：唐震寰

國立交通大學

電信工程學系 碩士班

摘要

本篇論文的研究焦點著重於降低電壓控制振盪器其功率消耗及相位雜訊的設計。利 用電流再利用的架構，可以使電壓控制振盪器在運作時的工作電流只需傳統型電壓控制 振盪器運作時的一半而達到低功率消耗的目的。同時，我們提出在共振腔上並聯一組負 阻電路，此方法可以有效降低功率損耗、供應電壓和相位雜訊。根據上述架構及方法， 我們完成低功率、低電壓和低相位雜訊2.5和3.5GHz之電壓控制振盪器。由量測結果 (TSMC 0.18-μm 1P6M CMOS 製程)，實作之IC均與模擬結果相近並達到預期之特性。 此設計的提供電壓和消耗功率分別為0.93V、0.54mW和1V、1.9mW，其工作頻率於 3.5GHz 和 2.5GHz 時 ， 相 位 雜 訊 在 距 離 中 心 頻 率 1 MHz 分 別 為 -116.9dBc/Hz 和 -125dBc/Hz。

II 

0.18 μm CMOS

Student：Ming-Tsung Li Advisor：Dr. Jenn-Hwan Tarng

Department of Communication Engineering

National Chiao Tung University

Abstract

The research described in this thesis focuses on the design of a low power consumption and phase noise LC-VCO. With the current-reused topology, the proposed LC-VCO can operate using only half amount of DC current compared with the conventional topologies to achieve low power consumption. Here, we also propose to add a negative-resistance cell shunt to the L-C tank, can effectively reduce of both the power consumption、supply voltage and phase noise. Based on proposed topology and novel method, we implement a low power、low voltage and low phase noise LC-VCO, which operates at 3.5/2.5 GHz. The proposed dual-band LC-VCO is implemented by TSMC 0.18-μm 1P6M CMOS process and the measured results are similar to simulation ones. Therefore, the performances of the proposed LC-VCO achieve anticipation. The measurement result of the VCO demonstrates a the power consumption and the supply voltage of its core is only 0.54 mW with 0.93 V and 1.9 mW with 1 V, the proposed LC-VCO operates 3.5 GHz and 2.5 GHz with phase noise of -116.9 dBc/Hz and -125 dBc/Hz, respectively, at 1 MHz offset frequency.

III  在碩士班研究的這二年歲月，首先要感謝的是我的指導教授 唐震寰教授並致上我 最誠摯的謝意。感謝老師在專業的通訊領域中，給予我不斷的指導與鼓勵，並賦予了實 驗室豐富的研究資源與環境，使得這篇碩士論文能夠順利完成。同時，亦感謝口試委員 國立臺灣大學 李學智教授及國立臺灣科技大學 楊成發教授對於論文內容所提出的 寶貴建議及指導，在此致上最誠懇的謝意。 其次，要感謝波散射與傳播實驗室的學長們—佩宗學長、清標學長、俊諺學長、雅 仲學長、豐吉學長、奕慶學長、威璁學長、智偉學長、稟文學長、文崇學長、瑞榮學長 等在研究上的幫助與意見，讓我獲益良多。感謝實驗室的同學—振銘、廣琪、兆凱等在 課業及研究上的互相砥礪與切磋，以及生活上的多彩多姿。亦感謝學弟們—冠豪、國政、 鉦浤、耿賢等，讓實驗室在嚴肅的研究氣氛中增添了許多歡樂，有了你們，更加豐富了 我這二年的研究生生活。另外，也要感謝助理—梁麗君小姐，在實驗室上的協助和籌劃 每次的美食聚餐饗宴。 最後，要感謝的就是我最親愛的家人。他們在我求學過程中，一路陪伴著我，給予 我最溫馨的關懷與鼓勵，讓我在人生的過程裡得到快樂，更讓我可以專心於研究工作中 而毫無後顧之憂。 鑒此，謹以此篇論文獻給所有關心我的每一個人。 李明宗 誌予 九十八年七月

Abstract (Chinese)

...

Ⅰ

Abstract (English)

...

II

Acknowledgement

...

III

Table of Contents

...

IV

List of Tables

...

VII

List of Figures

...

VIII

Chapter 1 Introduction

1

1.1 Background and Problems ... 1

1.2 Related Works and Motivation ... 3

1.3 Thesis Organization ... 4

Chapter 2 Design Basics of CMOS VCO

5

2.1 General Consideration ... 5

2.2 One port oscillator ... 7

2.3 Negative-R LC Oscillator ... 9

2.4 Voltage-Controlled Oscillator ... 10

2.6 Tuning Range ... 11

2.7 Output Power ... 12

2.8 Harmonic Rejection ... 12

2.9 Power Consumption ... 13

2.10 Phase Noise... 13

Chapter 3 Review of Low Power and Low Phase Noise designs

30

3.1 Low Power VCO Design in CMOS ... 30

3.2 Low Phase Noise Design in CMOS ... 34

Chapter 4 Design of a Low Power, Low Voltage and Low Phase

Noise VCO 35

4.1 INTRODUCTION ... 37

4.2 Current-reused VCO with Low Power and Low Voltage ... 38

4.3 EXPERIMENTAL RESULTS ... 41

4.4 Current-reused VCO with Low Power and Low Phase Noise ... 45

4.5 EXPERIMENTAL RESULTS ... 47

References

... 52

Appendix A Basic Oscillator Theory ... 54

VII 

TABLE I Current-reused VCO with Low Power and Low voltage MEASURED

PERFORMANCE SUMMARY AND COMPARISON ... 44 TABLE II Current reused VCO with Low Power and Low Phase Noise MEASURED

PERFORMANCE SUMMARY AND COMPARISON ... 50 TABLE III Comparison of oscillator topologies ... 64

VIII 

Figure 1.1 Block diagram of a typical RF front-end transceiver ... 2

Figure 2.1 Feedback system ... 5

Figure 2.2 Evolution of oscillatory system with times ... 5

Figure 2.3 Various views of oscillatory feedback system ... 7

Figure 2.4 (a) Decaying impulse response of a tank, (b) addition of negative resistance to cancel loss in Rp, (c) use of an active circuit to provide negative resistance ... 8

Figure2.5 (a) Source follower with positive feedback to create negative input impedance, (b) equivalent circuit if (a) to calculate the input impedance ... 8

Figure 2.6 Oscillator using negative input resistance of a source follower with positive feedback ... 9

Figure 2.7 (a) Redrawing of the topology shown in Fig. 2.6, (b) differential version of (a), (c) Equivalent circuit of Fig. 2.7(b) ... 10

Figure 2.8 Definition of a VCO ... 10

Figure 2.9 Nonlinear VCO characteristic ... 12

Figure 2.10 Frequency spectrum of ideal and real oscillators ... 13

Figure 2.11 Jitter in the time domain relates to phase noise in the frequency domain ... 14

Figure 2.12 Oscillator output power spectrum ... 14

Figure 2.13 Phase noise: Leeson versus (18) ... 18

Figure 2.14 Equivalent systems for phase and amplitude ... 18

Figure 2.15 Impulse response of an ideal LC oscillator ... 19

Figure 2.16 Bose oscillator with parallel perturbation current source ... 20

Figure 2.17 The waveform of the Bose oscillator shown in Figure 3 ... 20

Figure 2.20 The equivalent system for ISF decomposition ... 23

Figure 2.21 Conversion of a low frequency sinusoidal current to phase ... 24

Figure 2.22 Conversion of a tone in the vicinity of ω0 ... 25

Figure 2.23 Evolution of circuit noise into phase noise ... 27

Figure 2.24 (a) Waveform and ISF for the symmetric waveform (b) the asymmetric waveform ... 29

Figure 3.1 Schematic of the FBB ... 31

Figure 3.2 I-V characteristics of the MOSFET with and without FBB ... 31

Figure 3.3 Schematic of the DTMOS ... 32

Figure 3.4 I-V characteristics of the MOSFET with and without DTMOS ... 32

Figure 3.5 Schematic of the Current-Reuse VCO ... 33

Figure 3.6 Simplified schematic diagrams of optimized HT VCO. ... 34

Figure 3.7 Simulated phase-noise results for each technique ... 35

Figure 3.8 Channel noise 2 d i against drain current IDS as a function of body bias VBS. (a) NMOS. (b) PMOS ... 36

Figure 4.1 Proposed VCO circuit ... 38

Figure 4.2 Parallel LC oscillator model of the proposed VCO ... 39

Figure 4.3 (a) Negative-resistance cell circuit; (b) Series circuit model of the negative-resistance cell ... 39

Figure 4.4 Microphotograph of the VCO ... 42

Figure 4.5 Measure tuning range of the VCO ... 43

Figure 4.6 Measured the VCO output spectrum at 3.5 GHz ... 43

Figure 4.7 Measured phase noise versus offset frequency of the VCO at 3.5 GHz ... 44

Figure 4.8 Proposed VCO circuit. ... 45

Figure 4.9 Parallel LC oscillator model of the proposed VCO. ... 45

X 

negative-resistance cell. ... 46

Figure 4.11 Microphotograph of the VCO. ... 48

Figure 4.12 Measure tuning range of the VCO. ... 48

Figure 4.13 Measured the VCO output spectrum at 2.4 GHz ... 49

Figure 4.14 Measured phase noise versus offset frequency of the VCO at 2.4 GHz ... 49

Figure A.1 (a) N-stage single ended ting oscillator, (b) four-stage differential ring oscillator ... 54

Figure A.2 (a) Ideal and (b) realistic LC tanks ... 56

Figure A.3 Conversion of a series combination to a parallel combination ... 57

Figure A.4 (a)Tuned gain stage, (b) stage of (a) in feedback ... 58

Figure A.5 Two tuned stages in a feedback loop ... 58

Figure A.6 (a) Redrawing of the oscillator shown in Fig. 8 (b) adding of tail current source to lower supply sensitivity ... 59

Figure A.7 (a) Colpitts oscillator (b) equivalent circuit of (a) with input stimulus ... 60

Figure A.8 Variation of phase for two signals ... 62

Figure A.9 Spectrum ... 63

Figure A.10 Generic wireless transceiver ... 65

Figure A.11 (a) Downconversion by an ideal oscillator, (b) reciprocal mixing ... 66

1 

Chapter 1 Introduction

1.1 Background and Problems

In recent years, the development of several kinds of new communication technique is expected to provide high data rate, wide range and high speed communications in wireless area networks [1]. As the advancement of wireless communication system, transmission distance and data rate growing rapidly, the design of high performance radio frequency (RF) transceivers is an aspiration target.

At present, RF transceivers have been widely implemented by SiGe, GaAs or HBT processes due to the high performance at high frequency. However, the system cost will remain high because that those processes are not compatible with the silicon process and let along of a system on a chip (SOC) solution for the present time. Thus, the CMOS technology is an attractive process to meet the low cost requirement in RF transceivers.

Among function blocks of a RF transceiver as shown in Fig 1.1, the voltage controlled oscillator (VCO) is used to provide clean, stable, and precise carrier signals for frequency

2 

translation in wireless transceivers. Because the purity (phase noise) of local signal which generated by the VCO will dominate the performance of the system, the design of high performance VCO is an urgent and momentous subject. In the design of VCOs, there are several common goals, such as low phase noise, low power consumption, low cost, satisfactory output power, and sufficient tuning range. Mostly, the low phase noise is a critical specification of VCOs for actual practice. As the shrinking of chip size and the growing demand of portable applications and power-efficient issues, the low voltage and low power design is another important target of VCOs. However, according to the well-known Leeson’s model of phase noise [2], the phase noise and power consumption usually formed a key tradeoff in the circuit design of VCOs. Hence, how to design a VCO that satisfies the requirements described above is a challenging issue.

LNA PA Mixer Mixer LO Baseband Baseband

Duplexer

or

Switch

Antenna

Figure 1.1Block diagram of a typical RF front-end transceiver

3 

1.2 Related Works and Motivation

In designing a VCO, low power consumption and low phase noise are two important parameters. The low power consumption may be achieved by reducing the supply voltage and/or the current in the VCO core circuit. Forward body bias (FBB) has been proposed as an effective method for improving the device performance in MOSFETs. Forward bias the body to source voltage VBS and source to body voltage VSB of NMOS and PMOS reduce the

threshold voltage (Vt). The increase in high frequency noise with VBS was qualitatively

explained by considering the contributions from nonequilibrium channel noise and substrate resistance noise in 0.18 μm CMOS transistors. Therefore, in RF circuit applications, an FBB scheme is not favorable if high frequency noise is an important concern [3]. However, the low voltage limits the signal amplitude, which in turn limits the signal-to-noise ratio (SNR) and leads to an increase of the phase noise of the VCO. There is a tradeoff between the VCO phase noise and power consumption due to the degradation of the phase noise with the increased VCO gain needed for a larger power consumption. Therefore, how to control a low phase noise effectively at the low power level becomes an important and challenging issue. [4]

suggests adding an external circuit called a harmonic tuned (HD) LC tank to suppress the harmonic frequency of the circuit. This method can reduce the phase noise effectively, but it also increases both the die area and power consumption. In conclusion, how to obtain a comparable phase noise effectively at the low power level becomes a bottleneck to design.

In this thesis, low power 、 low voltage and low phase noise LC-VCO by the negative resistance enhancement method in a current-reused VCO. In the VCO design, achieving the goal of low power or low voltage may not be a difficulty. The real problem is the phase noise performance is considerably poor at low power level. On the other hand, the bottleneck is how to improve the phase noise of VCOs at low voltage or low power operation. The negative

4 

resistance enhancement method employs a PMOS shunt to the LC-tank, can reduce both the power consumption and the phase noise effectively.

1.3 Thesis Organization

The thesis is organized into five chapters including the introduction. Chapter 2 deals with the basic concepts of VCO design, its metrics and some popular voltage-controlled oscillator (VCO) topologies. In chapter 3, some advanced popular VCO topologies are reviewed. In chapter 4, we design the low phase noise low power consumption dual-band VCO with the simulated and measured results. Chapter 5 conclusion is drawn.

5 

Chapter 2

Basics of CMOS VCO

2.1 General Consideration

A simple oscillator produces a periodic output, usually in the form of voltage. As such, the circuit has no input while sustaining the output indefinitely. How can a circuit oscillate? Consider the unity gain negative feedback circuit shown in Fig. 2.1, where

( ) ( ) 1 ( ) out in V _s H s V = +H s (1)

If the amplifier itself experiences so much phase shift at high frequencies that the overall feedback becomes positive, then oscillation may occur. More accurately, if for s=jω0,

H(jω)=‐1, then the closed loop gain approach infinity at ω0 indefinitely. In fact, as

conceptually illustrated in Fig. 2.2, a noise component at ω0 experiences a total gain of unity

and a phase shift of 180°, returning to the subtractor as a negative replica of the input. Upon subtraction, the input and the feedback signals give a lager difference. Thus, the circuit continues to “regenerate,” allowing the component at ω0 to grow.

6 

Figure 2.2 Evolution of oscillatory system with time

For the oscillation to begin, a loop gain of unity or greater is necessary. This can be seen by following the signal around the loop over many cycles and expressing the amplitude of the subtractor’s output in Fig. 2.2 as geometric series (if ∠H(jω)=180°):

2 3

0 ( 0) 0 ( 0) 0 ( 0) 0

X

V =V + H jω V + H jω V + H jω V + ⋅⋅⋅ (2)

If H j( ω0) > 1, the above summation diverges whereas if H j( ω0) <1, then 0 0 1 ( ) X V V H jω = < ∞ − (3)

In summary, if a negative feedback circuit has a loop gain that satisfies two conditions:

0 ( ) H jω ≥ 1 (4) 0 ( ) 180 H jω ∠ = ° (5)

then the circuit may oscillate at ω0, which is Called “Barkhausen criteria.” These conditions

are necessary but not sufficient. In order to ensure oscillation in the presence of temperature and process variations, we typically choose the loop gain to be at least twice or three times the required value.

We may state the second Barkhausen critertion as ∠H j( ω₀) 180= °or a total phase shift of 360°. This should not be confusing: if the system is designed to have a low frequency negative feedback, it already produces 180° of phase shift in the signal traveling around the loop in Fig 2.1, and ∠H j( ω0) 180= ° denotes an additional frequency dependent phase shift

that, as illustrated in Fig 2.2, ensures the feedback signal enhances the original signal. Thus, three illustrated in Fig 2.3 are equivalent in terms of the second criterion. We say the system of Fig 2.3 exhibits a frequency dependent phase shift of 180°. The difference between Figs.

7 

2.3(b) and (c) is that the open loop amplifier in the former contains enough stages with proper polarities a total phase shift of 360° at ω0 whereas that in the latter produces no phase shift at

ω0.

Figure 2.3 Various views of oscillatory feedback system

2.2 One port oscillator

An alternative view that provides more insight into the oscillation phenomenon employs the concept of “negative resistance.” To arrive at this view, let us first consider a simple tank that is stimulated by a circuit impulse Fig. 2.4(a). The tank responds with a decaying

oscillatory behavior because, in every cycle, some of the energy that reciprocates between the capacitor and the inductor is lost in the form of heat in the resistor. Now suppose a resistor equal to –Rp is placed in parallel with Rp and experiment is repeated Fig. 2.4(b). Since

Rp∥(-Rp)=∞, the tank oscillates indefinitely. Thus, if a one port circuit exhibiting a negative

resistance is placed in parallel with a tank Fig. 2.4(c), the combination may oscillate. Such a topology is called a one port oscillator.

8 

Figure 2.4 (a) Decaying impulse response of a tank, (b) addition of negative resistance to cancel loss in Rp, (c)

use of an active circuit to provide negative resistance.

How can a circuit provide a negative resistance? Recall that feedback multiplies or divides the input and output impedances of circuits by a factor equal to one plus the loop gain. Thus, if the loop gain is sufficiently negative, (i.e., the feedback is sufficiently positive), a negative resistance is achieved.

Figure 2.5 (a) Source follower with positive feedback to create negative input impedance, (b) equivalent circuit if (a) to calculate the input impedance

9 

For feedback system

1 ( in R R T s = + ) V , Rin becomes negative as T(s) < -1 2 1 X m I = −g (6) 1( X m g X) I =g V −V (7) 1 2 1 1 2 ( ) X X m m V I = − g +g = −g_m (if gm1=gm2=gm) (8)

2.3 Negative-R LC Oscillator

With a negative resistance available, we can now construct an oscillator as illustrated in Fig. 2.6. Here, Rp denotes the equivalent parallel resistance of the tank and, for oscillation

build-up, Rp-2/gm ≧ 0.

Figure 2.6 Oscillator using negative input resistance of a source follower with positive feedback

More interestingly, the circuit can be redrawn as in Fig. 2.7(a), bearing a resemblance to Fig. A.6(b). in fact, if the drain current of M1 flows through a tank and resulting voltage is

10 

Figure 2.7 (a) Redrawing of the topology shown in Fig. 2.6, (b) differential version of (a), (c) Equivalent circuit of Fig. 2.7(b)

For oscillation build-up 2Rp-2/gm ≧ 0, Rp≧1/gm.

2.4 Voltage-Controlled Oscillators

Most applications require that oscillators be “tunable,” i.e., their output frequency be a function of a control input, usually a voltage. An ideal voltage-controlled oscillator is a circuit whose output frequency is a linear function of its control voltage (Fig. 2.8):

0

out kVCO contV

ω =ω + (9)

Here, ω0 represents the intercept corresponding to Vcont=0 and KVCO denotes the “gain” or

“sensitivity” of the circuit (expressed in rad/s/V). The achievable range, ω2-ω1, is called the

“tuning range.”

11 

2.5 Center Frequency

The center frequency ( i.e., the midrange value in Fig. 2.8) is determined by the environment in which the VCO used.

2.6 Tuning Range

The required tuning range is dictated by two parameters: (1) the variation of the VCO center frequency with process and temperature and (2) the frequency range necessary for the application. The center frequency of some CMOS oscillator may vary by a factor of two at the extreme of process and temperature, thus mandating a sufficiently wide (≧2) tuning range to guarantee that the VCO output frequency can be driven to the desired value.

An important concern in the design of VCOs is the variation of the output phase and frequency as a result of noise on the control line. For a given noise amplitude, the noise in the output frequency is proportional to KVCO because ωout=ω0+KVCOVcont. Thus, to minimize the

effect of noise in Vcont, the VCO gain must be minimized, a constraint in direct conflict with

the required tuning range. In fact, if, as shown in Fig. 2.8, the allowable range of Vcont is from

V1 to V2 (e.g., from 0 to VDD) and the tuning range must span at least ω1 to ω2, then KVCO

must satisfy the following requirement:

2 1 2 1 VCO K V V ω −ω ≥ − (10)

Note that, for a given tuning range, KVCO increase as the supply voltage decreases, making

the oscillator more sensitive to noise on the control line. Tuning Linearity

As exemplified by Eq. (A.16), the tuning characteristics of VCOs exhibit nonlinearity, i.e., their gain, KVCO, is not constant. Nonlinearity degrades the settling behavior of phase-locked

loops. For this reason, it is desirable to minimize the variation of KVCO across the tuning range.

Actual oscillator characteristics typically exhibit a high gain region in the middle of the range and a low gain at the two extremes (Fig. 2.9). Compared to a linear characteristic (the gray

12 

line), the actual behavior displays a maximum gain greater than that predicted by (10), implying that, for a given tuning range, nonlinearity inevitably leads to higher sensitivity for some region of the characteristic.

Figure 2.9 Nonlinear VCO characteristic

2.7 Output Power

In general, it is not easy to predict the output power of the realistic VCO, but we can know that the maximum output power of VCO is not larger than the output power of the transistor in the VCO through large-signal analysis. The output power must be maximized in order to make the waveform less sensitive to noise or to lower phase noise. It trades with power consumption, supply voltage, and tuning range. The designer can choose the active devices whose parameter is known. Therefore, when the VCO is designed, we also can predict the output power of the VCO.

2.8 Harmonic Rejection

The VCO has a good harmonic rejection performance that means it is closed to a sinusoidal output waveform. In wireless communication systems, harmonic rejection is specified how much smaller the harmonics of the output signal are compared with the fundamental output power.

13 

2.9 Power Consumption

With fast growth in the radio-frequency (RF) wireless communications market, the demand for low-power and high-performance but low-cost RF solutions is rising. Low–power operation can extend the lifetime of the battery and save money for consumers.

2.10 Phase Noise

Noise injected into an oscillator by its constituent devices or by external means may influence both the frequency and the amplitude of the output signal. In most cases, the disturbance in the amplitude is negligible or unimportant, and only the random deviation of the frequency is considered.

For a nominally periodic sinusoidal signal, we can write x(t)=Acos[fct+φn(t)], where φn(t)

is a small random excess phase representing variations in the period. The function φn(t) is

called “phase noise”. Note that for∣φn(t)∣<<1 rad, we have x(t)≒Acosfct-Aφn(t) sinfct; that

is, the spectrum of φn(t) is translated to ±fc.

In RF applications, phase noise is usually characterized in the frequency domain. For an ideal sinusoidal oscillator operating at fc, the spectrum assumes the shape of an impulse,

whereas for an actual oscillator, the spectrum exhibits “skits” around the carrier frequency (Fig. 2.10). The frequency fluctuations correspond to jitter in the time domain, which is a random perturbation of zero crossings of a periodic signal (Fig. 2.11).

14 

Figure 2.11 Jitter in the time domain relates to phase noise in the frequency domain

Frequency fluctuations are usually characterized by the single sideband noise spectral density normalized to the carrier signal power (Fig. 2.10). It is defined as

( ,1 ( , ) 10 log sideband c c carrier P f f Hz L f f P ) ⎡ + Δ ⎤ Δ = _{⎢ ⎥} ⎣ ⎦ (11)

and has units of decibels below the carrier per hertz (dBc/Hz). Pcarrier is the carrier signal

power at the carrier frequency fC and Psideband(fc+Δf, 1 Hz) denotes the single sideband power

at the offset Δf from the carrier fC at a measurement bandwidth of 1 Hz.

15 

The typical oscillator output power spectrum is shown in Fig. 2.12. The noise distribution on each side of the oscillator signal is subdivided into a larger number of strips of width Δf located at the distance fm away from the single. It should be noted that, generally, the

spectrum of the output single consists of the phase noise components. Hence, to measure the phase noise close to the carrier frequency, one needs to make sure that any contributions of parasitic amplitude modulation to the oscillator output noise spectrum are negligible compared with those from frequency modulation. The single sideband phase noise L(fm)

usually given logarithmically is defined as the ratio of signal power PssΔf in one phase

modulation sideband per bandwidth Δf=1 Hz, at an offset fm away from the carrier, to the total

signal power Ps.

Time invariant model

In this section, phase noise analysis is described by using time invariant model. Time invariant means whenever noise sources injection, the phase noise in VCO is the same. In the other words, phase shift of VCO caused by noise is the same in any time. Therefore, it’s no need to consider when the noise is coming. Suppose oscillator is consists of amplifier and resonator. The transfer function of a band-pass resonator is written as

( )

2 1 1 1 j RC H j j LC RC ω ω ω ω = + − (12)

The transfer function of a common band-pass is written as

( )

0 2 0 2 0 j Q H j j Q ω ω ω _ω ω ω ω = + − (13)

Compare equation (12) with (13). Thus,

0

1

LC

16 

The frequency ω ω= ₀+ Δω which is near oscillator output frequency. If ω₀ Δω, we can use Taylor expansion for only first and second terms. Hence

( )

0 2 1 H j j Q ω ≈ + _ω ⋅ Δω (15)

The close-loop response of oscillator is expressed by

( )

_{( )}

0 1 1 2 j Q G j H j ω ω ω ω − = ≈ − ⋅ Δ (16)

When input noise density isS_i

( )

ω , the output noise density is

( )

( ) ( )

2 ₀ 2 0 2 i S S G FkT Q ω ω ω ω ω ⎛ ⎞ = = _⎜ Δ ⎝ ⎠⎟ (17)

The above equation is double sideband noise. The phase noise faraway center frequency

ω Δ can be expressed by

( )

_{10 log} 2 0 2 2 S FkT L P Q ω ω ω ⎡ _{⎛ ⎞} ⎤ Δ = ⎢ ⋅_{⎜ ⎟} ⎥ Δ ⎢ ⎝ ⎠ ⎥ ⎣ ⎦ (18) Where F is empirical parameter (“often called the device excess noise number”), k is

Boltzman’ s constant, T is the absolute temperature, PS is the average power dissipated in the

resistive part of the tank, ω₀ is the oscillation frequency, and Q is the effective quality factor of the tank with all the loading in place(also known as loaded Q). From equation (18), increasing power consumption and higher Q factor can get better phase noise. Increasing power consumption means increasing the power of amplifier. This method will decrease noise figure (NF) and improve phase noise.

From, equation (18), we can briefly understand phase noise. But the equation and actual measured results are different. The VCO spectrum is shown as Fig. 2.12. The phase noise equation can be modified as the same as equation (31) that is called Lesson’s model [5].

17 

( )

3 2 ₁ 0 2 10log 1 1 2 f S FKT L P Q ω ω ω ω ω ⎧ _{⎡ ⎛ ⎞ ⎤} ⎡ Δ ⎤⎫ ⎪ _{⎢ ⎥}⎪ Δ = _⎨ ⋅ +⎢ _{⎜ ⎟} ⎥⋅ +_{⎢ ⎥⎬} Δ Δ ⎢ ⎝ ⎠ ⎥ ⎪ _{⎣ ⎦ ⎢⎣ ⎥⎦}⎪ ⎩ ⎭

These modifications, due to Leeson, consist of a factor to account for the increased noise in the _1/(Δω)2 _{region, an additive factor of unity (inside the braces) to account for the noise}

floor, and a multiplicative factor (the term in the second set of parentheses) to provide a

3

1/ Δω behavior at sufficiently small offset frequencies. With these modifications, the phase-noise spectrum appears as in Fig. 2.13.

It is important to note that the factor F is an empirical fitting parameter and therefore must be determined from measurements, diminishing the predictive power of the phase-noise equation. Furthermore, the model asserts that Δω_{1/ f}3, the boundary between the

2

1/(Δω) and 1/ Δω3 regions, is precisely equal to the 1/f corner of device noise. However, measurements frequently show no such equality, and thus one must generally treat Δω_{1/ f}3 as

an empirical fitting parameter as well. Also, it is not clear what the corner frequency will be in the presence of more than one noise source with 1/f noise contribution. Last, the frequency at which the noise flattens out is not always equal to half the resonator bandwidth, ω₀/ 2Q. Both the ideal oscillator model and the Leeson model suggest that increasing resonator Q and signal amplitude are ways to reduce phase noise. The Leeson model additionally introduces the factor F, but without knowing precisely what it depends on, it is difficult to identify specific ways to reduce it. The same problem exists with Δω_{1/ f}3 as well. Last, blind

application of these models has periodically led to earnest but misguided attempts to use active circuits to boost Q. Sadly, increases in Q through such means are necessarily accompanied by increases in F as well, preventing the anticipated improvements in phase noise. Again, the lack of analytical expressions for F can obscure this conclusion, and one

18 

continues to encounter various doomed oscillator designs based on the notion of active Q boosting.

Figure 2.13 Phase noise: Leeson versus (18).

Time Variant

In the general case, multiple noise sources affect the phase and amplitude of an oscillator. This chapter begins by investigating the effect of a single noise source on the amplitude and phase of the oscillator.

Figure 2.14 Equivalent systems for phase and amplitude

Since each input source generally affects both amplitude and phase, a pair of equivalent systems, one each for amplitude and phase, can be defined. Each system can be viewed as a single-input, single-output system as shown in Fig. 2.14. The input of each system in Fig.

19 

2.14 is a perturbation current (or voltage) and the outputs are the excess phase, φ(t), and amplitude, A(t). Both systems shown in Fig. 2.14 are time-variant as shown by the following examples.

The first example is an ideal parallel LC tank oscillating with voltage amplitude, as shown in Fig. 2.15. If one injects an impulse of current at the voltage maximum, only the voltage across the capacitor changes; there is no effect on the current through the inductor. Therefore, the tank voltage changes instantaneously, as shown in Fig. 2.15. Assuming a voltage- and time-invariant capacitor, the instantaneous voltage change ΔV is given by

total q V C Δ Δ = (19)

where Δq is the total charge injected by the current impulse and Ctotal is the total capacitance

in parallel with the current source. It can be seen from Fig. 2.15 that the resultant change in

A(t) and φ(t) is time dependent. In particular, if the impulse is applied at the peak of the

voltage across the capacitor, there will be no phase shift and only an amplitude change will result, as shown in Fig. 2.15(a). On the other hand, if this impulse is applied at the zero crossing, it has the maximum effect on the excess phase, φ(t), and the minimum effect on the amplitude, as depicted in Fig. 2.15(b).

Figure 2.15 Impulse response of an ideal LC oscillator

20 

relaxation oscillator known as the Bose oscillator is shown in Fig. 2.16. It consists of a Schmitt-trigger inverter and an RC circuit. The hysteresis in the transfer function of the inverter and the RC time constant determine the frequency of oscillation. The resulting capacitor voltage waveform is shown with a solid line in Fig. 2.17.

As before, imagine an impulsive current source in parallel with the capacitor, injecting charge at t=τ, as shown in Fig. 2.16. All of the injected charge goes into the capacitor and changes the voltage across it instantaneously. This voltage change, ΔV, results in a phase shift, Δφ, as shown in Fig. 2.17. As can be seen from Fig. 2.17, for a small area of the current impulse (injected charge), the resultant phase shift is proportional to the voltage change, ΔV, and hence to the injected charge, Δq. Therefore, Δφ can be written as

0 0 max max ( ) V ( ) q V q φ ω τ Δ ω τ Δ Δ = Γ = Γ Δ q q_max (20)

Figure 2.16 Bose oscillator with parallel perturbation current source

21 

where Vmax is the voltage swing across the capacitor and qmax=CnodeVmax is the maximum

charge swing. The function, Γ(x) is the time-varying “proportionality factor”. It is called the

impulse sensitivity function (ISF), since it determines the sensitivity of the oscillator to an

impulsive input. It is a dimensionless, frequency- and amplitude-independent function periodic in 2π that describes how much phase shift results from applying a unit impulse at any point in time.

In any event, to develop a feel for typical shapes of ISF’s, consider two representative examples, first for an LC and a ring oscillator in Fig. 2.18(a) and (b).

Figure 2.18 Example ISF for (a) LC oscillator and (b) ring oscillator.

It is critical to note that the current-to-phase transfer function is linear for small injected charge, even though the active elements may have strongly nonlinear voltage current behavior. It should also be noted that the linearity and time-variance of a system depends on both the characteristics of the system and its input and output variables. The linearization of the current-to-phase system of Fig. 2.14 does not imply linearization of the nonlinearity of the voltage-current characteristics of the active devices. In fact, this nonlinearity affects the shape of the ISF and therefore has an important influence on phase noise, as will be seen shortly.

22 

Noting that the introduced phase shift persists indefinitely, the unity phase impulse response can be easily calculated from (20) to be

0 max ( ) ( , ) ( ) h t u t q ω τ τ τ Φ Γ = − (21)

where u(t) is the unit step.

Thanks to linearity, the output excess phase, φ(t), can be calculated for small charge injections using the superposition integral

0 max ( ) ( ) ( , ) ( ) ( ) t t h t i d i d q φ ω τ φ τ τ τ τ τ +∞ −∞ −∞ Γ =

∫

=

∫

(22)

where i(t) represents the input noise current injected into the node of interest. Equation (22) is one of the most important results of this section and will be referred to frequently.

The output voltage, V(t), is related to the phase, φ(t), through a phase modulation process. Thus the complete process by which a noise input becomes an output perturbation in V(t) can be summarized in the block diagram of Fig. 2.19. The essential features of the block diagram of Fig. 2.19 are a modulation by a periodic function, an ideal integration and a nonlinear phase modulation. The complete process thus can be viewed as a cascade of an LTV system that converts current (or voltage) to phase, with a nonlinear system that converts phase to voltage.

Figure 2.19 The equivalent block diagram of the process.

Since the ISF is periodic, it can be expanded in a Fourier series

0 0 0 1 ( ) _ncos( n c c n _n) ω τ ∞ = Γ = +

∑

ω τ θ+ (23)

23 

where the coefficients cn are real-valued, and θn is the phase of the nth harmonic. As will be

seen later, θn is not important for random input noise and is thus neglected here. Using the

expansion in (23) for Γ(ω0τ) in the superposition integral and exchanging the order of

summation and integration, the following is obtained:

0 max 1 1 ( ) ( ) ( ) cos( ) t t n n t c i d c i n q 0 d φ τ τ ∞ τ ω τ τ = −∞ − ⎡ ⎤ ⎢ ⎥ = + ⎢ ⎥ ⎣

∫

∑

∫

= ⎦ (24) Equation (24) identifies individual contributions to the total φ(t) for an arbitrary input current

i(t) injected into any circuit node, in terms of the various Fourier coefficients of the ISF. The

decomposition implicit in (24) can be better understood with the equivalent block diagram shown in Fig. 2.20.

Each branch of the equivalent system in Fig. 2.20 acts as a bandpass filter and a downconverter in the vicinity of an integer multiple of the oscillation frequency. For example, the second branch weights the input by c1, multiplies it with a tone at ω0 and integrates the

product. Hence, it passes the frequency components around ω0 and downconverts the output

to the baseband. As can be seen, components of perturbations in the vicinity of integer multiples of the oscillation frequency play the most important role in determining φ(t).

Figure 2.20 The equivalent system for ISF decomposition

To investigate the effect of low frequency perturbations on the oscillator phase, a low frequency sinusoidal perturbation current, i(t), is injected into the oscillator at a frequency of Δω  ω0 :

24  0

( ) cos( )

i t =I Δωt (25)

Figure 2.21 Conversion of a low frequency sinusoidal current to phase

where I0 is the amplitude of i(t). The arguments of all the integrals in (24) are at frequencies

higher than Δω and are significantly attenuated by the averaging nature of the integration, except the term arising from the first integral, which involves c0. Therefore, the only

significant term in φ(t) will be

0 0 0 0 max max sin( ) ( ) cos( ) t I c I c t d q t q ω φ ωτ τ ω −∞ Δ ≈ Δ = Δ

∫

(26)

As a result, there will be two impulses at ±Δω in the power spectral density of φ(t), denoted as Sφ(ω) as shown in Fig. 2.21.

As another important special case, consider a current at a frequency close to the oscillation frequency given by

1 0 ( ) cos ( )

i t =I ⎡_⎣ω + Δωt⎤_⎦ (27)

A process similar to that of the previous case occurs except that the spectrum of i(t) consists of two impulses at ±(ω0+Δω) as shown in Fig. 2.22. This time the dominant term in

25 

Figure 2.22 Conversion of a tone in the vicinity of ω0

by 1 1 max sin( ) ( ) 2 I c t t q ω φ ω Δ ≈ Δ (28)

which again results in two equal sidebands at ±Δω in Sφ(ω).

More generally, (24) suggests that applying a current, i t( )=Incos (⎣⎡nω0+ Δω)t⎤⎦, close to any

integer multiple of the oscillation frequency will result in two equal sidebands at ±Δω in Sφ(ω). Hence, in the general case φ(t) is given by

max sin( ) ( ) 2 n n I c t t q ω φ ω Δ ≈ Δ (29)

for n≠0. For n=0, phase is given by (26).

Unfortunately, we are not quite done: (29) allows us to figure out the spectrum of φ(t), but we ultimately want to find the spectrum of the output voltage of the oscillator, which is not quite the same thing. The two quantities are linked through the actual output waveform, however. To illustrate what we mean by this linkage, consider a specific case where the output may be approximated as a sinusoid, so that v_out( ) cos[t = ω₀t+φ( )]t . This equation may be considered a phase-to-voltage converter; it takes phase as an input, and produces from it the output voltage. This conversion is fundamentally nonlinear because it involves the phase

26 

modulation of a sinusoid.

Performing this phase-to-voltage conversion, and assuming “small” amplitude disturbances, we find that the single-tone injection leading to (29) results in two equal-power sidebands symmetrically disposed about the carrier

2 max ( ) 10 log 4 n n SBC I c P q ω ω ⎛ ⎞ Δ ≈ ⋅ _⎜ Δ ⎝ ⎟⎠ .

The foregoing result may be extended to the general case of a white noise source

(30) 2 i ∞ ⎛ ⎞ 2 0 2 2 max ( ) 10 log . 4 n n n SBC c f P q ω ω = ⎜ ⎟ Δ ⎜ ⎟ Δ ≈ ⋅ ⎜ ⎟ Δ ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎝ ⎠

∑

(31)

Equation (30) implies both upward and downward frequency translations of noise into the noise nea

, weighted by coefficient , so 1/f device noise ultimately becom

r the carrier, as illustrated in Fig. 2.23. This figure summarizes what the foregoing equations tell us: components of noise near integer multiples of the carrier frequency all fold into noise near the carrier itself.

Noise near dc gets upconverted

es 1/f3 noise near the carrier; noise near the carrier stays there, weighted by ; and white noise near higher integer multiples of the carrier undergoes downconversion, turning into noise in the 1/f2 region. Note that the 1/f2 shape results from the integration implied by the step change in phase caused by an impulsive noise input. Since an integration (even a time-varying one) gives a white voltage or current spectrum a 1/f character, the power spectral density will have a 1/f2 shape.

27 

Figure 2.23 Evolution of circuit noise into phase noise.

It is clear from Fig. 2.23 that minimizing the various coefficients cn (by minimizing the

ISF) will minimize the phase noise. To underscore this point quantitatively, we may use Parseval’s theorem to write

2 ₂ 2 0 0 1 ( ) 2 n n c π x dx π ∞ = 2 rms = Γ = Γ

∑

∫

(32)

so that the spectrum in the 1/f2 region may be expressed as 2 2 2 2 max ( ) 10 log 2 n rms i f L q ω ω ⎛ ⎞ ⎜ Γ ⎟ Δ ⎜ Δ = ⋅ _⎜ Δ ⎜ ⎟ ⎜ ⎟ ⎝ ⎠ ⎟ ⎟ (33)

where is the rms value of the ISF. All other factors held equal, reducing will reduce the phase noise at all frequencies. Equation (33) is the rigorous equation for the 1/f2 region and is one key result of the LTV model. Note that no empirical curve-fitting parameters are present in (33).

rms

28 

Calculation of the 1/f3 Noise Corner

Many active and passive devices exhibit low frequency noise with a power spectrum that is approximately inversely proportional to the frequency. It is for this reason that noise sources with this behavior are referred to as 1/f noise.

Noting that device noise in the 1/f region can be described by

1/ 2 2 ,1/ f n f n i i ω ω = ⋅ Δ (Δ <ω ω1/f) (34)

where ω1/f is the corner frequency of device 1/f noise, (30) and (34) result in the following

expression for phase noise in the 1/f 3 portion of the phase noise spectrum:

2 2 0 1/ 2 2 max ( ) 10 log 8 n f i c f L q ω ω ω ω ⎛ ⎞ ⎜ ⎟ Δ ⎜ Δ = ⋅ _⎜ ⋅ Δ Δ ⎜ ⎟ ⎜ ⎟ ⎝ ⎠ ⎟ ⎟ (35)

which describes the phase noise in the 1/f 3 region. The 1/f 3 corner frequency is then

3 2 2 0 1/ 1/ 1/ ₄ 2 dc f f f rms rms c ω ω ω ⎛ Γ ⎞ Δ = ⋅ = _⋅⎜ Γ Γ ⎝ ⎟⎠

from which we see that the 1/f 3 phase noise corner is not necessarily the same as the 1/f

(36)

device/circuit noise corner, but is smaller by a factor equal to 2 2 0 / rms

c Γ where c is the dc value of ISF, 0 2 0 0 1 ( ) 2 c π x π =

∫

Γ dx (37)

it will generally be lower. In fact, sinceΓdcis the dc value of the ISF, there is a possibility of

the control of the designer, usually through adjust

reducing by large factors the 1/f 3 phase-noise corner.

The ISF is a function of the waveform, and hence potentially under

ment of the rise- and fall-time symmetry. This result is not anticipated by LTI approaches, and is one of the most powerful insights conferred by this LTV model. This result has particular significance for technologies with notoriously poor 1/f noise performance, such as CMOS and GaAs MESFET’s.

29 

Figure 2.24 (a) Waveform and ISF for the symmetric waveform (b) the asymmetric waveform

To u in Fig

2.2

symmetric rising and falling edge is much larger than that in t

nderstand what affects c0, consider two ring oscillators, with waveforms shown

4. The first waveform has symmetric rising and falling edges, i.e., its rise time is the same as its fall-time. Assuming a time-invariant node capacitor1, the sensitivity of this oscillator to a perturbation during the rising edge is the same as its sensitivity during the falling edge, except for a sign. Therefore, the ISF has a small dc value. The second case corresponds to an asymmetric waveform with slow rising edge and a fast falling edge. In this case, the phase is more sensitive during the rising edge, and is also is sensitive for a longer time; therefore, the positive lobe of the ISF will be taller and wider as opposed to its negative lobe which is short and thinner, as shown in Fig. 2.24.

The dc value of the ISF for the a

he symmetric case, and hence a low frequency noise source injecting into it shows a stronger upconversion of low frequency noise. A limited case of the effect of odd-symmetric waveforms on phase noise. However minimizing (37) is more a general criterion because although odd-symmetric waveforms may have small c0 coefficients, the class of waveforms

30 

Chapter 3

Review of Low Power and Low Phase Noise

Designs

3.1 Low Power VCO Design in CMOS

A. Forward Body Bias (FBB) [6]

For deep-submicrometer MOSFETs, the threshold voltage Vt is no longer constant, but

influenced by circuit parameters such as gate length, channel width, and drain-to-source voltage due to the short-channel and narrow-channel effects. Typically, transistors with a large channel width and a minimum gate length exhibit a reduced Vt, which is preferable for

low-voltage operations. In this VCO topology, the fundamental limitation on the supply voltage is imposed by the threshold voltage of the cross-coupled transistors. To further reduce the supply voltage, the FBB technique is adopted as shown in Fig. 3.1. For a MOSFET device, the threshold voltage is governed by the body effect as

0 ( 2 / ) ( 2 2 )

t t A s F SB F

V =V + qN ε Cox ⋅ φ +V − φ (1)

where Vt0 is the threshold voltage for VSB = 0 V, φF is a physical parameter with a typical

value of 0.4 V, NA is the substrate doping, and εs is the permittivity of silicon. By applying a

31 

voltage is thus reduced while maintaining a minimum forward junction current between the body and the source terminals. The simulated effective threshold voltage and the drain current of a MOSFET with W = 64 μm and L = 0.18 μm are demonstrated in Fig. 3.2, indicating a threshold voltage reduction more than 100 mV due to the FBB technique.

B

B

Figure 3.1 Schematic of the FBB

32 

B. Dynamic Threshold Voltage MOSFET (DTMOS) [7]

For low power operation at very low voltages, a MOSFET should ideally have a high Vt

at VGS = 0 to achieve low leakage and low Vt at VGS = Vdd to achieve high speed. By tying

body and gate of an SO1 MOSFET together, a dynamic threshold voltage MOSFET (DTMOS) is obtained. This device has ideal 60 mV/dec subthreshold swing. DTMOS threshold voltage drops as gate voltage is raised, resulting in much higher current drive than regular MOSFET. DTMOS is ideal for very low voltage (< 0.6 V) operation, as demonstrated by ring oscillator data. DTMOS also solves the floating body problems of SO1 MOSFET such as kinks and Vt

stability. Furthermore, carrier mobility is enhanced.

Figure 3.3 Schematic of the DTMOS

33 

C. Current-Reuse CMOS Differential LC-VCO [8]

Figure 3.5 shows schematics the current-reuse differential LC-VCO. The series stacking of N- and P-MOSFETs allows the supply current to be reduced by half compared to that of the conventional LC VCO while providing the same negative conductance.

34 

3.2 Low Phase Noise VCO Design in CMOS

A. A Low Phase-Noise CMOS VCO With Harmonic Tuned LC Tank [4]

The filtering, by parallel resonation at 2f0 frequency using an inductor with the parasitic

capacitor at the common source, stops the differential-pair FETs in the triode region from loading the resonator, preventing the degradation of the resonator Q. As shown in Fig. 3.6, an Ls is used to make a parallel resonation with the parasitic capacitance Cp at 2f0 frequency.

This technique has an independent phase-noise reduction effect and the combination of the harmonic tuning and filtering techniques can reduce the phase noise significantly for 1/f3 and 1/f2 regions. Using these techniques, a complementary VCO is designed to achieve the minimum phase noise. The phase-noise simulation results in Fig. 3.7 show the phase-noise reduction effect of each technique independently and also that of the combined case.

35 

Figure 3.7 Simulated phase-noise results for each technique.

B. Effects of Forward Body Bias on High-Frequency Noise in 0.18-μm CMOS Transistors

[3]

The effects of FBB on the high-frequency noise in 0.18-μm, MOS transistors have been investigated. Although MOSFET dc performance could be improved when the substrate is forward biased, significant degradation of RF noise was observed in both N and PMOS devices. The increase in high-frequency noise with was qualitatively explained by considering the contributions from nonequilibrium channel noise and substrate resistance noise. The increase in RF noise in PMOS noise was found to be strongly correlated to the substrate resistance noise, while the increase in RF noise in NMOS was attributed to a combinational effect of substrate resistance noise and channel noise. Our experimental results in this study suggest that, for RF circuit applications, a forward body biasing scheme is not favorable if high-frequency noise is an important concern.

36 

37 

Chapter 4 Proposed Low Power, Low Voltage and Low

Phase Noise VCO

4.1 INTRODUCTION

Among the building blocks of a radio frequency (RF) transceiver, the voltage-controlled oscillator (VCO) is an important block since it affects the system performance of the transceiver to a large extent. In designing a VCO, low power consumption and low phase noise are two important parameters. The low power consumption may be achieved by reducing the supply voltage and/or the current in the VCO core circuit. Forward body bias (FBB) has been proposed as an effective method for improving the device performance in MOSFETs. Forward bias the body to source voltage VBS and source to body voltage VSB of

NMOS and PMOS reduce the threshold voltage (Vt). The increase in high frequency noise

with ∣VBS∣ was qualitatively explained by considering the contributions from

nonequilibrium channel noise and substrate resistance noise in 0.18 µm CMOS transistors. Therefore, in RF circuit applications, an FBB scheme is not favorable if high frequency noise is an important concern [3].

However, the low voltage limits the signal amplitude, which in turn limits the signal-to-noise ratio (SNR) and leads to an increase of the phase noise of the VCO. There is a tradeoff between the VCO phase noise and power consumption due to the degradation of the phase noise with the increased VCO gain needed for a larger power consumption. Therefore,

38 

how to control a low phase noise effectively at the low power level becomes an important and challenging issue. [4] suggests adding an external circuit called a harmonic tuned (HD) LC tank to suppress the harmonic frequency of the circuit. This method can reduce the phase noise effectively, but it also increases both the die area and power consumption.

In this chapter, a low power, low voltage and low phase noise LC-VCO circuit is proposed. An external negative-resistance cell is also added between the different outputs, which can effectively reduce both the power consumption, supply voltage and the phase noise. The proposed LC-VCO is validated by an implementation using the TSMC 0.18 µm 1P6M process.

4.2.1 Current-reused VCO with Low Power and Low voltage

Vdd

Vdd

Vct

Negative resistance cell

Resonator Mp1 Mn2 Mp5 L Vg Vg Vd Vd Vo+ V o-Mn7 Mn8 Rg Rg Rd Rd C1 C2 Mp3 Mp4 Buffer Amplifier Core circuit

39 

Y

in

L

C

var

R

p

R

c

C

eq

Negative -resistance cell

LC - Tank

R

eq

Figure 4.2 Parallel LC oscillator model of the proposed VCO1.

Figure 4.3 (a) Negative-resistance cell circuit; (b) Series circuit model of the negative-resistance cell.

Our design, as shown in Fig. 4.1, adds a negative-resistance cell (Mp5 and Cgs5-Cds5)

shunt to the L-C tank to a current-reuse topology (Mp1-Mn2) [8], which effectively enlarges

the negative resistance and leads to the reduction of both the core power consumption, supply voltage and phase noise of the VCO. Fig. 4.2 shows a simplified equivalent circuit of the proposed VCO shown in Fig.1 in the steady state, where the resistance Rp represents the tank

40 

approximately equal to -(1/gmN1 + 1/gmP2). Req and Ceq, which represent the equivalent

resistance and capacitance of the negative-resistance cell, are given by

2 2 5 5 e 2 5 5 ( ) R gs ds m5 q gs ds C C g C C ω ω + + = − (1) 5 5 5 2 5 5 5 2 5 5 ( ) gs ds eq gd m gs ds gs ds C C C C g C C C C ω = + + + + (2)

where gm5 is the transconductance of Mp5, the symbols (Cgs5 , Cds5) represent the (gate-source

drain-source) capacitor of pMOS Mp5 and ω is the operating frequency. They are derived by

using a small-signal model as shown in Fig. 4.3(a). The series circuit mode of the cell circuit is given in Fig. 4.3(b) and then the input im

,

pedance of the differential negative-resistance cell, Zin = vin/iin, is given by 5 2 5 5 5 5 1 1 1 1 ( ) m in s gs ds gs ds s g Z R C C j C C j C ω ω ω = − + + = + (3) Therefore, 5 2 5 5 m s gs ds g R C C ω = − , 5 5 5 5 gs ds s gs ds C C C C C = +

In order to sim in, and Yin is defined as

1/Req + jωCeq. With Eq. (3), Req and Ceq are given by

plify the analysis, conductance Yin is given as 1/Z

e 2 2 1 R _{q s} s s R C ω R = + , ₂ e R 1 s s q R C ω s eq C C = + (4)

Thus, equations (1) and (2) are derived. By tuning W/L for MOSFET (Mp5) in the typical

design, we can easily achieve 2 _ds5 2and

5 ( 5 ) m gs g ω C +C 2 5 5 5 2 5 5 ( ) ( ) m gs ds gs ds g C C C C ω + +  .

Then, (1) is simplified and given by

5 e 2 5 5 R m q gs ds g C C ω ≈ − (5)

41  5 5 5 5 5 gs ds eq gd gs ds C C C +C

In (5), the magnitude of the negative resistance Req is inversely proportional to the square

of ω and is linearly proportional to the transconductance of Mp5 which is proportional to the

transistor current. This means that the larger the frequency or the smaller current is, the larger the negative resistance is, which shows that our proposed circuit can achieve a much larger negative resistance than conventional designs in RF circuit applications. The small current flow has the advantage of a low power consumption. To analyze the effect of the negative resistance

C ≈C + (6)

on the phase noise level, the pioneering work by Hajimiri and Lee is applied to evaluate the phase noise L of the circuit at an offset frequency Δω from the carrier [5]. L is given by 2 2 2 2 2 tan 2 n rms eq k i C A ω Γ Δ

with Atank being the oscillation amplitude across the resonator. Ceq is the tank capacitance, and

Γrms is the root mean square value of the impulse sensitivity function (ISF). Equation (7)

demons

( ) 10log( )

L Δω = (7)

trates that a larger Ceq of the resonant tank results in a lower phase noise. In (6), Cgs5

nd Cds5 are equivalent to Ceq by using a negative-resistance cell. Thus can lower the phase

a noise.

4.3 EXPERIMENTAL RESULTS

The die microphotograph of the proposed VCO is shown in Fig. 4.4, where the proposed VCO is fabricated by using the TSMC 0.18 μm CMOS process. Its die area is 0.67× 0.81 mm2 including the pads. An on-wafer measurement is carried out for RF characterization. The measured oscillation frequencies cover 3.6 GHz to 3.4 GHz while the control voltage Vct is changed from 0 V to 1.3 V, as shown in Fig. 4.5. Fig. 4.6 shows the VCO output spectrum

42 

with values of -5 dBm. As shown in Fig. 7, the measured phase noise of the proposed VCO is about -116.89 dBc/Hz at 1MHz offset frequency. The power consumption of the proposed

CO core is 0.54 mW at the supply voltage of 0.93 V. The figure

V of merit (FOM) of the

proposed VCO is -190.4 dBc/Hz with the FOM defined by { } _{10 log 20 log} 0 1 DC P f FOM L f mW f ⎛ ⎞ = Δ + × _{⎜ ⎟}− × _{⎜ ⎟} Δ ⎝ ⎠ ⎝ ⎠ (8)

where f0 is the oscillating frequency, Δf is the offset frequency, L{Δf} is the measured phase

noise at Δf, and PDC is the DC power consumption of VCOs in mW. Table I summarizes the

measured phase noise (PN), f0, power consumption a

⎛ ⎞

nd FOM of the proposed VCO and other ublished results. The comparison shows that our proposed work yields very low power consumption and achieve a high FOM performance.

Figure 4.4 Microphotograph of the VCO1.

43 

Figure 4.5 Measure tuning range of the VCO1.

44 

Figure 4.7 Measured phase noise versus offset frequency of the VCO1 at 3.5 GHz. TABLE I

Current-reused VCO with Low Power and Low voltage MEASURED PERFORMANCE SUMMARY AND COMPARISON Ref. CMOS Technology (μm) Freq. (GHz) Phase Noise @ 1-MHz offset (dBc/Hz) PDC (mW) FOM (dBc/Hz) [9] MWCL 2005 0.18 4.96-5.32 4.98-5.45 -116.71 -110.02 3.9 2.59 -185 -180 [6] MTT2007 0.18 5.6 -118 3 -189 [10] MWCL 2007 0.18 2.01 -124 2.2 -186.7 [11] CASII 2008 0.18 2.17-2.73 -122.3 2.7 -186.3 [12] MWCL 2009 0.18 5.6 -119.13 2.4 -190 [13]MWCL 2009 0.18 5.46 -120.2 6.4 -187 [14]MWCL 2009 0.18 2.93-3.62 -122 1.7 -190 VCO1 0.18 3.5 -116.89 0.54 -190.4

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4.4 Current reused VCO with Low Power and Low Phase Noise

Figure 4.8 Proposed VCO2 circuit.

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Figure 4.10 (a) Negative-resistance cell circuit; (b) Series circuit model of the negative-resistance cell. 5 e ₂ 1 2 R m q g C C ω ≈ − (8) 2 1 2 5 1 2 eq m C C C g C C ω ≈ + (9)

Form (9), C1−C2 can be enlarged to Ceq by using a negative-resistance cell, and Ceq is

positively correlated with (ω/gm5)2 without any additional capacitance and thus can lower the

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4.5 EXPERIMENTAL RESULTS

The die microphotograph of the proposed VCO is shown in Fig. 4.11, where the proposed VCO is fabricated by using the TSMC 0.18 μm CMOS process. Its die area is 0.56× 0.71 mm2 including the pads. An on-wafer measurement is carried out for RF characterization. The measured oscillation frequencies cover 2.52 GHz to 2.41 GHz while the control voltage Vct is changed from 0 V to 1.3 V, as shown in Fig. 4.12. Fig. 4.13 shows the VCO output spectrum with values of -3.5 dBm. As shown in Fig. 4.14, the measured phase noise of the proposed VCO is about -125 dBc/Hz at 1MHz offset frequency. The power consumption of the proposed VCO core is 1.9 mW at the supply voltage of 1 V.

The figure of merit (FOM) of the proposed VCO is -190 dBc/Hz with the FOM defined by { } _{10 log 20 log} 0 1 DC P f FOM L f mW f ⎛ ⎞ ⎛ ⎞ = Δ + × _{⎜ ⎟}− × _{⎜ ⎟} Δ ⎝ ⎠ ⎝ ⎠ (10)

where f0 is the oscillating frequency, Δf is the offset frequency, L{Δf} is the measured phase

noise at Δf, and PDC is the DC power consumption of VCOs in mW. Table II summarizes the

measured phase noise (PN), f0, power consumption and FOM of the proposed VCO and other

published results. The comparison result shows that our proposed work yields very low phase noise even with a relatively low power consumption, and shows the best FOM performance.

48 

Figure 4.11 Microphotograph of the VCO2.

49 

Figure 4.13 Measured the VCO2 output spectrum at 2.4 GHz.

50  TABLE II

Current reused VCO with Low Power and Low Phase Noise MEASURED PERFORMANCE SUMMARY AND COMPARISON Ref. CMOS Technology (μm) Freq. (GHz) Phase Noise @ 1-MHz offset (dBc/Hz) PDC (mW) FOM (dBc/Hz) [9] MWCL 2005 0.18 4.96-5.32 4.98-5.45 -116.71 -110.02 3.9 2.59 -185 -180 [6] MTT2007 0.18 5.6 -118 3 -189 [10] MWCL 2007 0.18 2.01 -124 2.2 -186.7 [11] CASII 2008 0.18 2.17-2.73 -122.3 2.7 -186.3 [12] MWCL 2009 0.18 5.6 -119.13 2.4 -190 [13]MWCL 2009 0.18 5.46 -120.2 6.4 -187 [14]MWCL 2009 0.18 2.93-3.62 -122 1.7 -190 VCO2 0.18 2.4 -125 1.9 -190