Joule heating effect

Joule heating effect is that the electrons moving through a metal, the electrical energy converted into thermal energy. The heating power can be expressed as

P = I²R = j²ρV (2.1)

where P is Joule heating power, I is the current, R is the resistance, j is the local current density, V is the volume of the material, and ρ is the resistivity. The product of I²R is the total heating power, whereas j²ρis the heating power per unit volume.

During the electromigration test, the applied current may be as high as 2.0 A, and thus Joule heating effect in the solder bumps becomes significant.[9] Furthermore, the total length of the Al trace is typically few hundreds to few thousands microns, which corresponds to a resistance of approximately few hundreds milli-ohms or few ohms. On the other hand, the resistances of the solder bumps and the Cu trace in the substrate are relatively low, typically in

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the order of few or tens of milli-ohms. The major heat source for the solder joints is the Al trace.[10] Hence, the temperature in the bumps during testing may be much higher than that of the ambient due to Joule heating, and may affect the mean-time-to-failure (MTTF) analysis, as delineated by Black’s equation: [11]

)k T

where A is constant, j is the current density, n is a model parameter for current density, Q is the activation energy, k is the Boltzmann’s constant, and T is the average bump temperature.

It is noteworthy that the MTTF decreases exponentially with the stressing temperature. Wu et al. [12] conducted electromigration test for SnPb solder bumps, and found that the MTTF decreased from 711 hours to 84 hours when the testing temperature increased from 125 °C to 150 °C at 5.0 × 10³ A/cm², whereas the MTTF decreased from 277 hours to 84 hours as the current density increased from 2.5 × 10³ A/cm² to 5.0 × 10³ A/cm² at 150 °C. Therefore, the

influence of the stressing temperature on MTTF is more profound than the current density.

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1.3.2 Current crowding effect

In previous work published by Liang et al.[13], current density distribution in a solder joint was thoroughly studied by a three-dimensional finite element simulation. It was found that the maximum current density in a solder bump can be much higher than the average one that was previously projected. It locates itself near the solder/underbump metallization (UBM)

interface, which serves as a vacancy flux divergence plane and favors electromigration occurring at that location. Consequently, the solder joint is more prone to electromigration.

The cause of such locally high current density is a result of the current crowding effect.

Current crowding occurring in the solder joints is due to the current flow experiencing a dramatic geometrical and resistance transition from the thin on-chip metal line to the solder bump. Because the cross-section of the Al trace on the chip side is about two orders smaller than that of the solder joints, the majority of the current will tend to gather near the Al/UBM entrance point to enter the solder bump instead of spreading uniformly across the opening before entering the bump. The materials near the entrance point experience a current density of about one order of magnitude higher than the average value. Current crowding plays a critical role in the electromigration failure of the solder joints.[13]

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1.3.3 Thermomigration

Thermomigration is the atom movement due to temperature gradient.[14,15] As the required performance in microelectronic density increases, the design rule of packaging requires that some of the power bumps may need to carry 0.2 to 0.4 A. Therefore, Joule heating effect in the solder bumps become an important issue. Furthermore, to meet the need for increased miniaturization of portable devices, the dimension and the pitch of the solder bumps continues to shrink, causing the Joule heating effect to be even more serious. Roush found that the thermal gradient is as higher as 1200°C/cm in Pb-In bump, and Pb atoms moved from hot end to cold end in 1982.[16]。Ye at al. stressed the SnPb solder under 1.3 ×

105 A/cm2 (1A) for 16 h. The found voids occurred at both anode and cathode side as shown in Figure 5 and Figure 6. They performed a simulation for the temperature distribution, and found the thermal gradient was as high as 1500 °C/cm in a SnPb solder bump when it was stressed by 1.0 A as shown in Figure 7. However, there is still no experimental data to verify the temperature in the bump because the solder joints are completely surrounded by a chip, a substrate and underfill, so no direct temperature measurement can be made to investigate the Joule heating effect inside the solder joints. [17]

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Figure 5. Voids occurred at anode side.

Figure 6. Voids occurred at cathode side.

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Figure 7. Smulation of temperature distribution under 1.0A (a) the solder joint (b) temperature as a function of distance from Al trace to Cu plate

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1.3.4 Void formation in flip chip solder joint during electromigration

The pitch of solder bumps has decreased rapidly, in turn the contact area of the solder bumps and the diameter of under bump metallization (UBM) decrease rapidly too.

On the other hand, the operation current for the bumps keeps increasing, resulting in a dramatic rise of the current density in the solder bump. [16-18] Tu et al. stressed the SnPb solder with Al/Ni(V)/Cu UBM under 1.90、2.25、2.75 × 10⁴A/cm² . The voltage was recorded in the same time. They found that once the void was formed and propagated toward the rest of UBM at the interface of Si chip and SnPb solder, dramatic rise of electrical resistance occurred.[16] Brandenburg and Yeh reported the observation of electromigration failure in flip chip eutectic SnPb solder joints stressed under 8x10³ A/cm² at 150 for a few hundred ℃ hours. [8] The important findings are void formation at the cathode and Pb accumulation at the anode of the solder joint.

Redistribution of current density and temperature due to void formation in flip-chip solder joints during electromigration was investigated using three-dimensional thermo-electrical coupled modeling, in which the current density and temperature redistribution were simulated at different stages of void growth for solder joints with thin-film UBM. Liang et al. found that after the void formation near the entrance point of Al trace, the current may propagate through the UBM layer to the periphery of the solder joint, leading to the void formation in the

periphery of the solder joint, which was low current density region before the void formation

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as shown in Figure 8.[25] In addition, the temperature of the solder did not rise significantly until 95% of the contact opening was eclipsed by the propagating void. It is proposed that current redistribution is the main reason accounting for void formation and propagation, especially the propagation into the low current density region below the contact passivation. It is found that UBM provided a conducting path for current to go below the passivation, and it directed the current to the periphery of the solder joint, which is in agreement with the experimental observation of void formation in those regions. Increase in temperature due to void formation was not significant since the major heat source was the Al trace and the applied current was as low as 0.28 A. However, there is also no experimental data to verify temperature redistribution due to void formation in real flip-chip solder bumps. We will discuss that in later chapters.

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Figure 8 (a) Cross-sectional view of current density distribution in solder joint (b) Corresponding cross-sectional view for temperature

distribution.

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1.4 Motivation

Since electromigration is the result of a combination of thermal and electrical effects on mass motion, the Joule heating effect must be addressed to provide better understanding of the electromigration behavior. The current used for typical accelerated electromigration tests ranges from 0.5 A to 2.2 A. Although whether a hot spot exists at the current crowding region is of interest, only a few studies have addressed the Joule heating effect in solder joints.[9, 10, 19] Furthermore, the total length of the Al trace is typically few hundreds to few thousands microns, which corresponds to a resistance of approximately few hundreds milli-ohms or few ohms. On the other hand, the resistances of the solder bumps and the Cu trace in the substrate are relatively low, typically in the order of few or tens of milli-ohms. The major heat source for the solder joints is the Al trace.[10] Hence, the temperature in the bumps during testing may be much higher than that of the ambient due to Joule heating, and may affect the mean-time-to-failure (MTTF) analysis, as delineated by Black’s equation (2.2):[11]

It is noteworthy that the MTTF decreases exponentially with the stressing temperature. Wu et

al.⁸ conducted electromigration test for SnPb solder bumps, and found that the MTTF decreased from 711 hours to 84 hours when the testing temperature increased from 125 °C to 150 °C at 5.0 × 10³ A/cm², whereas the MTTF decreased from 277 hours to 84 hours as the current density increased from 2.5 × 10³ A/cm² to 5.0 × 10³ A/cm² at 150 °C. Therefore, the

influence of the stressing temperature on MTTF is more profound than the current density.

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Ye at al. performed a simulation for the temperature distribution, and found the thermal gradient was as high as 1500 °C/cm in a SnPb solder bump when it was stressed by 1.0 A.

However, there is still no experimental data to verify the temperature in the bump because the solder joints are completely surrounded by a chip, a substrate and underfill, so no direct temperature measurement can be made to investigate the Joule heating effect inside the solder joints. For this study, we used thermal infrared (IR) microscopy to measure the temperature distribution in the Al trace at various stressing conditions. Based on the experimental data, we constructed a finite element model to simulate the temperature distribution inside the solder bump during current stressing. Therefore, this study provides deeper understanding of the Joule heating effect inside the flip-chip solder joints during current stressing.

During electromigration, voids nucleate in the solder bump near the point of entry of the electron flow, where serious current crowding and flux divergence occur.[20,21] In previous studies, void formation and propagation were observed by cross-sectional scanning electron microscope (SEM). Therefore, only the length and the depth of the void at those specific cross-sections can be observed. However, the location where voids nucleate, the shape of voids, as well as how voids propagate in the UBM opening remains unclear. In addition, the propagation velocities of voids at different stages have not been measured. X-ray microscopy has been used to study formation of voids in Cu interconnects during electromigration.[22]

Since the size of voids formed in Cu interconnects is in submicron range, synchrotron

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radiation x-ray is needed. For flip-chip solder joints, the voids are of a much larger dimension, typically ranging from few microns to tens of microns. Thus, a laboratory-based x-ray

microscope appears to be sufficient for the investigation of void nucleation and propagation in solder joints during electromigration. Nevertheless, it has not been applied to solder joints.

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Chapter II Experimental

2.1 Fabrication of clip chip packages (I)

The fabrication procedure for the SnAg bumps were prepared as follows: A SnAg3.5 solder paste was printed and deposited on the UBM pad of the chip. The chip was reflowed in a nitrogen atmosphere oven at the 250°C peak temperature and remained above the liquid temperature for approximately 60 s. Then, the bumped die sample was prepared after sawing.

Afterward, the bumped die was mounted on a BT substrate, on which the SnAg3.5 solder paste was printed through a metal stencil printing on the metallization pads of the substrate.

Then, the flip-chip sample was reflowed for the second time in a nitrogen atmosphere oven at the 250°C peak temperature for approximately 60 s. The flip-chip joints were formed after the second reflow. Afterward, the flip-chip package was under filled as shown in Figure 9.

Figure 10 shows the schematic for the solder bump. The thickness of the Si chip was 300 μm. The under-bump-metallization (UBM) consisted of 0.7 μm Cu, 0.3 μm Cr-Cu, and 0.1 μm Ti. It is assumed that a layer-type Cu6Sn5 intermetallic compound (IMC) of 1.4 μm thick grew in the interface of the UBM and the solder, whereas a layer-typeNi3Sn4 IMC of 1.0 μm thick formed in the interface of the pad metallization and the solder in the substrate side. The UBM and passivation openings were 120 μm and 85 μm in diameter, respectively. The Al trace on the chip side was 34 μm wide and 1.5 μm thick. BT substrate was employed for the flip chip package.

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Figure 9. Flip chip Package (I)

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Figure 10. Schematic for the solder bump

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2.2 Fabrication of flip chip packages (II)

To analyze the effect of Al-trace dimension on electromigration of flip-chip solder joints, another flip chip package was prepared. The dimension of the flip-chip joint used in this study is shown in Figure 11(a) schematically. The under bump metallization (UBM) was Ti/Cu/Cu/Ni. A titanium layer of 0.1 μm was sputtered on the oxidized Si wafer and acted as an adhesion layer. Copper (0.5 μm) was then sputtered on the Ti layer and served as a seed layer for the subsequent electroplating process. Then a 5-μm Cu and a 3-μm Ni layers were electroplated on the Ti/Cu layers. Photolithography was applied to define the UBM opening.

Afterwards, the UBM opening was formed by wet etching process. Due to the fast etching of Cu, the diameter of Cu UBM was smaller than that of the Ni UBM, as shown in Figure 11(a).

The passivation and UBM openings are 110 µm and 120 µm in diameter, respectively.

Eutectic SnPb solder was electroplated onto the UBM, followed by reflowing in an infrared oven at 220 for about 1 minute. The solder bumps were jointed to FR4 substrates. The pad ℃ metallization consisted of 1-μm Au and 5-μm electroless Ni layers. The dimension of the pad opening was 300 μm in diameter. The dimension of the Si chip was 5.35 mm long, 4.35 mm wide, and 250 μm thick, whereas the dimension of the FR4 substrate was 5.35 mm long, 4.35 mm wide, and 250 μm thick. Two different layouts of Al traces were fabricated: one was 40 μm wide and 1.5 μm thick as shown in Fig. 11(b); the other was 100 μm wide and 1.5 μm thick, as shown in Fig. 11(c). The four bumps in Fig. 11(d) were labeled as B1 through B4, and the three Al traces were labeled as T1 through T3. The pitch for both test samples was 850 μm. The non-solder mask process was adopted.

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Figure 11(a) Cross-sectional view showing the materials and the dimension of a SnPb bump.

Figure 11(b) Plan-view schematic showing the solder joints with 40-μm-wide Al traces.

Figure 11(c) Plan-view schematic showing the solder joints with 100-μm-wide Al traces.

Figure 11(d) Plan-view schematic showing the solder joints with 100-μm-wide Al traces for the investigation of length effect on electromigration.

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2.3 Temperature measurement by infrared microscopy

An Infrared microscope(Quantum Focus Instrument) as shown in Figure 12(a) was

employed to measure the temperature in the Al trace during current stressing. The temperature distribution inside the bumps when powered by electric current was detected by a thermal infrared microscope, which has the resolution of 0.1 °C in temperature sensitivity and 2.8 μm in spatial resolution. The current stressing of the specimen was performed on a hot plate in ambient air, which has heating capacity up to 120℃. Prior to the current stressing, the emissivity of the specimen was calibrated at 100 °C. After the calibration, the bumps were

powered by a desired current stressing condition. Then, temperature measurement was performed to record the temperature distribution after the temperature reached a steady state.

Figure 12(b) shows the schematic diagram for experimental setup, in which the Si side faced the infrared microscope.Since the 250 μm Si is transparent to infrared,the corresponding penetration depth is larger than 2m and much larger than the thickness of the silicon wafer.

Therefore, the absorption can be ignored.[28] The temperature distribution in the Al traces and in the Al pad directly above the solder bumps during current stressing can be measured.

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1. Cooling chamber 2. CCD Sensor 3. Cantilever -X 4. Cantilever -Y 5. Cantilever -Z 6. Camera 7. IR detector

8. Heating apparatus 9. Heater

10. Heater stage 11. Stage Figure 12(a) Infrared microscope

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Figure 12(b) Infrared microscope schematic diagram for experimental setup, in which the Si side faced the infrared microscope.

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2.4 Microstructure examination

A JEOL 6500 scanning electron microscope (SEM) and energy dispersive spectroscopy (EDS) were used to observe the microstructure and composition of the solder joints in the flip chip package. The cross-sectional samples were prepared by polishing laterally until the contact opening was visible. Figure 13 shows the cross-sectional SEM image for the fabricated samples. Due to the large opening in the substrate side, the bump height was as small as 25 μm. Both the electroplated and elctroless Ni layers reacted with the solder to form Ni3Sn4 intermetallic compounds (IMCs), and the average thickness of the IMCs was 1 μm.

SEM was also employed to examine the voids in the cross-section of the solder bumps. Then, an etching solution consisting of glycerin, nitric acid and acetic acid at ratio of 1 : 1 : 1, was used to selectively etch the tin. Thus, the morphology of intermetallic compound (IMC) and the whole contact opening could be observed clearly after the selective etching.

Figure 13. The cross-sectional SEM image for the fabricated samples.

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2.5 X-ray microscope

In this study, void formation during electromigration was monitored by an x-ray

microscope. A DAGE XL-6500 x-ray microscope with the Si side facing the x-ray detector, which has 2 μm in spatial resolution. The corresponding current density was 6.5×10³ A/cm². The operation voltage was set at 95 kV in this study. Since voids form in the bump with electron flow from the chip side to the substrate side, only the bumps with this stressing direction were examined. The solder joints were stressed by 0.8 A at 150°C for a desired time.

Figure 14 shows the cross-sectional schematic for the solder joint used in this study. The dimension of the Al trace was 1.5 μm thick and 100 μm wide, while the dimension of the Cu lines on the substrate was 25 μm thick and 100 μm wide. The UBM consists of 0.1-μm Ti, 5-μm Cu, and 3-μm Ni layers. The diameter of the UBM and the passivation openings was 120 μm and 85 μm, respectively. Electroplated SnPb solder bumps were mounted on a FR4 substrate to form flip-chip joints. Non-solder-mask-defined process was used in this structure.

The dimension of the Cu pad opening was 300 μm in diameter. Owing to the large opening in the substrate side, the bump height was as small as 25 μm. With the low bump height, the voids in the solder bump would be much clearly seen in an x-ray microscope.

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Figure 14. Cross-sectional schematic diagram of the samples used in this study.

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2.6 3-D thermo-electrical simulation by finite element analysis

On the basis of the experimental results, a three-dimensional (3-D) simulation was carried out by finite element analysis. The schematic diagram for the package is shown in Figure 12(b). Two solder bumps had electrical current applied through the circuit shown in the Figure.

The electrical and thermal resistivities for the materials used in this modeling are listed in Table I. The effect of temperature coefficient of resistiviy (TCR) was considered, and the TCR values for the metals are also listed in Table I. In addition, 3-D coupled thermal-electric simulation was conducted to predict the steady state temperature distribution using the ANSYS software package developed by ANSYS, Inc. The model used in this study was a SOLID69 8-node hexahedral coupled field element. All the boundary conditions followed the experiment setup, shown in Figure 12(b). The whole flip chip package with meshization is

The electrical and thermal resistivities for the materials used in this modeling are listed in Table I. The effect of temperature coefficient of resistiviy (TCR) was considered, and the TCR values for the metals are also listed in Table I. In addition, 3-D coupled thermal-electric simulation was conducted to predict the steady state temperature distribution using the ANSYS software package developed by ANSYS, Inc. The model used in this study was a SOLID69 8-node hexahedral coupled field element. All the boundary conditions followed the experiment setup, shown in Figure 12(b). The whole flip chip package with meshization is