Chapter 3 Proposed Low-Power Injection-Locked D-BPSK Receiver
3.3 Circuit Implementation
3.3.1 Low Noise Amplifier and Multi-Stage Amplifier
LNA adopts the cascode common-source topology with Q-enhancement technique for increasing gain in ultra-low voltage design without consuming excess power as shown in Fig. 3-6. The CS and LG are off-chip element for an input matching network.
Moreover, the input terminal of LNA is connected with ESD protection, which consists of 2 reverse-biased diodes. The source degeneration inductor is implemented by the
Fig. 3-6 Schematic of the Low-Noise Amplifier
The input impedance with matching network can be expressed as equation (3-16), where CGS is the parasitic capacitance between gate terminal and source terminal.
1
Chapter 3 Proposed Low-Power Injection-Locked D-BPSK Receiver
28
resonant frequency = 435 MHz, the values of LG is 100 nH and CS is about 20 pF by the simulation of smith chart.
Q-enhancement technique is adopted by using colpitts structure which forms positive feedback path for canceling the parasitic loss Rs of inductor LD. The related
The multi-stage amplifier follows the LNA to provide additional gain for meeting the requirement analyzed in Chapter 3.2.2. The architecture composes of 3 cascade common-source amplifier. Each stage provides 15-dB voltage gain.
Vbias
Fig. 3-7 Schematic of the Multi-Stage Amplifier
3.3 Circuit Implementation
The simulated S11 of LNA is shown in Fig. 3-8, which is around -14 ~ -33 dB under different corners. The central-frequency drift is solved by adjusting digital code of ILO. Fig. 3-9 shows overall voltage gain of front-end amplifier. The results under TT 27°, FF 0°, SS 80° are 58 dB, 64 dB, 43 dB, respectively.
TT27 FF0
SS80
Fig. 3-8 Simulated S11 of LNA
TT27 FF0
SS80
Fig. 3-9 Simulated overall voltage gain
The simulated noise figure of total amplifier which consists of LNA and AMP is shown in Fig. 3-10. The value is around 7 ~ 25 dB under different corners from 414 MHz to 457 MHz.
Chapter 3 Proposed Low-Power Injection-Locked D-BPSK Receiver
30
SS80
FF0 TT27
Fig. 3-10 Simulated overall noise figure
Table 3-2 Simulated characteristics of LNA and AMP @ TT27 o
Item Value
Supply Voltage 0.5 V
Total Current 450 A
Input Return Loss -10 dB
Voltage Gain 46 dB
Noise figure 10 dB
3.3.2 Injection-Locked Dual-Conduction Oscillator
The schematic of injection-locked oscillator, composed of a digitally-controlled oscillator (DCO) and a Gm stage, is shown in Fig. 3-11. ILO adopts dual-conduction PN-complimentary LC-tank topology [27]. One main pair is used for sustaining class-C operation, while the other is an auxiliary pair with an added resistor RS for minimizing total current consumption after overcoming start-up condition. A 4-bit programmable capacitor array with varactor is incorporated to compensate for the center frequency deviation due to PVT variations. The Gm stage (M7, M8) is designed to convert the input voltage signal to current format for injecting the oscillator. Due to the
3.3 Circuit Implementation
low-voltage operation (0.5 V), the replica-biasing circuit is used to provide a stable bias point. The transistor size and biasing condition is listed in Table 3-3.
Table 3-3 Transistor size and operating point of the Gm stage under corner TT27o Device W/L (m/m) Current (A) gm (S) go (S)
Fig. 3-11 Schematic of Dual-Conduction Digitally-Controlled Oscillator
Fig. 3-12 shows the simulated frequency tuning range of DCO by varying the varator tuning voltage at different digital code. The range covers from 430 to 460 MHz over different corners. With 4-bit capacitor array, DCO support the entire Med-radio band and ensure the flexibility of channel selection. The simulated phase noise at 100-kHz and 1-MHz offset from the carrier frequency is lower than -75 dBc/Hz and -110 dBc/Hz, respectively, as shown in Fig. 3-13. Table 3-4 summaries the simulated characteristic of the DCO.
Chapter 3 Proposed Low-Power Injection-Locked D-BPSK Receiver
32 SS80
FF0 TT27
Fig. 3-12 Simulated analog frequency tuning range of DCO
SS80 FF0
TT27
Fig. 3-13 Simulated phase noise of the DCO under different corners
Table 3-4 Simulated characteristics of the DCO @ TT27 o
Item Value
Supply Voltage 0.5 V
Current 453 A
Oscillation frequency 435 MHz Phase Noise at 1 MHz -110 dBc/Hz
Digital Control bits 4 bits
Total Tuning Range 60 MHz
3.4 Simulation Results Fig. 3-14 Simplified baseband circuit
Fig. 3-14 shows the baseband circuits including an envelope detector and a data slicer. The envelope detector is realized as an active rectifier which feeds the data slicer to generate the raw data [28]. Since the envelope peak and valley levels will vary due to PVT variations, the threshold voltage of the slicer must be adaptively adjusted. This threshold voltage is generated by a low pass filter which has the ability to capture DC point of envelope waveform.
3.4 Simulation Results
The simulation results for total system are shown in Fig. 3-15 for the verification of theory analyzed in Chapter 3.1.2.
The data rate is 10 Mbps and the receiver demodulate D-BPSK encoded data to RZ data with input power is equal to -70 dBm.
Chapter 3 Proposed Low-Power Injection-Locked D-BPSK Receiver
34
Matching
Network ILO
AMPout
RFIN
Envelope Detector
LNA AMP Data
Slicer ILOout EDout RXout
DPSK code
AMPout
ILOout
EDout
RXout
Fig. 3-15 Time diagram of Proposed RX
3.5 Experimental Results
3.5.1 Die Photo
This chip is fabricated in TSMC 0.18-μm CMOS 1P6M process and occupies a core area of 5.4 mm2. As shown in Fig. 3-16, the whole system is divided into several blocks: low noise amplifier, injection-locked DCO, an envelope detector, and data slicer for producing RX output digital signal. Excepting for a 0.9-V supply used by output buffer for sufficient driving requirement of measurement, the supply for all the other blocks is 0.5 V. Besides, STC I/O PADS are applied to the interfaces of this die for ESD protection.
3.5 Experimental Results
3.5.2 Measurement Environment Setup
PCB
Fig. 3-17 Measurement Environment
The measurement environment setup is depicted in Fig. 3-17. Agilent E3646A power supply provides the dc supply for the LDO regulators which supply steady dc voltages on PCB. The network analyzer Agilent E5071C is utilized to measure the s-parameter of LNA, and oscilloscope is used for observing time-domain data.
Chapter 3 Proposed Low-Power Injection-Locked D-BPSK Receiver
36
Moreover, signal analyzer Agilent N9020A measures the performance of DCO and the vector-signal generator Agilent E4438C provides D-BPSK modulation signal for testing.
3.5.3 PCB Design
A PCB is fabricated for testing and verifying the function of the proposed D-BPSK receiver, as shown in Fig. 3-18. There are two power domains on this PCB: a 0.9-V supply for supplying digital buffer, and a 0.5-V supply for core circuit. The 5-bit controlling signal tunes DCO free-run frequency. AC input/output signals, such as LNA output signal, input D-BPSK signal,, and DCO output signal, are connected through SMA terminals. The LNA matching network, composed of shunt capacitor and series inductor, is also welded on board.
Fig. 3-18 PCB for Testing
3.5 Experimental Results
3.5.4 Measured Results
Fig. 3-19 shows the input-matching measurement for D-BPSK receiver with S11 is about -23.4 dB at 417MHz, and the bandwidth is larger than 10MHz.
30
410 420 430 440 450 400
380 390 370
10MHz
S11 (dB)
Fig. 3-19 Measured S11 Parameter
The measured phase noise of free-running DCO and injection-locked DCO are displayed in Fig. 3-20. As shown in the figure, the phase noise for injection-locked DCO is -91 dBc/Hz, -100 dBc/Hz, -111 dBc/Hz, and -114 dBc/Hz at frequency offset of 10 kHz, 100 kHz,1 MHz, and 10MHz. This measurement indicates that DCO phase noise is significantly improved by injection-locking technique.
The transmitted data generated from Agilent E4438C is in differentially encoded form. The ILO output experiences amplitude variation during every data transition of transmitted data. With the envelope detector and data slicer, the analog amplitude information is converted to a sequence of digital code, which is RZ data of RX output.
For example, a sequence “01010101000000” is differentially encoded to
Chapter 3 Proposed Low-Power Injection-Locked D-BPSK Receiver
38
“110011001111111”, and this transmitted data is demodulated successfully with timing delay as shown in Fig. 3-21.
Fig. 3-22 depicted the measured relationship between bit error rate (BER) and input power, which indicate that the sensitivity is -45dBm at 10-Mbps.
-40
Fig. 3-20 Measured DCO Phase Noise
Transmitted data
Fig. 3-21 Transient waveforms at 10-Mbps (Input power is -40 dBm)
3.5 Experimental Results
Input power(dBm)
Bit error rate (BER)
10-3 10-1
10-2
10-4
-55 -50 -45 -40
Fig. 3-22 BER Versus Input Power at 10-Mbps
Table 3-5 shows the detailed power breakdown of the proposed receiver. The total power consumption is 970 μW. Half of the power consumption is contributed by the RF front-end circuit. The baseband circuit ( ED + Data Slicer) only consumes 45 μW.
Table 3-5 Power Breakdown of the D-BPSK RX
Circuit Power (μW)
LNA+AMP 690
DCO 235
ED 40
Data Slicer 5
Total 970
Finally, Table 3-6 summarizes the performances of the proposed RX. By the comparison between the related works, it concludes that we proposed an ultra-low-voltage receiver with good energy efficiency.
Chapter 3 Proposed Low-Power Injection-Locked D-BPSK Receiver
40
Table 3-6 Comparison Table of the Proposed RX
Reference [9]
VLSI’14
[19]
T-MTT’11
[29]
BioCAS’11
[30]
ISOCC’14
This Work Technology
(nm) 180 90 180 110 180
Supply
(V) 0.9 1.2 1.8 1.2 0.5
Modulation D-BPSK BFSK OOK OOK D-BPSK
Freq. Band
(MHz) 430 300 400 433 414 ~ 454
Data Rate
(Mbps) 10 1 2 2 10
Power Con.
(μW) 1770 120 590 750 970
Sensitivity
(dBm) -63 -34 -45 -50 -45
Energy/bit
(pJ/bit) 177 120 295 375 97
4.1 Transmitter Introduction
Chapter 4 Proposed Low-Power Injection-Locked D-BPSK Transmitter
4.1 Transmitter Introduction
4.1.1 Motivation
As discussed in Chapter 2.3 that many transmitters were published for low-power application. However energy-efficient transmitters with high data rate are much desired for short-range IoT applications in the future. Traditional injection-locked transmitter with edge-combing technique provides proper choice [21][22].
Nevertheless, the mismatch of edge combiner induces the spur issue in spectrum. To sum up, a low-power high-data-rate transmitter is needed to be proposed for addressing these issue.
4.1.2 Sub-harmonic injection-locked oscillator as phase modulator
The sub-harmonic injection-locked oscillator plays an important role on low-power transmitters. As depicted in Fig.4-1, the output phase noise of sub-harmonic injection-locked oscillator is dominated by that of input signal, where N is the frequency ratio between injection signal and free-running oscillator.
The equation (4-1) reveals that the phase-noise performance of the free-running DCO is not significantly important. However it depends on the phase-noise performance of input signal. According to the analysis in [23], the output phase noise of sub-harmonically injection-locked VCO is expressed in (4-1).
Chapter 4 Proposed Low-Power Injection-Locked D-BPSK Transmitter
42
Fig. 4-1 Phase-Noise Behavior of a Sub-harmonically Injection-Locked VCO 20log
out inj
L L N (4-1)
When sub-harmonic injection-locked oscillator is locked and return to steady state, the frequency of oscillator will oscillate at N times of the frequency of input injected signal. The relationship between phase and injected frequency is shown in (4-2). SS is steady-state phase difference between input signal and oscillator signal, L is locking range and osc is free-running frequency. It reveals that phase difference is constant if the free-running frequency of oscillator is equal to N times input frequency of injected signal [26]. In other word, the phase of oscillator will track that of input injected signal when returning steady state.
1( osc inj)
This property indicates that the phase modulator can be accomplished by a simple sub-harmonic injection-locked oscillator.
Assume the frequency ratio between injected frequency and oscillation frequency is an integer N. Equation (4-3) is derived for the phase relationship of oscillator and injected signal [23]. The change of phase for sub-harmonic injection-locked oscillator is N times the change of phase of input injected signal.
osc N inj
4.2 System Architecture
For an odd number N and assume only two phases, 0゜and 180゜, for injected signal, the equation (4-3) can be rewritten to (4-4).
0 , 0 modulate the high frequency oscillator rather than generating multi-phase oscillator for BPSK modulation at RF frequency.
Fig. 4-2 displays the operating principle of BPSK modulation. (Iinj,0) and (Iinj, ) represent 0゜phase for symbol “0” and 180゜phase for symbol “1” from baseband injected frequency. For transmitting symbol “0” , a 0゜input signal (right short solid line) is injected and the oscillator is locked to the same phase (right long solid line); on the other hand, the 180゜input signal (left short dash line) is injected to drive oscillator to 180゜phase (left long dash line) if transmitter delivers symbol “1”.
Iosc
Fig. 4-2 The diagram of phase modulation by sub-harmonic injection technique
4.2 System Architecture
4.2.1 The Proposed D-BPSK Transmitter
The proposed architecture of the DPSK transmitter, as shown in Fig. 4-3, is composed of a single-to-differential buffer, a multiplexer (MUX), a pulse generator, an
Chapter 4 Proposed Low-Power Injection-Locked D-BPSK Transmitter
44
injection-locked ring oscillator (ILO), a PA, and a baseband circuit for D-BPSK encoding.
The single-to-differential buffer produces multi-phase information for MUX.
Before injecting to the ILO, the signal is passing through the pulse generator for optimizing injection strength. The baseband circuit generates digital data to drive MUX and select correct phase signal. Therefore, the sub-harmonically injection-locked ring oscillator performs phase modulation. That is the the phase of ILO depends on the phase of injected signal as discussed in Chapter 4.1.2. Finally, power amplifier transmitted the modulated RF signal to output.
Matching
Fig. 4-3 Proposed DPSK Transmitter with Sub-harmonic Injection-Locked Modulation
4.2.2 Design Specifications of the Proposed Transmitter
Error vector magnitude (EVM) is defined as the deviation of the constellation points from their ideal positions [11].
The magnitude deviation ( A M
D ) is small enough to be neglected when comparing
with phase deviation in this work, the relationship between EVM and phase error can be expressed in (4-5) according to [32].
4.2 System Architecture sub-harmonically injection-locked technique. As analyzed in Chapter 4.1.2, there’s no phase error if the free-running frequency of oscillator is equal to N times input frequency of injected signal in ideal environment. However, the frequency mismatch due to the non-ideal effect in real circuit will induce the periodic phase error.
Equation (4-6) shows the connection between EVM and frequency deviation Df, center frequency f0 and N is the sub-harmonic injection ratio which affects the performance of EVM significantly [31].
2The improvement of EVM is by setting N as small as possible. However, it means that most circuit blocks operating at higher frequency, which consumes more power.
That is to say, there is a trade-off lying between power and EVM. Therefore, the sub-harmonic injection ratio N is designed to be 9 in this proposed architecture.
To substitute the design parameter f0 = 430 MHz, N is 9 and assume the worst frequency deviation Df is 100 kHz , the EVM is smaller than 1% which obeys the specification for this target.
The injection spurs resulting from sub-harmonic injection-locked technique are discussed at [31], and (4-7) shows the connection to design parameter. The performance of spurs also depends on the sub-harmonic injection ratio.
Chapter 4 Proposed Low-Power Injection-Locked D-BPSK Transmitter
Another significant specification is maximum data rate which is dominated by locking range L as discussed in Chapter 3.2.2. According to (3-14), the locking range
L of ILO must be larger than 2*6.366 MHz if maximum data rate is 10 Mbps. This requirement of locking range for ring oscillator isn’t a tight specification for transmitter.
The injection strength not only depends on the amplitude of injected signal but also the pulse width. In this system, the pulse width is only the designed parameter because the amplitude is rail to rail swing which is limited by voltage supply (0.5V).
Equation (4-8) shows the Fourier transform for a pulse with pulse width W=
D T INJ, which D is duty cycle for injected signal whose period is TINJ, and KN represents the injection strength.
( )
N, the sub-harmonic injection ratio is 9, and the maximum injection strength K9 is obtained by setting duty cycle D is 1/18. It is the optimum value of pulse width for sub-harmonic injection oscillator.
To sum up, the maximum data rate determines the locking range of sub-harmonic injected oscillator. Not only EVM but also spur is affected by the sub-harmonic injection ratio mainly. Moreover, the injected pulse width is required to be designed carefully for maximum injection strength. Above analysis provides insights into the design of TX system. Finally, the specification of this work is shown in Table 4-1.
4.3 Circuit Implementation
Table 4-1 Designing Specifications of D-BPSK Transmitter
Process TSMC 0.18-m CMOS
Supply Voltage 0.5 V
Operating Frequency 414 ~ 457 MHz
Max Data Rate 10 Mbps
Pout >-10 dBm
Modulation D-BPSK
Power Consumption < 0.3 mW Energy Efficiency < 30 pJ/b
4.3 Circuit Implementation
4.3.1 Pulse Generator
CKINJ
CK’
VINJ
t Vbody
Time delay Circuit
CKINJ VINJ
CK’
CKDelay
CKDelay
Fig. 4-4 Pulse Generator
Chapter 4 Proposed Low-Power Injection-Locked D-BPSK Transmitter
48
A pulse generator which is depicted in Fig. 4-4 is adopted for generating optimum injected pulse width from an external clock reference (CKINJ) as mentioned in Chapter 4.2.2. The pulse width of the pulse generator can be tuned through modifying the time delay circuit with body-bias technique, and Fig. 4-5 displays the tuning range of pulse width, and the range is from 400 ps to 2.3 ns at different corner conditions.
SS80
Fig. 4-5 The pulse width tuning range
4.3.2 Sub-harmonically Injection-Locked Ring DCO
Fig. 4-6 displays a 3-stage sub-harmonically single-ended injection-locked ring DCO in this work. The injection-locking technique is realized by shorting one of the stages to ground through an NMOS, and this would make the transition edge of VOSC
align with that of VINJ. The output phase noise performance of a ring DCO can be improved effectively with sub-harmonic injection-locked technique as discussed in Chapter 4.1.2.
4.3 Circuit Implementation
VINJ
Vosc
C<2:0>
Digital Control
Vbody Analog Control
Fig. 4-6 Single-ended Sub-harmonic Injection-Locked Ring Oscillator
Fig. 4-7 Simulated Phase Noise of Ring Oscillator (Carrier@430MHz)
Fig. 4-7 displays the simulated phase noise of the single-ended injection-locked ring DCO under free-run conditions, and it is simulated under TT corner with 27°
Chapter 4 Proposed Low-Power Injection-Locked D-BPSK Transmitter
50
temperature. As the figure shows, the phase noise for free-run DCO is -18.58 dBc/Hz, -47.5 dBc/Hz, -75.4 dBc/Hz, and -99.57 dBc/Hz at frequency offset of 10 kHz, 100 kHz,1 MHz, and 10MHz. Table 4-2 summaries the simulated characteristic of the DCO.
Table 4-2 Simulated characteristics of the DCO @ TT27 o
Item Value
Supply Voltage 0.5 V
Current 198 A
Oscillation frequency 435 MHz Phase Noise at 1 MHz -99 dBc/Hz
Digital Control bits 3 bits
Total Tuning Range 70 MHz
4.3.3 Power Amplifier
To achieve low-power operation, the class-E power amplifier is adopted in ultra-low power supply (0.5V). An inverter inserted between DCO and PA acts as a buffer for the purpose of isolation. The detailed circuit implementation with the output impedance transformation is shown in Fig. 4-8.
The output 50-ohm matching at TXOUT is accomplished by the tapped matching work which is composed of the choke inductor L and capacitors C1, C2.. Assume the quality factor Q of inductor L is larger than 10, then the following approximation establishes the impedance transformation in equation (4-9), where RL is output loading whose value is usually 50-ohm.
4.3 Circuit Implementation
Fig. 4-8 Class-E Power Amplifier and Output Impedance Transformation Network
L
The tapped output matching network is simplified as a LC tank. The DC current (IPA) required for a certain PA output power can be approximately estimated as
Chapter 4 Proposed Low-Power Injection-Locked D-BPSK Transmitter
52
-40dBm as discussed in Chapter 4.1.2. Table 4-3 summaries the simulated characteristic of the PA.
Fig. 4-9 PA Output Spectrum with injected signal Table 4-3 Simulated characteristics of the PA @ TT27 o
Item Value
Supply Voltage 0.5 V
Current 295 A
Oscillation frequency 435 MHz
Max Pout -9.7dBm
Efficiency 62.5%
4.4 System Simulation Results
4.4 System Simulation Results
The system simulation results displayed in Fig. 4-10 verifies the sub-harmonic injected-locked modulation technique.
Fig. 4-10 Timing diagram of Proposed TX
4.5 Experimental Results
4.5.1 Die Photo
This chip is fabricated in TSMC 0.18-μm CMOS 1P6M process and occupies a core area of 0.8 mm2. As shown in Fig. 4-11, the whole system is divided into several blocks: baseband circuit, injection-locked DCO, a pulse generator, and a power amplifier for transmitting TX output signal. The supply voltage for all blocks is 0.5 V.